Commit 113c604e authored by Tanfer's avatar Tanfer
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% "Probability-Driven Evaluation of Lower-Part Approximation Adders" on IEEE TCAS II
% Tanfer Alan @ CES - KIT Germany
function [ output_args ] = eta_uniform_quick( input_args )
% Expected Value of Error
% Model of Error Tolerant Adder (ETA) from
%N. Zhu, W. L. Goh, and K. S. Yeo, “An enhanced low-power high-speed adder
%for error-tolerant application,” in Integrated Circuits, ISIC’09. Proceedings of the
%2009 12th International Symposium on. IEEE, 2009, pp. 69–72.
k=16;
tic %Experiment Timer-Start
for d = 1:k;
temp(d) = (1/4)* ( ((3/4)^(k-d)) * 2^(d-1));
end
eta_error_uniform = sum(temp)
toc %Experiment Timer-Stop
end
% "Probability-Driven Evaluation of Lower-Part Approximation Adders" on IEEE TCAS II
% Tanfer Alan @ CES - KIT Germany
%
% Lower-part approximation adders binary behavioral models
% -this script is called by the main file, MonteCarlo_RUN
function [ ea_trunc, ea_copy, ea_shiftcopy, ea_loa, ea_lxoa, ea_eta ] = monteCarloGatesAuto( abW )
bW = 36; % Total Bit Width of the Adder including accurate and approximate parts
experiment_length = 1000; % PARAMETER: Monte Carlo simulation steps / 100.000 in paper
ea_trunc = 0;
ea_copy = 0;
ea_loa = 0;
ea_lxoa = 0;
ea_eta = 0;
for c = 1:experiment_length;
OPa=(floor((2^bW)*rand)); %Generate Operands 1,2
OPb=(floor((2^bW)*rand));
OPa2=de2bi(OPa,bW); %Binary represtation of operands
OPb2=de2bi(OPb,bW);
exactsum(c) = OPa+OPb; %Exact addition
truncsum(c) = bi2de(OPa2&[zeros(1,abW),ones(1,bW-abW)])+bi2de(OPb2&[zeros(1,abW),ones(1,bW-abW)]);
copysum(c) = bi2de(de2bi(truncsum(c),bW+1)| [OPa2(1:abW),zeros(1,bW+1-abW)]); % copy operand1
shiftcopy(c) = bi2de(de2bi(truncsum(c),bW+1)| [1, OPa2(1:abW-1),zeros(1,bW+1-abW)]); % shift_copy operand1
% LOA start
temp_loa1 = OPa2(abW)&OPb2(abW); % LOA-to-Accurate Carry-in
temp_loa2 = [zeros(1,abW),temp_loa1,zeros(1,bW-abW-2)];
loa(c) = bi2de(de2bi((truncsum(c)+bi2de(temp_loa2)),bW+1)| [OPa2(1:abW)|OPb2(1:abW),zeros(1,bW+1-abW)]);
% LOA end
% LXOA start
trunc2 = bi2de(OPa2&[zeros(1,abW-1),ones(1,bW-abW+1)])+bi2de(OPb2&[zeros(1,abW-1),ones(1,bW-abW+1)]);
trunc3 = de2bi(trunc2,bW+1);
lxoa(c) = bi2de(trunc3 | [(OPa2(1:abW-1)|OPb2(1:abW-1)),zeros(1,bW+2-abW)]);
% LXOA end
% ETA start
tempc = zeros(1,abW);
for ceta = 1:abW
tempc(ceta) =OPa2(ceta) + OPb2(ceta);
eta_con = (OPa2(ceta)&OPb2(ceta));
tempc= (eta_con==1).*[ones(1,ceta), zeros(1,abW-ceta)] + ~(eta_con==1).*tempc ;
end
eta(c) = truncsum(c) + bi2de(tempc);
% ETA end
error_trunc(c) = exactsum(c) - truncsum(c);
error_copysum(c) = exactsum(c) - copysum(c);
error_shiftcopy(c) = exactsum(c) - shiftcopy(c);
error_loa(c) = exactsum(c) - loa(c);
error_lxoa(c) = exactsum(c) - lxoa(c);
error_eta(c) = exactsum(c) - eta(c);
end % experiment_length
ea_trunc = mean(mean(error_trunc));
ea_copy = mean(mean(error_copysum));
ea_shiftcopy = mean(mean(abs(error_shiftcopy)));
ea_loa = mean(mean(abs(error_loa)));
ea_lxoa = mean(mean(abs(error_lxoa)));
ea_eta = mean(mean(abs(error_eta)));
end
% "Probability-Driven Evaluation of Lower-Part Approximation Adders" on IEEE TCAS II
% Tanfer Alan @ CES - KIT Germany
%
% Main file for Monte-Carlo simulation of lower-part approximation adders
% -requires the script: MonteCarloGates
function [ output_args ] = monteCarloRun( input_args )
tic %Experiment Timer-Start
for abW = 1:16; % PARAMETER: Approximate Bit-Width Sweep
[ ea_trunc(abW), ea_copy(abW), ea_shiftcopy(abW), ea_loa(abW), ea_lxoa(abW), ea_eta(abW) ] = MonteCarloGates( abW );
abW
end
toc %Experiment Timer-Stop
figure; semilogy(ea_trunc);
hold on
semilogy(ea_copy);
semilogy(ea_shiftcopy);
semilogy(ea_loa);
semilogy(ea_eta);
semilogy(ea_lxoa);
grid on;
end
// Unsigned Carry-Lookahead Adder 32 Bit
// Accurate
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module cla32(A,B,C0,S,C32)
input [31:0] A,B;
input C0;
output [31:0] S;
output C32;
reg [31:0] S;
reg [32:0] C;
integer i;
always @* begin
C[0] <= C0;
for (i=0; i<32; i=i+1) begin
S[i] <= A[i] ^ B[i] ^ C[i];
C[i+1] <= ( A[i] & B[i] ) | ( A[i] & C[i] ) | ( B[i] & C[i] );
end
end
assign C32 = C[32];
endmodule
// Unsigned Carry-Lookahead Adder 32 Bit
// Lower Part Approximation with ETA, Zhu@ISIC2009
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module cla32_eta(A,B,C0,S,C32);
parameter k = 2;//PARAMETER: Approximate bits
input [31:0] A,B;
input C0; //left-open
output [31:0] S;
output C32;
reg [31:0] S;
reg [32:0] C;
wire [k-1:0] ctrl;
integer i;
genvar j;
assign ctrl[k-1] = (A[k-1] & B[k-1]);
generate
for (j=k-2; j>=0; j=j-1) begin
assign ctrl[j] = ((A[j] & B[j] ==1)|(ctrl[j+1]==1)) ? 1:0;
end
endgenerate
always @* begin
S[k-1:0] <= (A[k-1:0]^B[k-1:0])|ctrl[k-1:0];
C[k] <= 0;
for (i=k; i<32; i=i+1) begin
S[i] <= A[i] ^ B[i] ^ C[i];
C[i+1] <= ( A[i] & B[i] ) | ( A[i] & C[i] ) | ( B[i] & C[i] );
end
end
assign C32 = C[32];
endmodule
// Unsigned Carry-Lookahead Adder 32 Bit
// Lower Part Approximation with LOA, Mahdiani@TCAS-I--2010
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module cla32_loa(A,B,C0,S,C32);
parameter k = 4;//PARAMETER: Approximate bits
input [31:0] A,B;
input C0; //left-open
output [31:0] S;
output C32;
reg [31:0] S;
reg [32:0] C;
integer i;
always @* begin
S[k-1:0] <= A[k-1:0]|B[k-1:0]; //Lower Part OR Gate - Approximation
C[k] <= A[k-1]&B[k-1]; //Carry-in
for (i=k; i<32; i=i+1) begin
S[i] <= A[i] ^ B[i] ^ C[i];
C[i+1] <= ( A[i] & B[i] ) | ( A[i] & C[i] ) | ( B[i] & C[i] );
end
end
assign C32 = C[32];
endmodule
// Unsigned Carry-Lookahead Adder 32 Bit
// Lower Part Approximation with LXOA, Albicocco@ASILOMAR2012
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module cla32_lxoa(A,B,C0,S,C32);
parameter k = 2;//PARAMETER: Approximate bits
input [31:0] A,B;
input C0; //left-open
output [31:0] S;
output C32;
reg [31:0] S;
reg [32:0] C;
integer i;
always @* begin
S[k-2:0] <= A[k-2:0]|B[k-2:0]; //Lower Part OR Gate - Approximation
S[k-1] <= A[k-1]^B[k-1]; //Half-Adder
C[k] <= A[k-1]&B[k-1]; //Half-Adder
for (i=k; i<32; i=i+1) begin
S[i] <= A[i] ^ B[i] ^ C[i];
C[i+1] <= ( A[i] & B[i] ) | ( A[i] & C[i] ) | ( B[i] & C[i] );
end
end
assign C32 = C[32];
endmodule
// Unsigned Carry-Lookahead Adder 32 Bit
// Lower Part Approximation by truncation
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module cla32_trunc(A,B,C0,S,C32);
parameter k = 2;//PARAMETER: Approximate bits
input [31:0] A,B;
input C0; //left-open
output [31:0] S;
output C32;
reg [31:0] S;
reg [32:0] C;
integer i;
always @* begin
S[k-1:0] <= {(k-1){1'b0}}; //Lower Part Truncate
C[k] <= 0;
for (i=k; i<32; i=i+1) begin
S[i] <= A[i] ^ B[i] ^ C[i];
C[i+1] <= ( A[i] & B[i] ) | ( A[i] & C[i] ) | ( B[i] & C[i] );
end
end
assign C32 = C[32];
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Kogge-Stone Adder (unsigned) - Verilog ////
//// ////
//// Author: Tanfer Alan ////
//// @ CES - KIT 2016 ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// If you use the verilog code, please cite [1] or [2]:
// [1] Tanfer Alan and Jörg Henkel. "Slackhammer: Logic synthesis for graceful errors under frequency scaling." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37.11 (2018): 2802-2811.
// [2] Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module ks_nbits(A,B,S,Cout );
parameter bit_width = 4;
parameter radix = 2;
input wire [bit_width-1:0] A;
input wire [bit_width-1:0] B;
wire [bit_width-1:0] P,G,P2,G2,P3,G3;
wire [bit_width-1:0] Ci;
output wire [bit_width-1:0] S;
wire Cin = 0;
output wire Cout;
genvar c;
assign G = A&B;
assign P = A^B;
assign P2[0] = P[0];
assign G2[0] = G[0];
for (c = 1; c <bit_width; c=c+1) begin
assign P2[c] = P[c]&&P[c-1];
assign G2[c] = (P[c]&&G[c-1])|G[c];
end
for (c = 0; c <bit_width; c=c+1) begin
assign P3[c] = P2[c]&((c-2)>=0 ? P2[c-2] : 1);
assign G3[c] = (P2[c]&((c-2)>=0 ? G2[c-2] : 0))|G2[c];
end
assign Ci = G3;
assign S[0] = P[0]^Cin;
assign S[bit_width-1:1] = P[bit_width-1:1]^Ci[bit_width-2:0];
assign Cout = Ci[bit_width-1];
endmodule
// 32-bit Kogge-Stone Adder with radixes 4-4-2 (for the final stage)
// Lower Part Approximation with ETA, Zhu@ISIC2009
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module ks32_eta(A_in,B_in,S,Cout );
parameter k = 2; //PARAMETER: Approximate bits
parameter in_width = 32;
parameter bit_width = 32-k;
parameter radix = 4;
input wire [in_width-1:0] A_in;
input wire [in_width-1:0] B_in;
output wire [in_width-1:0] S;
output wire Cout;
// ETA PART
genvar j;
wire [k-1:0] ctrl;
assign ctrl[k-1] = (A_in[k-1] & B_in[k-1]);
generate
for (j=k-2; j>=0; j=j-1) begin
assign ctrl[j] = ((A_in[j] & B_in[j] ==1)|(ctrl[j+1]==1)) ? 1:0;
end
endgenerate
// END ETA
assign S[k-1:0] = (A_in[k-1:0]^B_in[k-1:0])|ctrl[k-1:0];
wire Cin = 0;
wire [bit_width-1:0] A = A_in[in_width-1:k];
wire [bit_width-1:0] B = B_in[in_width-1:k];
wire [bit_width-1:0] P,G,P2,G2,P3,G3,P4,G4;
wire [bit_width-1:0] Ci;
wire [bit_width-1:0] S_ks;
genvar c;
assign G = A&B;
assign P = A^B;
for (c = 0; c <bit_width; c=c+1) begin
assign P2[c] = P[c]&((c-1)>=0 ? P[c-1] : 1)&((c-2)>=0 ? P[c-2] : 1)&((c-3)>=0 ? P[c-3] : 1);
assign G2[c] = (P[c]&(((c-1)>=0 ? G[c-1] : 0)|((c-2)>=0 ? P[c-1]&G[c-2] : 0)|((c-3)>=0 ? P[c-1]&P[c-2]&G[c-3] : 0)))|G[c];
end
for (c = 0; c <bit_width; c=c+1) begin
assign P3[c] = P2[c]&((c-4)>=0 ? P2[c-4] : 1)&((c-8)>=0 ? P2[c-8] : 1)&((c-12)>=0 ? P2[c-12] : 1);
assign G3[c] = (P2[c]&(((c-4)>=0 ? G2[c-4] : 0)|((c-8)>=0 ? P2[c-4]&G2[c-8] : 0)|((c-12)>=0 ? P2[c-4]&P2[c-8]&G2[c-12] : 0)))|G2[c];
end
for (c = 0; c <bit_width; c=c+1) begin
// assign P4[c] = P3[c]&((c-16)>=0 ? P3[c-16] : 1)&((c-32)>=0 ? P3[c-32] : 1)&((c-48)>=0 ? P3[c-48] : 1);
assign G4[c] = (P3[c]&(((c-16)>=0 ? G3[c-16] : 0)|((c-32)>=0 ? P3[c-16]&G3[c-32] : 0)|((c-48)>=0 ? P3[c-16]&P3[c-32]&G3[c-48] : 0)))|G3[c];
end
assign Ci = G4;
assign S_ks[0] = P[0]^Cin;
assign S_ks[bit_width-1:1] = P[bit_width-1:1]^Ci[bit_width-2:0];
assign Cout = Ci[bit_width-1];
assign S[in_width-1:k] = S_ks;
endmodule
// 32-bit Kogge-Stone Adder with radixes 4-4-2 (for the final stage)
// Lower Part Approximation with LOA, Mahdiani@TCAS-I--2010
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module ks32_loa(A_in,B_in,S,Cout );
parameter k = 6; //PARAMETER: Approximate bits
parameter in_width = 32;
parameter bit_width = 32-k;
parameter radix = 4;
input wire [in_width-1:0] A_in;
input wire [in_width-1:0] B_in;
output wire [in_width-1:0] S;
output wire Cout;
assign S[k-1:0] = A_in[k-1:0]|B_in[k-1:0];
wire Cin = A_in[k-1]&B_in[k-1];
wire [bit_width-1:0] A = A_in[in_width-1:k];
wire [bit_width-1:0] B = B_in[in_width-1:k];
wire [bit_width-1:0] P,G,P2,G2,P3,G3,P4,G4;
wire [bit_width-1:0] Ci;
wire [bit_width-1:0] S_ks;
genvar c;
assign G = A&B;
assign P = A^B;
for (c = 0; c <bit_width; c=c+1) begin
assign P2[c] = P[c]&((c-1)>=0 ? P[c-1] : 1)&((c-2)>=0 ? P[c-2] : 1)&((c-3)>=0 ? P[c-3] : 1);
assign G2[c] = (P[c]&(((c-1)>=0 ? G[c-1] : 0)|((c-2)>=0 ? P[c-1]&G[c-2] : 0)|((c-3)>=0 ? P[c-1]&P[c-2]&G[c-3] : 0)))|G[c];
end
for (c = 0; c <bit_width; c=c+1) begin
assign P3[c] = P2[c]&((c-4)>=0 ? P2[c-4] : 1)&((c-8)>=0 ? P2[c-8] : 1)&((c-12)>=0 ? P2[c-12] : 1);
assign G3[c] = (P2[c]&(((c-4)>=0 ? G2[c-4] : 0)|((c-8)>=0 ? P2[c-4]&G2[c-8] : 0)|((c-12)>=0 ? P2[c-4]&P2[c-8]&G2[c-12] : 0)))|G2[c];
end
for (c = 0; c <bit_width; c=c+1) begin
// assign P4[c] = P3[c]&((c-16)>=0 ? P3[c-16] : 1)&((c-32)>=0 ? P3[c-32] : 1)&((c-48)>=0 ? P3[c-48] : 1);
assign G4[c] = (P3[c]&(((c-16)>=0 ? G3[c-16] : 0)|((c-32)>=0 ? P3[c-16]&G3[c-32] : 0)|((c-48)>=0 ? P3[c-16]&P3[c-32]&G3[c-48] : 0)))|G3[c];
end
assign Ci = G4;
assign S_ks[0] = P[0]^Cin;
assign S_ks[bit_width-1:1] = P[bit_width-1:1]^Ci[bit_width-2:0];
assign Cout = Ci[bit_width-1];
assign S[in_width-1:k] = S_ks;
endmodule
// 32-bit Kogge-Stone Adder with radixes 4-4-2 (for the final stage)
// Lower Part Approximation with LXOA, Albicocco@ASILOMAR2012
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//----------------------------------------------------------------------------------------------------
module ks32_lxoa(A_in,B_in,S,Cout );
parameter k = 2; //PARAMETER: Approximate bits
parameter in_width = 32;
parameter bit_width = 32-k;
parameter radix = 4;
input wire [in_width-1:0] A_in;
input wire [in_width-1:0] B_in;
output wire [in_width-1:0] S;
output wire Cout;
assign S[k-2:0] = A_in[k-2:0]|B_in[k-2:0];
assign S[k-1] = A_in[k-1]^B_in[k-1];
wire Cin = A_in[k-1]&B_in[k-1];
wire [bit_width-1:0] A = A_in[in_width-1:k];
wire [bit_width-1:0] B = B_in[in_width-1:k];
wire [bit_width-1:0] P,G,P2,G2,P3,G3,P4,G4;
wire [bit_width-1:0] Ci;
wire [bit_width-1:0] S_ks;
genvar c;
assign G = A&B;
assign P = A^B;
for (c = 0; c <bit_width; c=c+1) begin
assign P2[c] = P[c]&((c-1)>=0 ? P[c-1] : 1)&((c-2)>=0 ? P[c-2] : 1)&((c-3)>=0 ? P[c-3] : 1);
assign G2[c] = (P[c]&(((c-1)>=0 ? G[c-1] : 0)|((c-2)>=0 ? P[c-1]&G[c-2] : 0)|((c-3)>=0 ? P[c-1]&P[c-2]&G[c-3] : 0)))|G[c];
end
for (c = 0; c <bit_width; c=c+1) begin
assign P3[c] = P2[c]&((c-4)>=0 ? P2[c-4] : 1)&((c-8)>=0 ? P2[c-8] : 1)&((c-12)>=0 ? P2[c-12] : 1);
assign G3[c] = (P2[c]&(((c-4)>=0 ? G2[c-4] : 0)|((c-8)>=0 ? P2[c-4]&G2[c-8] : 0)|((c-12)>=0 ? P2[c-4]&P2[c-8]&G2[c-12] : 0)))|G2[c];
end
for (c = 0; c <bit_width; c=c+1) begin
// assign P4[c] = P3[c]&((c-16)>=0 ? P3[c-16] : 1)&((c-32)>=0 ? P3[c-32] : 1)&((c-48)>=0 ? P3[c-48] : 1);
assign G4[c] = (P3[c]&(((c-16)>=0 ? G3[c-16] : 0)|((c-32)>=0 ? P3[c-16]&G3[c-32] : 0)|((c-48)>=0 ? P3[c-16]&P3[c-32]&G3[c-48] : 0)))|G3[c];
end
assign Ci = G4;
assign S_ks[0] = P[0]^Cin;
assign S_ks[bit_width-1:1] = P[bit_width-1:1]^Ci[bit_width-2:0];
assign Cout = Ci[bit_width-1];
assign S[in_width-1:k] = S_ks;
endmodule
// 32-bit Kogge-Stone Adder with radixes 4-4-2 (for the final stage)
// Lower Part Approximation by truncation
//
// Tanfer Alan - 2016 KIT|CES Germany
//
// If you use the verilog code, please cite:
// Tanfer Alan and Jörg Henkel. "Probability-Driven Evaluation of Lower-Part Approximation Adders" IEEE Transactions on Circuits and Systems II: Express Briefs (2021).
//---------------------
module ks32_trunc(A_in,B_in,S,Cout );
parameter k = 6; //PARAMETER: Approximate bits
parameter in_width = 32;
parameter bit_width = 32-k;
parameter radix = 4;
input wire [in_width-1:0] A_in;