Commit e7afd19b authored by marvin.damschen's avatar marvin.damschen Committed by Marvin Damschen
Browse files

Implement partial reconfiguration synthesis flow including LED example for VC707

- add simple led example and pblock

- add synthesis of pr instances with example of second leds_ctrl

- add forgotten xilinx-vc707-xc7vx485t.xdc

- first version of partial flow, update led example

- generate full and partial bitstreams for two (led_ctrl) configurations

- generate *.h of partial bitstreams

- minor build.sh cleanup
parent 6d999ff9
......@@ -2,7 +2,7 @@
source /home/adm/xilinx_2014.4_64bit.setup # TODO adjust path to vivado 2014.4 environment
# Customize IP Cores in top
printf "customizing ip cores..."
printf "$(date +%T) - customizing ip cores..."
cd leon3-xilinx-vc707
touch wave.do # workaround to avoid warning. seems to be missing in grlilb for this board
make ip_7series_generate > /dev/null
......@@ -16,7 +16,7 @@ fi
# Begin Partial Reconfiguration Flow
cd ../pr_flow
printf "synthesizing ip cores..."
printf "$(date +%T) - synthesizing ip cores..."
mkdir -p runs/sgmii_synth
cd runs/sgmii_synth
vivado -mode batch -source ../../tcl/sgmii.tcl > /dev/null
......@@ -27,7 +27,7 @@ else
exit
fi
printf "synthesizing top..."
printf "$(date +%T) - synthesizing top..."
cd ../..
mkdir -p runs/synth
cd runs/synth
......@@ -39,11 +39,13 @@ else
exit
fi
printf "implementing top..."
printf "$(date +%T) - synthesizing instances for partial reconfiguration..."
cd ../..
mkdir -p runs/impl
cd runs/impl
vivado -mode batch -source ../../tcl/impl.tcl > /dev/null
mkdir -p runs/pr_instance_synth
mkdir -p pr_instances
cd runs/pr_instance_synth
vivado -mode batch -source ../../tcl/synth_pr_instance.tcl -tclargs leds_ctrl0 > /dev/null
vivado -mode batch -source ../../tcl/synth_pr_instance.tcl -tclargs leds_ctrl1 > /dev/null
if [ $? -eq 0 ]; then
printf "DONE\n"
else
......@@ -51,15 +53,62 @@ else
exit
fi
printf "writing bitstream for initial configuration..."
printf "$(date +%T) - implementing configuration 0..."
cd ../..
mkdir -p runs/config0
cd runs/config0
vivado -mode batch -source ../../tcl/impl.tcl > /dev/null # initial implementation with leds_ctrl0
if [ $? -eq 0 ]; then
printf "DONE\n"
else
printf "FAILED\n"
exit
fi
printf "$(date +%T) - implementing configuration 1..."
cd ../..
mkdir -p runs/config1
cd runs/config1
vivado -mode batch -source ../../tcl/config.tcl -tclargs leds_ctrl1 > /dev/null # reopens config 0's checkpoint
if [ $? -eq 0 ]; then
printf "DONE\n"
else
printf "FAILED\n"
exit
fi
printf "$(date +%T) - writing bitstreams for configuration 0..."
cd ../..
mkdir -p bitstreams
mkdir -p runs/bitstream_config0
cd runs/bitstream_config0
vivado -mode batch -source ../../tcl/bitstream0.tcl > /dev/null
vivado -mode batch -source ../../tcl/bitstream.tcl -tclargs config0 > /dev/null
# convert bitstream into ICAP compatible format
vivado -mode batch -source ../../tcl/bitstream_icap.tcl -tclargs config0_pr_leds_partial > /dev/null
cd ../..
# convert ICAP compatible bitstream into *.h for easy integration into applications
xxd -i bitstreams/config0_pr_leds_partial.bin bitstreams/config0_pr_leds_partial.h
if [ $? -eq 0 ]; then
printf "DONE\n"
else
printf "FAILED\n"
exit
fi
printf "$(date +%T) - writing bitstreams for configuration 1..."
mkdir -p runs/bitstream_config1
cd runs/bitstream_config1
vivado -mode batch -source ../../tcl/bitstream.tcl -tclargs config1 > /dev/null
# convert bitstream into ICAP compatible format
vivado -mode batch -source ../../tcl/bitstream_icap.tcl -tclargs config1_pr_leds_partial > /dev/null
cd ../..
# convert ICAP compatible bitstream into *.h for easy integration into applications
xxd -i bitstreams/config1_pr_leds_partial.bin bitstreams/config1_pr_leds_partial.h
if [ $? -eq 0 ]; then
printf "DONE\n"
else
printf "FAILED\n"
exit
fi
......@@ -103,7 +103,7 @@ entity leon3mp is
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(4 downto 0);
led : out std_logic_vector(6 downto 0);
leds : out std_logic_vector(7 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
usb_refclk_opt : in std_logic;
......@@ -135,6 +135,17 @@ end;
architecture rtl of leon3mp is
component leds_ctrl
port(
rstn : in std_ulogic;
clk : in std_ulogic;
ledso : out std_logic_vector(7 downto 0)
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of leds_ctrl_inst : label is "yes";
component sgmii_vc707
generic(
pindex : integer := 0;
......@@ -385,6 +396,8 @@ signal migrstn : std_logic;
signal cmdqu_iu_stall_reqh : std_ulogic;
--cmdqueue end
signal led : std_logic_vector(6 downto 0); -- keeps original led connections open
attribute keep : boolean;
attribute syn_keep : string;
attribute keep of clkm : signal is true;
......@@ -1109,7 +1122,7 @@ begin
end generate;
-----------------------------------------------------------------------
--- Cmdqueue Reconfiguratioin Controller -----------------------------
--- Cmdqueue Reconfiguratioin Controller & LEDs ---------------------
-----------------------------------------------------------------------
bitloadgen: if CFG_CMDQUEUE_ENABLE = 1 generate
cmdqueue : CmdQueue_TOP
......@@ -1135,6 +1148,8 @@ begin
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRUSBDC+CFG_GRUSBHC*2+CFG_GRUSB_DCL)
);
end generate;
leds_ctrl_inst: leds_ctrl port map ( rstn => rstn, clk => clkm, ledso => leds);
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
......
set_property PACKAGE_PIN AM39 [get_ports {leds[0]}]
set_property PACKAGE_PIN AN39 [get_ports {leds[1]}]
set_property PACKAGE_PIN AR37 [get_ports {leds[2]}]
set_property PACKAGE_PIN AT37 [get_ports {leds[3]}]
set_property PACKAGE_PIN AR35 [get_ports {leds[4]}]
set_property PACKAGE_PIN AP41 [get_ports {leds[5]}]
set_property PACKAGE_PIN AP42 [get_ports {leds[6]}]
set_property PACKAGE_PIN AU39 [get_ports {leds[7]}]
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity leds_ctrl0 is
generic (PRESCALER : integer := 50000000);
port ( rstn : in std_ulogic;
clk : in std_ulogic;
ledso : out std_logic_vector(7 downto 0)
);
end leds_ctrl0;
architecture Behavioral of leds_ctrl0 is
begin
shifter_right: process (clk)
variable prescale_count : integer range 0 to PRESCALER - 1 := 0;
variable led_state : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
begin
if clk'event and clk = '1' then
if prescale_count < PRESCALER - 1 then
prescale_count := prescale_count + 1;
else
prescale_count := 0;
led_state := led_state(0) & led_state(7 downto 1);
end if;
end if;
ledso <= std_logic_vector(led_state);
end process;
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity leds_ctrl1 is
generic (PRESCALER : integer := 50000000);
port ( rstn : in std_ulogic;
clk : in std_ulogic;
ledso : out std_logic_vector(7 downto 0)
);
end leds_ctrl1;
architecture Behavioral of leds_ctrl1 is
begin
shifter_left: process (clk)
variable prescale_count : integer range 0 to PRESCALER - 1 := 0;
variable led_state : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
begin
if clk'event and clk = '1' then
if prescale_count < PRESCALER - 1 then
prescale_count := prescale_count + 1;
else
prescale_count := 0;
led_state := led_state(6 downto 0) & led_state(7);
end if;
end if;
ledso <= std_logic_vector(led_state);
end process;
end Behavioral;
create_pblock pr_leds
add_cells_to_pblock [get_pblocks pr_leds] [get_cells -quiet [list {leds_ctrl_inst}]]
resize_pblock [get_pblocks pr_leds] -add {SLICE_X136Y200:SLICE_X141Y249 DSP48_X12Y80:DSP48_X12Y99}
source ../../tcl/defines.tcl
set config $argv
open_checkpoint $run_dir/impl/config0_routed.dcp
write_bitstream $bitstream_dir/config0
open_checkpoint $run_dir/$config/config_routed.dcp
write_bitstream $bitstream_dir/$config
set bitstream_dir ../../bitstreams
set config $argv
write_cfgmem -format BIN -size 256 -loadbit "up 0 $bitstream_dir/$config.bit" $bitstream_dir/$config
file delete $bitstream_dir/$config.prm
source ../../tcl/defines.tcl
set static_dcp ../config0/static_routed.dcp
set pr_instance $argv
open_checkpoint $static_dcp
read_checkpoint -cell [get_cells -hier leds_ctrl_inst] $pr_instance_dcp_dir/$pr_instance.dcp
opt_design
place_design
phys_opt_design
route_design
phys_opt_design
write_checkpoint -force config_routed.dcp
write_checkpoint -force -cell [get_cells -hier leds_ctrl_inst] $pr_instance_dcp_dir/$pr_instance.dcp
......@@ -3,9 +3,10 @@ set top leon3mp
set lib ../../../../grlib-gpl-1.4.1-b4156/lib
set ceslib ../../../../ces
set design ../../../leon3-xilinx-vc707
set atom_dcp_dir ../../atoms
set pr_instance_dcp_dir ../../pr_instances
set bitstream_dir ../../bitstreams
set run_dir ../../runs
set src_dir ../../src
set ip ../../../leon3-xilinx-vc707/vivado/leon3-xilinx-vc707/leon3-xilinx-vc707.srcs/sources_1/ip
create_project -part ${part} -in_memory
#set_property part ${part} [current_project]
......
......@@ -8,32 +8,24 @@ foreach xdc $xdcs {
read_xdc $xdc
}
#set_property HD.RECONFIGURABLE TRUE [get_cells -hier atomContainer*_inst]
set_property HD.RECONFIGURABLE TRUE [get_cells -hier leds_ctrl_inst]
#config0
#read_checkpoint -cell [get_cells -hier atomContainer2_inst] $atom_dcp_dir/fmav.dcp
#read_checkpoint -cell [get_cells -hier atomContainer3_inst] $atom_dcp_dir/fmav.dcp
#read_checkpoint -cell [get_cells -hier atomContainer4_inst] $atom_dcp_dir/fp_util.dcp
#read_checkpoint -cell [get_cells -hier atomContainer5_inst] $atom_dcp_dir/fp_div.dcp
#read_checkpoint -cell [get_cells -hier atomContainer6_inst] $atom_dcp_dir/fp_sqrt.dcp
# initial config
read_checkpoint -cell [get_cells -hier leds_ctrl_inst] $pr_instance_dcp_dir/leds_ctrl0.dcp
opt_design -directive Explore
place_design -directive Explore
phys_opt_design -directive AggressiveExplore
route_design -directive Explore -tns_cleanup
phys_opt_design -directive AggressiveExplore
opt_design
place_design
phys_opt_design
route_design
phys_opt_design
report_timing_summary
write_checkpoint -force config0_routed.dcp
write_checkpoint -force config_routed.dcp
#for {set i 2} {$i < 7} {incr i} {
# write_checkpoint -force -cell [get_cells -hier atomContainer${i}_inst] ac${i}_Sha_Full.dcp
#}
#write_checkpoint -force -cell [get_cells -hier leds_ctrl_inst] pr_leds_ctrl0.dcp
#for {set i 2} {$i < 7} {incr i} {
# update_design -cell [get_cells -hier atomContainer${i}_inst] -black_box
#}
update_design -cell [get_cells -hier leds_ctrl_inst] -black_box
lock_design -level routing
......
source ../../tcl/defines.tcl
read_vhdl -library grlib ${lib}/grlib/stdlib/version.vhd
read_vhdl -library grlib ${lib}/grlib/stdlib/config_types.vhd
read_vhdl -library grlib ${lib}/grlib/stdlib/config.vhd
......@@ -282,6 +283,8 @@ file copy -force ${ip}/mig/mig.prj mig/mig.prj
read_ip mig/mig.xci
generate_target all [get_ips mig]
#read_vhdl -library work ${src_dir}/leds_ctrl.vhd
read_vhdl -library work ${design}/config.vhd
read_vhdl -library work ${design}/ahbram_sim.vhd
read_vhdl -library work ${design}/ahbrom.vhd
......@@ -289,8 +292,9 @@ read_vhdl -library work ${design}/leon3mp.vhd
read_vhdl -library work ${design}/ddr_dummy.vhd
read_vhdl -library work ${design}/sgmii_vc707.vhd
read_xdc ${lib}/../boards/xilinx-vc707-xc7vx485t/xilinx-vc707-xc7vx485t.xdc
#read_xdc ${design}/containers.xdc
read_xdc ${design}/xilinx-vc707-xc7vx485t.xdc
read_xdc ${src_dir}/partial_region.xdc
read_xdc ${src_dir}/leds.xdc
synth_design -top $top -part $part -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -no_lc -shreg_min_size 5
......
source ../../tcl/defines.tcl
set name $argv
read_vhdl ../../src/$name.vhd
synth_design -top $name -part $part -mode out_of_context
write_checkpoint -force $pr_instance_dcp_dir/$name.dcp
close_design
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