arm_transform.c 58.7 KB
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/*
 * This file is part of libFirm.
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 * Copyright (C) 2012 University of Karlsruhe.
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 */

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/**
 * @file
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 * @brief   The codegenerator (transform FIRM into arm FIRM)
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 * @author  Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
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 */
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#include "config.h"

#include "irnode_t.h"
#include "irgraph_t.h"
#include "irmode_t.h"
#include "irgmod.h"
#include "iredges.h"
#include "ircons.h"
#include "dbginfo.h"
#include "iropt_t.h"
#include "debug.h"
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#include "error.h"
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#include "util.h"
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#include "benode.h"
#include "beirg.h"
#include "beutil.h"
#include "betranshlp.h"
#include "beabihelper.h"
#include "beabi.h"
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#include "bearch_arm_t.h"
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#include "arm_nodes_attr.h"
#include "arm_transform.h"
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#include "arm_optimize.h"
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#include "arm_new_nodes.h"
#include "arm_map_regs.h"
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#include "arm_cconv.h"
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#include "gen_arm_regalloc_if.h"

#include <limits.h>

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DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
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static const arch_register_t *sp_reg = &arm_registers[REG_SP];
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static ir_mode               *mode_gp;
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static ir_mode               *mode_fp;
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static beabi_helper_env_t    *abihelper;
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static be_stackorder_t       *stackorder;
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static calling_convention_t  *cconv = NULL;
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static arm_isa_t             *isa;
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static pmap                  *node_to_stack;

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static const arch_register_t *const callee_saves[] = {
	&arm_registers[REG_R4],
	&arm_registers[REG_R5],
	&arm_registers[REG_R6],
	&arm_registers[REG_R7],
	&arm_registers[REG_R8],
	&arm_registers[REG_R9],
	&arm_registers[REG_R10],
	&arm_registers[REG_R11],
	&arm_registers[REG_LR],
};

static const arch_register_t *const caller_saves[] = {
	&arm_registers[REG_R0],
	&arm_registers[REG_R1],
	&arm_registers[REG_R2],
	&arm_registers[REG_R3],
	&arm_registers[REG_LR],

	&arm_registers[REG_F0],
	&arm_registers[REG_F1],
	&arm_registers[REG_F2],
	&arm_registers[REG_F3],
	&arm_registers[REG_F4],
	&arm_registers[REG_F5],
	&arm_registers[REG_F6],
	&arm_registers[REG_F7],
};

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static bool mode_needs_gp_reg(ir_mode *mode)
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{
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	return mode_is_int(mode) || mode_is_reference(mode);
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}

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/**
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 * create firm graph for a constant
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 */
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static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
                                         unsigned int value)
{
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	ir_node *result;
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	arm_vals v, vn;
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	int cnt;
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	/* We only have 8 bit immediates. So we possibly have to combine several
	 * operations to construct the desired value.
	 *
	 * we can either create the value by adding bits to 0 or by removing bits
	 * from an register with all bits set. Try which alternative needs fewer
	 * operations */
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	arm_gen_vals_from_word(value, &v);
	arm_gen_vals_from_word(~value, &vn);
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	if (vn.ops < v.ops) {
		/* remove bits */
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		result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
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		for (cnt = 1; cnt < vn.ops; ++cnt) {
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			result = new_bd_arm_Bic_imm(dbgi, block, result,
			                            vn.values[cnt], vn.rors[cnt]);
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		}
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	} else {
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		/* add bits */
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		result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
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		for (cnt = 1; cnt < v.ops; ++cnt) {
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			result = new_bd_arm_Or_imm(dbgi, block, result,
			                           v.values[cnt], v.rors[cnt]);
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		}
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	}
	return result;
}

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/**
 * Create a DAG constructing a given Const.
 *
 * @param irn  a Firm const
 */
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static ir_node *create_const_graph(ir_node *irn, ir_node *block)
{
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	ir_tarval *tv   = get_Const_tarval(irn);
	ir_mode   *mode = get_tarval_mode(tv);
	unsigned   value;
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	if (mode_is_reference(mode)) {
		/* ARM is 32bit, so we can safely convert a reference tarval into Iu */
		assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
		tv = tarval_convert_to(tv, mode_Iu);
	}
	value = get_tarval_long(tv);
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	return create_const_graph_value(get_irn_dbg_info(irn), block, value);
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}

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/**
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 * Create an And that will zero out upper bits.
 *
 * @param dbgi     debug info
 * @param block    the basic block
 * @param op       the original node
 * param src_bits  number of lower bits that will remain
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 */
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static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
                                   int src_bits)
{
	if (src_bits == 8) {
		return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
	} else if (src_bits == 16) {
		ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
		ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
		return rshift;
	} else {
		panic("zero extension only supported for 8 and 16 bits");
	}
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}

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/**
 * Generate code for a sign extension.
 */
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static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
                                   int src_bits)
{
	int shift_width = 32 - src_bits;
	ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
	ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
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	return rshift_node;
}

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static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
                              ir_mode *orig_mode)
{
	int bits = get_mode_size_bits(orig_mode);
	if (bits == 32)
		return op;

	if (mode_is_signed(orig_mode)) {
		return gen_sign_extension(dbgi, block, op, bits);
	} else {
		return gen_zero_extension(dbgi, block, op, bits);
	}
}

/**
 * returns true if it is assured, that the upper bits of a node are "clean"
 * which means for a 16 or 8 bit value, that the upper bits in the register
 * are 0 for unsigned and a copy of the last significant bit for signed
 * numbers.
 */
static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
{
	(void) transformed_node;
	(void) mode;
	/* TODO */
	return false;
}

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/**
 * Transforms a Conv node.
 *
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 * @return The created ia32 Conv node
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 */
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static ir_node *gen_Conv(ir_node *node)
{
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	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *op       = get_Conv_op(node);
	ir_node  *new_op   = be_transform_node(op);
	ir_mode  *src_mode = get_irn_mode(op);
	ir_mode  *dst_mode = get_irn_mode(node);
	dbg_info *dbg      = get_irn_dbg_info(node);

	if (src_mode == dst_mode)
		return new_op;

	if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
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		if (USE_FPA(isa)) {
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			if (mode_is_float(src_mode)) {
				if (mode_is_float(dst_mode)) {
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					/* from float to float */
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					return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
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				} else {
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					/* from float to int */
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					panic("TODO");
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				}
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			} else {
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				/* from int to float */
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				if (!mode_is_signed(src_mode)) {
					panic("TODO");
				} else {
					return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
				}
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			}
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		} else if (USE_VFP(isa)) {
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			panic("VFP not supported yet");
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		} else {
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			panic("Softfloat not supported yet");
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		}
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	} else { /* complete in gp registers */
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		int src_bits = get_mode_size_bits(src_mode);
		int dst_bits = get_mode_size_bits(dst_mode);
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		int min_bits;
		ir_mode *min_mode;
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		if (src_bits == dst_bits) {
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			/* kill unnecessary conv */
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			return new_op;
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		}

		if (src_bits < dst_bits) {
			min_bits = src_bits;
			min_mode = src_mode;
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		} else {
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			min_bits = dst_bits;
			min_mode = dst_mode;
		}

		if (upper_bits_clean(new_op, min_mode)) {
			return new_op;
		}

		if (mode_is_signed(min_mode)) {
			return gen_sign_extension(dbg, block, new_op, min_bits);
		} else {
			return gen_zero_extension(dbg, block, new_op, min_bits);
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		}
	}
}

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typedef struct {
	unsigned char  imm_8;
	unsigned char  rot;
} arm_immediate_t;

static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
{
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	unsigned val, low_pos, high_pos;
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	if (!is_Const(node))
		return false;
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	val = get_tarval_long(get_Const_tarval(node));
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	if (val == 0) {
		res->imm_8 = 0;
		res->rot   = 0;
		return true;
	}
	if (val <= 0xff) {
		res->imm_8 = val;
		res->rot   = 0;
		return true;
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	}
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	/* arm allows to use to rotate an 8bit immediate value by a multiple of 2
	   (= 0, 2, 4, 6, ...).
	   So we determine the smallest even position with a bit set
	   and the highest even position with no bit set anymore.
	   If the difference between these 2 is <= 8, then we can encode the value
	   as immediate.
	 */
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	low_pos  = ntz(val) & ~1u;
	high_pos = (32-nlz(val)+1) & ~1u;
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	if (high_pos - low_pos <= 8) {
		res->imm_8 = val >> low_pos;
		res->rot   = 32 - low_pos;
		return true;
	}

	if (high_pos > 24) {
		res->rot = 34 - high_pos;
		val      = val >> (32-res->rot) | val << (res->rot);
		if (val <= 0xff) {
			res->imm_8 = val;
			return true;
		}
	}

	return false;
}

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static bool is_downconv(const ir_node *node)
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{
	ir_mode *src_mode;
	ir_mode *dest_mode;

	if (!is_Conv(node))
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		return false;
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	/* we only want to skip the conv when we're the only user
	 * (not optimal but for now...)
	 */
	if (get_irn_n_edges(node) > 1)
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		return false;
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	src_mode  = get_irn_mode(get_Conv_op(node));
	dest_mode = get_irn_mode(node);
	return
		mode_needs_gp_reg(src_mode)  &&
		mode_needs_gp_reg(dest_mode) &&
		get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
}

static ir_node *arm_skip_downconv(ir_node *node)
{
	while (is_downconv(node))
		node = get_Conv_op(node);
	return node;
}

typedef enum {
	MATCH_NONE         = 0,
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	MATCH_COMMUTATIVE  = 1 << 0,  /**< commutative node */
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	MATCH_REVERSE      = 1 << 1,  /**< support reverse opcode */
	MATCH_SIZE_NEUTRAL = 1 << 2,
	MATCH_SKIP_NOT     = 1 << 3,  /**< skip Not on ONE input */
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} match_flags_t;
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ENUM_BITSET(match_flags_t)
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/**
 * possible binop constructors.
 */
typedef struct arm_binop_factory_t {
	/** normal reg op reg operation. */
	ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
	/** normal reg op imm operation. */
	ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
	/** barrel shifter reg op (reg shift reg operation. */
	ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
	/** barrel shifter reg op (reg shift imm operation. */
	ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
} arm_binop_factory_t;
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static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
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		const arm_binop_factory_t *factory)
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{
	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *op1     = get_binop_left(node);
	ir_node  *new_op1;
	ir_node  *op2     = get_binop_right(node);
	ir_node  *new_op2;
	dbg_info *dbgi    = get_irn_dbg_info(node);
	arm_immediate_t imm;

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	if (flags & MATCH_SKIP_NOT) {
		if (is_Not(op1))
			op1 = get_Not_op(op1);
		else if (is_Not(op2))
			op2 = get_Not_op(op2);
		else
			panic("cannot execute MATCH_SKIP_NOT");
	}
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	if (flags & MATCH_SIZE_NEUTRAL) {
		op1 = arm_skip_downconv(op1);
		op2 = arm_skip_downconv(op2);
	} else {
		assert(get_mode_size_bits(get_irn_mode(node)) == 32);
	}

	if (try_encode_as_immediate(op2, &imm)) {
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		new_op1 = be_transform_node(op1);
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		return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
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	}
	new_op2 = be_transform_node(op2);
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    if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
		if (flags & MATCH_REVERSE)
			return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
		else
			return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
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	}
	new_op1 = be_transform_node(op1);

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	/* check if we can fold in a Mov */
	if (is_arm_Mov(new_op2)) {
		const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);

		switch (attr->shift_modifier) {
		case ARM_SHF_IMM:
		case ARM_SHF_ASR_IMM:
		case ARM_SHF_LSL_IMM:
		case ARM_SHF_LSR_IMM:
		case ARM_SHF_ROR_IMM:
			if (factory->new_binop_reg_shift_imm) {
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				ir_node *mov_op = get_irn_n(new_op2, 0);
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				return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
					attr->shift_modifier, attr->shift_immediate);
			}
			break;

		case ARM_SHF_ASR_REG:
		case ARM_SHF_LSL_REG:
		case ARM_SHF_LSR_REG:
		case ARM_SHF_ROR_REG:
			if (factory->new_binop_reg_shift_reg) {
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				ir_node *mov_op  = get_irn_n(new_op2, 0);
				ir_node *mov_sft = get_irn_n(new_op2, 1);
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				return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
					attr->shift_modifier);
			}
			break;
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		case ARM_SHF_REG:
		case ARM_SHF_RRX:
			break;
		case ARM_SHF_INVALID:
			panic("invalid shift");
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		}
	}
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	if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
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		const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
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		int idx = flags & MATCH_REVERSE ? 1 : 0;
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		switch (attr->shift_modifier) {
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		ir_node *mov_op, *mov_sft;
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		case ARM_SHF_IMM:
		case ARM_SHF_ASR_IMM:
		case ARM_SHF_LSL_IMM:
		case ARM_SHF_LSR_IMM:
		case ARM_SHF_ROR_IMM:
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			if (factory[idx].new_binop_reg_shift_imm) {
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				mov_op = get_irn_n(new_op1, 0);
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				return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
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					attr->shift_modifier, attr->shift_immediate);
			}
			break;

		case ARM_SHF_ASR_REG:
		case ARM_SHF_LSL_REG:
		case ARM_SHF_LSR_REG:
		case ARM_SHF_ROR_REG:
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			if (factory[idx].new_binop_reg_shift_reg) {
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				mov_op  = get_irn_n(new_op1, 0);
				mov_sft = get_irn_n(new_op1, 1);
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				return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
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					attr->shift_modifier);
			}
			break;
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		case ARM_SHF_REG:
		case ARM_SHF_RRX:
			break;
		case ARM_SHF_INVALID:
			panic("invalid shift");
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		}
	}
	return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
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}
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/**
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 * Creates an ARM Add.
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 *
 * @return the created arm Add node
 */
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static ir_node *gen_Add(ir_node *node)
{
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	static const arm_binop_factory_t add_factory = {
		new_bd_arm_Add_reg,
		new_bd_arm_Add_imm,
		new_bd_arm_Add_reg_shift_reg,
		new_bd_arm_Add_reg_shift_imm
	};

	ir_mode *mode = get_irn_mode(node);
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	if (mode_is_float(mode)) {
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		ir_node  *block   = be_transform_node(get_nodes_block(node));
		ir_node  *op1     = get_Add_left(node);
		ir_node  *op2     = get_Add_right(node);
		dbg_info *dbgi    = get_irn_dbg_info(node);
		ir_node  *new_op1 = be_transform_node(op1);
		ir_node  *new_op2 = be_transform_node(op2);
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		if (USE_FPA(isa)) {
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			return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
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		} else if (USE_VFP(isa)) {
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			panic("VFP not supported yet");
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		} else {
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			panic("Softfloat not supported yet");
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		}
	} else {
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		/* TODO: check for MLA */
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		return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
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	}
}
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/**
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 * Creates an ARM Mul.
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 *
 * @return the created arm Mul node
 */
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static ir_node *gen_Mul(ir_node *node)
{
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	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *op1     = get_Mul_left(node);
	ir_node  *new_op1 = be_transform_node(op1);
	ir_node  *op2     = get_Mul_right(node);
	ir_node  *new_op2 = be_transform_node(op2);
	ir_mode  *mode    = get_irn_mode(node);
	dbg_info *dbg     = get_irn_dbg_info(node);
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	if (mode_is_float(mode)) {
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		if (USE_FPA(isa)) {
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			return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
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		} else if (USE_VFP(isa)) {
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			panic("VFP not supported yet");
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		} else {
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			panic("Softfloat not supported yet");
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		}
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	}
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	assert(mode_is_data(mode));
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	return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
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}

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static ir_node *gen_Div(ir_node *node)
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{
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	ir_node  *block   = be_transform_node(get_nodes_block(node));
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	ir_node  *op1     = get_Div_left(node);
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	ir_node  *new_op1 = be_transform_node(op1);
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	ir_node  *op2     = get_Div_right(node);
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	ir_node  *new_op2 = be_transform_node(op2);
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	ir_mode  *mode    = get_Div_resmode(node);
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	dbg_info *dbg     = get_irn_dbg_info(node);
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	/* integer division should be replaced by builtin call */
	assert(mode_is_float(mode));
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	if (USE_FPA(isa)) {
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		return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
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	} else if (USE_VFP(isa)) {
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		panic("VFP not supported yet");
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	} else {
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		panic("Softfloat not supported yet");
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	}
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}

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static ir_node *gen_And(ir_node *node)
{
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	static const arm_binop_factory_t and_factory = {
		new_bd_arm_And_reg,
		new_bd_arm_And_imm,
		new_bd_arm_And_reg_shift_reg,
		new_bd_arm_And_reg_shift_imm
	};
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	static const arm_binop_factory_t bic_factory = {
		new_bd_arm_Bic_reg,
		new_bd_arm_Bic_imm,
		new_bd_arm_Bic_reg_shift_reg,
		new_bd_arm_Bic_reg_shift_imm
	};

	/* check for and not */
	ir_node *left  = get_And_left(node);
	ir_node *right = get_And_right(node);

	if (is_Not(left) || is_Not(right)) {
		return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
			&bic_factory);
	}
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	return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
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}
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static ir_node *gen_Or(ir_node *node)
{
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	static const arm_binop_factory_t or_factory = {
		new_bd_arm_Or_reg,
		new_bd_arm_Or_imm,
		new_bd_arm_Or_reg_shift_reg,
		new_bd_arm_Or_reg_shift_imm
	};

	return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
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}
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static ir_node *gen_Eor(ir_node *node)
{
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	static const arm_binop_factory_t eor_factory = {
		new_bd_arm_Eor_reg,
		new_bd_arm_Eor_imm,
		new_bd_arm_Eor_reg_shift_reg,
		new_bd_arm_Eor_reg_shift_imm
	};

	return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
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}
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static ir_node *gen_Sub(ir_node *node)
{
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	static const arm_binop_factory_t sub_rsb_factory[2] = {
		{
			new_bd_arm_Sub_reg,
			new_bd_arm_Sub_imm,
			new_bd_arm_Sub_reg_shift_reg,
			new_bd_arm_Sub_reg_shift_imm
		},
		{
			new_bd_arm_Rsb_reg,
			new_bd_arm_Rsb_imm,
			new_bd_arm_Rsb_reg_shift_reg,
			new_bd_arm_Rsb_reg_shift_imm
		}
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	};

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	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *op1     = get_Sub_left(node);
	ir_node  *new_op1 = be_transform_node(op1);
	ir_node  *op2     = get_Sub_right(node);
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	ir_node  *new_op2 = be_transform_node(op2);
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	ir_mode  *mode    = get_irn_mode(node);
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	dbg_info *dbgi    = get_irn_dbg_info(node);
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	if (mode_is_float(mode)) {
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		if (USE_FPA(isa)) {
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			return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
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		} else if (USE_VFP(isa)) {
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			panic("VFP not supported yet");
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		} else {
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			panic("Softfloat not supported yet");
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		}
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	} else {
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		return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
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	}
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}
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/**
 * Checks if a given value can be used as an immediate for the given
 * ARM shift mode.
 */
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static bool can_use_shift_constant(unsigned int val,
                                   arm_shift_modifier_t modifier)
{
	if (val <= 31)
		return true;
	if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
		return true;
	return false;
}

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/**
 * generate an ARM shift instruction.
 *
 * @param node            the node
 * @param flags           matching flags
 * @param shift_modifier  initial encoding of the desired shift operation
 */
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static ir_node *make_shift(ir_node *node, match_flags_t flags,
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		arm_shift_modifier_t shift_modifier)
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{
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	ir_node  *block = be_transform_node(get_nodes_block(node));
	ir_node  *op1   = get_binop_left(node);
	ir_node  *op2   = get_binop_right(node);
	dbg_info *dbgi  = get_irn_dbg_info(node);
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	ir_mode  *mode  = get_irn_mode(node);
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	ir_node  *new_op1;
	ir_node  *new_op2;

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	if (get_mode_modulo_shift(mode) != 32)
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		panic("modulo shift!=32 not supported");
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	if (flags & MATCH_SIZE_NEUTRAL) {
		op1 = arm_skip_downconv(op1);
		op2 = arm_skip_downconv(op2);
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	}
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	new_op1 = be_transform_node(op1);
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	if (is_Const(op2)) {
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		ir_tarval   *tv  = get_Const_tarval(op2);
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		unsigned int val = get_tarval_long(tv);
		assert(tarval_is_long(tv));
		if (can_use_shift_constant(val, shift_modifier)) {
			switch (shift_modifier) {
			case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
			case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
			case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
			case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
			default: panic("unexpected shift modifier");
			}
			return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
			                                    shift_modifier, val);
		}
	}

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	new_op2 = be_transform_node(op2);
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	return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
	                                    shift_modifier);
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}

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static ir_node *gen_Shl(ir_node *node)
{
	return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
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}

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static ir_node *gen_Shr(ir_node *node)
{
	return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
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}

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static ir_node *gen_Shrs(ir_node *node)
{
	return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
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}

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static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
{
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	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *new_op1 = be_transform_node(op1);
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	dbg_info *dbgi    = get_irn_dbg_info(node);
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	ir_node  *new_op2 = be_transform_node(op2);

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	return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
	                                    ARM_SHF_ROR_REG);
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}

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static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
{
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	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *new_op1 = be_transform_node(op1);
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	dbg_info *dbgi    = get_irn_dbg_info(node);
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	ir_node  *new_op2 = be_transform_node(op2);

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	/* Note: there is no Rol on arm, we have to use Ror */
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	new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
	return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
	                                    ARM_SHF_ROR_REG);
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}

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static ir_node *gen_Rotl(ir_node *node)
{
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	ir_node *rotate = NULL;
	ir_node *op1    = get_Rotl_left(node);
	ir_node *op2    = get_Rotl_right(node);

	/* Firm has only RotL, so we are looking for a right (op2)
	   operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
	   that means we can create a RotR. */

	if (is_Add(op2)) {
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		ir_node *right = get_Add_right(op2);
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		if (is_Const(right)) {
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			ir_tarval *tv   = get_Const_tarval(right);
			ir_mode   *mode = get_irn_mode(node);
			long       bits = get_mode_size_bits(mode);
			ir_node   *left = get_Add_left(op2);
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			if (is_Minus(left) &&
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			    tarval_is_long(tv)          &&
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			    get_tarval_long(tv) == bits &&
			    bits                == 32)
				rotate = gen_Ror(node, op1, get_Minus_op(left));
		}
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	} else if (is_Sub(op2)) {
		ir_node *left = get_Sub_left(op2);
		if (is_Const(left)) {
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			ir_tarval *tv   = get_Const_tarval(left);
			ir_mode   *mode = get_irn_mode(node);
			long       bits = get_mode_size_bits(mode);
			ir_node   *right = get_Sub_right(op2);
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			if (tarval_is_long(tv)          &&
			    get_tarval_long(tv) == bits &&
			    bits                == 32)
				rotate = gen_Ror(node, op1, right);
		}
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	} else if (is_Const(op2)) {
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		ir_tarval *tv   = get_Const_tarval(op2);
		ir_mode   *mode = get_irn_mode(node);
		long       bits = get_mode_size_bits(mode);
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		if (tarval_is_long(tv) && bits == 32) {
			ir_node  *block   = be_transform_node(get_nodes_block(node));
			ir_node  *new_op1 = be_transform_node(op1);
			dbg_info *dbgi    = get_irn_dbg_info(node);
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			bits = (bits - get_tarval_long(tv)) & 31;
			rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
		}
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	}

	if (rotate == NULL) {
		rotate = gen_Rol(node, op1, op2);
	}

	return rotate;
}

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static ir_node *gen_Not(ir_node *node)
{
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	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *op      = get_Not_op(node);
	ir_node  *new_op  = be_transform_node(op);
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	dbg_info *dbgi    = get_irn_dbg_info(node);
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	/* check if we can fold in a Mov */
	if (is_arm_Mov(new_op)) {
		const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);

		switch (attr->shift_modifier) {
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		ir_node *mov_op, *mov_sft;
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		case ARM_SHF_IMM:
		case ARM_SHF_ASR_IMM:
		case ARM_SHF_LSL_IMM:
		case ARM_SHF_LSR_IMM:
		case ARM_SHF_ROR_IMM:
			mov_op = get_irn_n(new_op, 0);
			return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
				attr->shift_modifier, attr->shift_immediate);

		case ARM_SHF_ASR_REG:
		case ARM_SHF_LSL_REG:
		case ARM_SHF_LSR_REG:
		case ARM_SHF_ROR_REG:
			mov_op  = get_irn_n(new_op, 0);
			mov_sft = get_irn_n(new_op, 1);
			return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
				attr->shift_modifier);
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		case ARM_SHF_REG:
		case ARM_SHF_RRX:
			break;
		case ARM_SHF_INVALID:
			panic("invalid shift");
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		}
	}
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	return new_bd_arm_Mvn_reg(dbgi, block, new_op);
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}

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static ir_node *gen_Minus(ir_node *node)
{
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	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *op      = get_Minus_op(node);
	ir_node  *new_op  = be_transform_node(op);
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	dbg_info *dbgi    = get_irn_dbg_info(node);
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	ir_mode  *mode    = get_irn_mode(node);
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	if (mode_is_float(mode)) {
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		if (USE_FPA(isa)) {
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			return new_bd_arm_Mvf(dbgi, block, op, mode);
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		} else if (USE_VFP(isa)) {
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			panic("VFP not supported yet");
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		} else {
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			panic("Softfloat not supported yet");
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		}
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	}
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	assert(mode_is_data(mode));
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	return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
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}

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static ir_node *gen_Load(ir_node *node)
{
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	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *ptr      = get_Load_ptr(node);
	ir_node  *new_ptr  = be_transform_node(ptr);
	ir_node  *mem      = get_Load_mem(node);
	ir_node  *new_mem  = be_transform_node(mem);
	ir_mode  *mode     = get_Load_mode(node);
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	dbg_info *dbgi      = get_irn_dbg_info(node);
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	ir_node  *new_load = NULL;
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	if (get_Load_unaligned(node) == align_non_aligned)
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		panic("unaligned Loads not supported yet");
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	if (mode_is_float(mode)) {
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		if (USE_FPA(isa)) {
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			new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
			                          NULL, 0, 0, false);
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		} else if (USE_VFP(isa)) {
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			panic("VFP not supported yet");
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		} else {
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			panic("Softfloat not supported yet");
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		}
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	} else {
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		assert(mode_is_data(mode) && "unsupported mode for Load");
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		new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
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	}
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	set_irn_pinned(new_load, get_irn_pinned(node));
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	/* check for special case: the loaded value might not be used */
	if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
		/* add a result proj and a Keep to produce a pseudo use */
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		ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
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		be_new_Keep(block, 1, &proj);
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	}

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	return new_load;
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}

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static ir_node *gen_Store(ir_node *node)
{
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	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *ptr      = get_Store_ptr(node);
	ir_node  *new_ptr  = be_transform_node(ptr);
	ir_node  *mem      = get_Store_mem(node);
	ir_node  *new_mem  = be_transform_node(mem);
	ir_node  *val      = get_Store_value(node);
	ir_node  *new_val  = be_transform_node(val);
	ir_mode  *mode     = get_irn_mode(val);
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	dbg_info *dbgi     = get_irn_dbg_info(node);
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	ir_node *new_store = NULL;
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	if (get_Store_unaligned(node) == align_non_aligned)
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		panic("unaligned Stores not supported yet");
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	if (mode_is_float(mode)) {
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		if (USE_FPA(isa)) {
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			new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
			                           new_mem, mode, NULL, 0, 0, false);
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		} else if (USE_VFP(isa)) {
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			panic("VFP not supported yet");
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		} else {
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			panic("Softfloat not supported yet");
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		}
	} else {
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		assert(mode_is_data(mode) && "unsupported mode for Store");
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		new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
		                           NULL, 0, 0, false);
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	}
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	set_irn_pinned(new_store, get_irn_pinned(node));
	return new_store;
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}

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static ir_node *gen_Jmp(ir_node *node)
{
	ir_node  *block     = get_nodes_block(node);
	ir_node  *new_block = be_transform_node(block);
	dbg_info *dbgi      = get_irn_dbg_info(node);

	return new_bd_arm_Jmp(dbgi, new_block);
}

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static ir_node *gen_Switch(ir_node *node)
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{
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	ir_graph              *irg      = get_irn_irg(node);
	ir_node               *block    = be_transform_node(get_nodes_block(node));
	ir_node               *selector = get_Switch_selector(node);
	dbg_info              *dbgi     = get_irn_dbg_info(node);
	ir_node               *new_op   = be_transform_node(selector);
	ir_mode               *mode     = get_irn_mode(selector);
	const ir_switch_table *table    = get_Switch_table(node);
	unsigned               n_outs   = get_Switch_n_outs(node);
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	table = ir_switch_table_duplicate(irg, table);
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	/* switch with smaller modes not implemented yet */
	assert(get_mode_size_bits(mode) == 32);
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	return new_bd_arm_SwitchJmp(dbgi, block, new_op, n_outs, table);
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}

static ir_node *gen_Cmp(ir_node *node)
{
	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *op1      = get_Cmp_left(node);
	ir_node  *op2      = get_Cmp_right(node);
	ir_mode  *cmp_mode = get_irn_mode(op1);
	dbg_info *dbgi     = get_irn_dbg_info(node);
	ir_node  *new_op1;
	ir_node  *new_op2;
	bool      is_unsigned;

	if (mode_is_float(cmp_mode)) {
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		/* TODO: this is broken... */
		new_op1 = be_transform_node(op1);
		new_op2 = be_transform_node(op2);

		return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
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	}
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	assert(get_irn_mode(op2) == cmp_mode);
	is_unsigned = !mode_is_signed(cmp_mode);

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	/* integer compare, TODO: use shifter_op in all its combinations */
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	new_op1 = be_transform_node(op1);
	new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
	new_op2 = be_transform_node(op2);
	new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
	return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
	                          is_unsigned);
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}

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static ir_node *gen_Cond(ir_node *node)
{
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	ir_node    *const block     = be_transform_node(get_nodes_block(node));
	dbg_info   *const dbgi      = get_irn_dbg_info(node);
	ir_node    *const selector  = get_Cond_selector(node);
	ir_node    *const flag_node = be_transform_node(selector);
	ir_relation const relation  = get_Cmp_relation(selector);
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	return new_bd_arm_B(dbgi, block, flag_node, relation);
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}

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enum fpa_imm_mode {
	FPA_IMM_FLOAT    = 0,
	FPA_IMM_DOUBLE   = 1,
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	FPA_IMM_MAX = FPA_IMM_DOUBLE
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};

static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
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static ir_node *gen_Const(ir_node *node)
{
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	ir_node  *block = be_transform_node(get_nodes_block(node));
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	ir_mode *mode =