ia32_emitter.c 57 KB
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/**
 * This file implements the node emitter.
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 * @author Christian Wuerdig, Matthias Braun
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 * $Id$
 */
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif

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#include <limits.h>

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#include "xmalloc.h"
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#include "tv.h"
#include "iredges.h"
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#include "debug.h"
#include "irgwalk.h"
#include "irprintf.h"
#include "irop_t.h"
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#include "irargs_t.h"
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#include "irprog_t.h"
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#include "iredges_t.h"
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#include "execfreq.h"
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#include "error.h"
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#include "../besched_t.h"
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#include "../benode_t.h"
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#include "../beabi.h"
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#include "../be_dbgout.h"
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#include "ia32_emitter.h"
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#include "gen_ia32_emitter.h"
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#include "gen_ia32_regalloc_if.h"
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#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
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#include "ia32_map_regs.h"
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#include "bearch_ia32_t.h"
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#define BLOCK_PREFIX ".L"
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#define SNPRINTF_BUF_LEN 128

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/* global arch_env for lc_printf functions */
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static const arch_env_t *arch_env = NULL;
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/** by default, we generate assembler code for the Linux gas */
asm_flavour_t asm_flavour = ASM_LINUX_GAS;

/**
 * Switch to a new section
 */
void ia32_switch_section(FILE *F, section_t sec) {
	static section_t curr_sec = NO_SECTION;
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	static const char *text[ASM_MAX][SECTION_MAX] = {
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		{
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			".section\t.text",
			".section\t.data",
			".section\t.rodata",
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			".section\t.bss",
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			".section\t.tbss,\"awT\",@nobits",
			".section\t.ctors,\"aw\",@progbits"
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		},
		{
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			".section\t.text",
			".section\t.data",
			".section .rdata,\"dr\"",
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			".section\t.bss",
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			".section\t.tbss,\"awT\",@nobits",
			".section\t.ctors,\"aw\",@progbits"
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		}
	};

	if (curr_sec == sec)
		return;

	curr_sec = sec;
	switch (sec) {

	case NO_SECTION:
		break;

	case SECTION_TEXT:
	case SECTION_DATA:
	case SECTION_RODATA:
	case SECTION_COMMON:
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	case SECTION_TLS:
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	case SECTION_CTOR:
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		fprintf(F, "\t%s\n", text[asm_flavour][sec]);
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		break;

	default:
		break;
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	}
}

static void ia32_dump_function_object(FILE *F, const char *name)
{
	switch (asm_flavour) {
	case ASM_LINUX_GAS:
		fprintf(F, "\t.type\t%s, @function\n", name);
		break;
	case ASM_MINGW_GAS:
		fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
		break;
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	default:
		break;
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	}
}

static void ia32_dump_function_size(FILE *F, const char *name)
{
	switch (asm_flavour) {
	case ASM_LINUX_GAS:
		fprintf(F, "\t.size\t%s, .-%s\n", name, name);
		break;
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	default:
		break;
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	}
}

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/**
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 * Returns the register at in position pos.
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 */
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static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
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	ir_node                *op;
	const arch_register_t  *reg = NULL;

	assert(get_irn_arity(irn) > pos && "Invalid IN position");

	/* The out register of the operator at position pos is the
	   in register we need. */
	op = get_irn_n(irn, pos);

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	reg = arch_get_irn_register(arch_env, op);
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	assert(reg && "no in register found");
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	/* in case of a joker register: just return a valid register */
	if (arch_register_type_is(reg, joker)) {
		arch_register_req_t       req;
		const arch_register_req_t *p_req;

		/* ask for the requirements */
		p_req = arch_get_register_req(arch_env, &req, irn, pos);

		if (arch_register_req_is(p_req, limited)) {
			/* in case of limited requirements: get the first allowed register */

			bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
			int      idx;

			p_req->limited(p_req->limited_env, bs);
			idx = bitset_next_set(bs, 0);
			reg = arch_register_for_index(p_req->cls, idx);
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		} else {
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			/* otherwise get first register in class */
			reg = arch_register_for_index(p_req->cls, 0);
		}
	}
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	return reg;
}

/**
 * Returns the register at out position pos.
 */
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static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
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	ir_node                *proj;
	const arch_register_t  *reg = NULL;

	/* 1st case: irn is not of mode_T, so it has only                 */
	/*           one OUT register -> good                             */
	/* 2nd case: irn is of mode_T -> collect all Projs and ask the    */
	/*           Proj with the corresponding projnum for the register */

	if (get_irn_mode(irn) != mode_T) {
		reg = arch_get_irn_register(arch_env, irn);
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	} else if (is_ia32_irn(irn)) {
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		reg = get_ia32_out_reg(irn, pos);
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	} else {
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		const ir_edge_t *edge;

		foreach_out_edge(irn, edge) {
			proj = get_edge_src_irn(edge);
			assert(is_Proj(proj) && "non-Proj from mode_T node");
			if (get_Proj_proj(proj) == pos) {
				reg = arch_get_irn_register(arch_env, proj);
				break;
			}
		}
	}

	assert(reg && "no out register found");
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	return reg;
}

/**
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 * Returns an ident for the given tarval tv.
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 */
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static ident *get_ident_for_tv(tarval *tv) {
	char buf[256];
	int len = tarval_snprintf(buf, sizeof(buf), tv);
	assert(len);
	return new_id_from_str(buf);
}
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/**
 * Determine the gnu assembler suffix that indicates a mode
 */
static char get_mode_suffix(const ir_mode *mode) {
	if(mode_is_float(mode)) {
		switch(get_mode_size_bits(mode)) {
		case 32:
			return 's';
		case 64:
			return 'l';
		case 80:
			return 't';
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		}
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	} else {
		assert(mode_is_int(mode) || mode_is_reference(mode));
		switch(get_mode_size_bits(mode)) {
		case 64:
			return 'q';
		case 32:
			return 'l';
		case 16:
			return 'w';
		case 8:
			return 'b';
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		}
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	}
	panic("Can't output mode_suffix for %+F\n", mode);
}
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static int produces_result(const ir_node *node) {
	return !(is_ia32_St(node) ||
		is_ia32_Store8Bit(node) ||
		is_ia32_CondJmp(node) ||
		is_ia32_xCondJmp(node) ||
		is_ia32_CmpSet(node) ||
		is_ia32_xCmpSet(node) ||
		is_ia32_SwitchJmp(node));
}

static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
	switch(get_mode_size_bits(mode)) {
		case 8:
			return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
		case 16:
			return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
		default:
			return (char *)arch_register_get_name(reg);
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	}
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}

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#if 0
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/**
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 * Determines the SSE suffix depending on the mode.
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 */
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static int ia32_print_mode_suffix(lc_appendable_t *app,
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    const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
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	ir_node *irn  = arg->v_ptr;
	ir_mode *mode = get_ia32_ls_mode(irn);
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	if (mode_is_float(mode)) {
		return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
	} else {
		if(get_mode_size_bits(mode) == 32)
			return 0;
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		if(mode_is_signed(mode))
			lc_appendable_chadd(app, 's');
		else
			lc_appendable_chadd(app, 'z');
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		lc_appendable_chadd(app, get_mode_suffix(mode));
		return 2;
	}
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}
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#endif
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/**
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 * Add a number to a prefix. This number will not be used a second time.
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 */
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static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
	static unsigned long id = 0;
	snprintf(buf, buflen, "%s%lu", prefix, ++id);
	return buf;
}

/*************************************************************
 *             _       _    __   _          _
 *            (_)     | |  / _| | |        | |
 *  _ __  _ __ _ _ __ | |_| |_  | |__   ___| |_ __   ___ _ __
 * | '_ \| '__| | '_ \| __|  _| | '_ \ / _ \ | '_ \ / _ \ '__|
 * | |_) | |  | | | | | |_| |   | | | |  __/ | |_) |  __/ |
 * | .__/|_|  |_|_| |_|\__|_|   |_| |_|\___|_| .__/ \___|_|
 * | |                                       | |
 * |_|                                       |_|
 *************************************************************/

void ia32_emit_ident(ia32_emit_env_t *env, ident *id)
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{
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	size_t len = get_id_strlen(id);
	const char* str = get_id_str(id);
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	ia32_emit_string_len(env, str, len);
}
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void ia32_emit_irprintf(ia32_emit_env_t *env, const char *fmt, ...)
{
	char buf[128];
	va_list ap;
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	va_start(ap, fmt);
	ir_vsnprintf(buf, sizeof(buf), fmt, ap);
	va_end(ap);
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	ia32_emit_string(env, buf);
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}

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void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
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{
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	const arch_register_t *reg = get_in_reg(node, pos);
	const char *reg_name = arch_register_get_name(reg);
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	assert(pos < get_irn_arity(node));
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	ia32_emit_char(env, '%');
	ia32_emit_string(env, reg_name);
}

void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
	const arch_register_t *reg = get_out_reg(node, pos);
	const char *reg_name = arch_register_get_name(reg);
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	ia32_emit_char(env, '%');
	ia32_emit_string(env, reg_name);
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}

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void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
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{
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	ia32_attr_t *attr = get_ia32_attr(node);
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	assert(pos < 7);
	ia32_emit_char(env, '%');
	ia32_emit_string(env, attr->x87[pos]->name);
}
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void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
{
	tarval *tv;
	ident *id;
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	switch(get_ia32_immop_type(node)) {
	case ia32_ImmConst:
		tv = get_ia32_Immop_tarval(node);
		id = get_ident_for_tv(tv);
		break;
	case ia32_ImmSymConst:
		id = get_ia32_Immop_symconst(node);
		break;
	default:
		assert(0);
		ia32_emit_string(env, "BAD");
		return;
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	}
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	ia32_emit_ident(env, id);
}
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void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode)
{
	ia32_emit_char(env, get_mode_suffix(mode));
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}

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void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
{
	if(get_mode_size_bits(mode) == 32)
		return;
	if(mode_is_signed(mode)) {
		ia32_emit_char(env, 's');
	} else {
		ia32_emit_char(env, 'z');
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	}
}

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/**
 * Emits registers and/or address mode of a binary operation.
 */
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void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
	switch(get_ia32_op_type(node)) {
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		case ia32_Normal:
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			if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
				ia32_emit_char(env, '$');
				ia32_emit_immediate(env, node);
				ia32_emit_cstring(env, ", ");
				ia32_emit_source_register(env, node, 2);
			} else {
				const arch_register_t *in1 = get_in_reg(node, 2);
				const arch_register_t *in2 = get_in_reg(node, 3);
				const arch_register_t *out = produces_result(node) ? get_out_reg(node, 0) : NULL;
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				const arch_register_t *in;
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				const char            *in_name;
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				in      = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
				out     = out ? out : in1;
				in_name = arch_register_get_name(in);
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				if (is_ia32_emit_cl(node)) {
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					assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
					in_name = "cl";
				}

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				ia32_emit_char(env, '%');
				ia32_emit_string(env, in_name);
				ia32_emit_cstring(env, ", %");
				ia32_emit_string(env, arch_register_get_name(out));
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			}
			break;
		case ia32_AddrModeS:
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			if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
				assert(!produces_result(node) && "Source AM with Const must not produce result");
				ia32_emit_am(env, node);
				ia32_emit_cstring(env, ", $");
				ia32_emit_immediate(env, node);
			} else if (produces_result(node)) {
				ia32_emit_am(env, node);
				ia32_emit_cstring(env, ", ");
				ia32_emit_dest_register(env, node, 0);
			} else {
				ia32_emit_am(env, node);
				ia32_emit_cstring(env, ", ");
				ia32_emit_source_register(env, node, 2);
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			}
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			break;
		case ia32_AddrModeD:
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			if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
				ia32_emit_char(env, '$');
				ia32_emit_immediate(env, node);
				ia32_emit_cstring(env, ", ");
				ia32_emit_am(env, node);
			} else {
				const arch_register_t *in1 = get_in_reg(node, get_irn_arity(node) == 5 ? 3 : 2);
				ir_mode               *mode = get_ia32_ls_mode(node);
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				const char            *in_name;
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				in_name = ia32_get_reg_name_for_mode(env, mode, in1);

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				if (is_ia32_emit_cl(node)) {
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					assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
					in_name = "cl";
				}
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				ia32_emit_char(env, '%');
				ia32_emit_string(env, in_name);
				ia32_emit_cstring(env, ", ");
				ia32_emit_am(env, node);
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			}
			break;
		default:
			assert(0 && "unsupported op type");
	}
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}

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/**
 * Emits registers and/or address mode of a binary operation.
 */
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void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
	switch(get_ia32_op_type(node)) {
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		case ia32_Normal:
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			if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
				// should not happen...
				assert(0);
			} else {
				ia32_attr_t *attr = get_ia32_attr(node);
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				const arch_register_t *in1 = attr->x87[0];
				const arch_register_t *in2 = attr->x87[1];
				const arch_register_t *out = attr->x87[2];
				const arch_register_t *in;

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				in  = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
				out = out ? out : in1;
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				ia32_emit_char(env, '%');
				ia32_emit_string(env, arch_register_get_name(in));
				ia32_emit_cstring(env, ", %");
				ia32_emit_string(env, arch_register_get_name(out));
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			}
			break;
		case ia32_AddrModeS:
		case ia32_AddrModeD:
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			ia32_emit_am(env, node);
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			break;
		default:
			assert(0 && "unsupported op type");
	}
}

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/**
 * Emits registers and/or address mode of a unary operation.
 */
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void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node) {
	switch(get_ia32_op_type(node)) {
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		case ia32_Normal:
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			if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
				ia32_emit_char(env, '$');
				ia32_emit_immediate(env, node);
			} else {
				if (is_ia32_IMul(node) || is_ia32_Mulh(node)) {
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					/* MulS and Mulh implicitly multiply by EAX */
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					ia32_emit_source_register(env, node, 3);
				} else if(is_ia32_IDiv(node)) {
					ia32_emit_source_register(env, node, 1);
				} else if(is_ia32_Push(node)) {
					ia32_emit_source_register(env, node, 2);
				} else if(is_ia32_Pop(node)) {
					ia32_emit_dest_register(env, node, 1);
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				} else {
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					ia32_emit_dest_register(env, node, 0);
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				}
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			}
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			break;
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		case ia32_AddrModeS:
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		case ia32_AddrModeD:
			ia32_emit_am(env, node);
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			break;
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		default:
			assert(0 && "unsupported op type");
	}
}

/**
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 * Emits address mode.
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 */
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void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
	ia32_am_flavour_t am_flav = get_ia32_am_flavour(node);
	ident *id = get_ia32_am_sc(node);
	int offs = get_ia32_am_offs_int(node);
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	/* just to be sure... */
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	assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
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	/* emit offset */
	if (id != NULL) {
		if (is_ia32_am_sc_sign(node))
			ia32_emit_char(env, '-');
		ia32_emit_ident(env, id);
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	}

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	if(offs != 0) {
		if(id != NULL) {
			ia32_emit_irprintf(env, "%+d", offs);
		} else {
			ia32_emit_irprintf(env, "%d", offs);
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		}
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	}
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	if (am_flav & (ia32_B | ia32_I)) {
		ia32_emit_char(env, '(');
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		/* emit base */
		if (am_flav & ia32_B) {
			ia32_emit_source_register(env, node, 0);
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		}

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		/* emit index + scale */
		if (am_flav & ia32_I) {
			ia32_emit_char(env, ',');
			ia32_emit_source_register(env, node, 1);
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			if (am_flav & ia32_S) {
				ia32_emit_irprintf(env, ",%d", 1 << get_ia32_am_scale(node));
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			}
		}
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		ia32_emit_char(env, ')');
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	}
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}
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#if 0
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/**
 * Formated print of commands and comments.
 */
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static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
	unsigned lineno;
	const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;

	if (name)
		fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
	else
		fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
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}
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#endif
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void ia32_write_line(ia32_emit_env_t *env)
{
	char *finished_line = obstack_finish(env->obst);
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	fwrite(finished_line, env->linelength, 1, env->out);
	env->linelength = 0;
	obstack_free(env->obst, finished_line);
}
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void ia32_pad_comment(ia32_emit_env_t *env)
{
	while(env->linelength <= 30) {
		ia32_emit_char(env, ' ');
	}
	ia32_emit_cstring(env, "    ");
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}

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void ia32_emit_finish_line(ia32_emit_env_t *env, const ir_node *node)
{
	dbg_info *dbg;
	const char *sourcefile;
	unsigned lineno;

	if(node == NULL) {
		ia32_emit_char(env, '\n');
		ia32_write_line(env);
		return;
	}

	ia32_pad_comment(env);
	ia32_emit_cstring(env, "/* ");
	ia32_emit_irprintf(env, "%+F ", node);

	dbg = get_irn_dbg_info(node);
	sourcefile = be_retrieve_dbg_info(dbg, &lineno);
	if(sourcefile != NULL) {
		ia32_emit_string(env, sourcefile);
		ia32_emit_irprintf(env, ":%u", lineno);
	}
	ia32_emit_cstring(env, " */\n");
	ia32_write_line(env);
}
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/*************************************************
 *                 _ _                         _
 *                (_) |                       | |
 *   ___ _ __ ___  _| |_    ___ ___  _ __   __| |
 *  / _ \ '_ ` _ \| | __|  / __/ _ \| '_ \ / _` |
 * |  __/ | | | | | | |_  | (_| (_) | | | | (_| |
 *  \___|_| |_| |_|_|\__|  \___\___/|_| |_|\__,_|
 *
 *************************************************/

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#undef IA32_DO_EMIT
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#define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
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/*
 * coding of conditions
 */
struct cmp2conditon_t {
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	const char *name;
	pn_Cmp      num;
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};

/*
 * positive conditions for signed compares
 */
static const struct cmp2conditon_t cmp2condition_s[] = {
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	{ NULL,              pn_Cmp_False },  /* always false */
	{ "e",               pn_Cmp_Eq },     /* == */
	{ "l",               pn_Cmp_Lt },     /* < */
	{ "le",              pn_Cmp_Le },     /* <= */
	{ "g",               pn_Cmp_Gt },     /* > */
	{ "ge",              pn_Cmp_Ge },     /* >= */
	{ "ne",              pn_Cmp_Lg },     /* != */
	{ NULL,              pn_Cmp_Leg},     /* Floating point: ordered */
	{ NULL,              pn_Cmp_Uo },     /* Floating point: unordered */
	{ "e",               pn_Cmp_Ue },     /* Floating point: unordered or == */
	{ "b",               pn_Cmp_Ul },     /* Floating point: unordered or < */
	{ "be",              pn_Cmp_Ule },    /* Floating point: unordered or <= */
	{ "a",               pn_Cmp_Ug },     /* Floating point: unordered or > */
	{ "ae",              pn_Cmp_Uge },    /* Floating point: unordered or >= */
	{ "ne",              pn_Cmp_Ne },     /* Floating point: unordered or != */
	{ NULL,              pn_Cmp_True },   /* always true */
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};

/*
 * positive conditions for unsigned compares
 */
static const struct cmp2conditon_t cmp2condition_u[] = {
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	{ NULL,              pn_Cmp_False },  /* always false */
	{ "e",               pn_Cmp_Eq },     /* == */
	{ "b",               pn_Cmp_Lt },     /* < */
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	{ "be",              pn_Cmp_Le },     /* <= */
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	{ "a",               pn_Cmp_Gt },     /* > */
	{ "ae",              pn_Cmp_Ge },     /* >= */
	{ "ne",              pn_Cmp_Lg },     /* != */
	{ NULL,              pn_Cmp_True },   /* always true */
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};

/*
 * returns the condition code
 */
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static const char *get_cmp_suffix(int cmp_code)
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{
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	assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
	assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
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	if((cmp_code & ia32_pn_Cmp_Unsigned)) {
		return cmp2condition_u[cmp_code & 7].name;
	} else {
		return cmp2condition_s[cmp_code & 15].name;
	}
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}

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void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
{
	ia32_emit_string(env, get_cmp_suffix(pnc));
}


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/**
 * Returns the target block for a control flow node.
 */
static ir_node *get_cfop_target_block(const ir_node *irn) {
	return get_irn_link(irn);
}

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/**
 * Returns the target label for a control flow node.
 */
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void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
	ir_node *block = get_cfop_target_block(node);
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	ia32_emit_cstring(env, BLOCK_PREFIX);
	ia32_emit_irprintf(env, "%d", get_irn_node_nr(block));
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}
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/** Return the next block in Block schedule */
static ir_node *next_blk_sched(const ir_node *block) {
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	return get_irn_link(block);
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}

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/**
 * Returns the Proj with projection number proj and NOT mode_M
 */
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static ir_node *get_proj(const ir_node *node, long proj) {
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	const ir_edge_t *edge;
	ir_node         *src;

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	assert(get_irn_mode(node) == mode_T && "expected mode_T node");
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	foreach_out_edge(node, edge) {
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		src = get_edge_src_irn(edge);

		assert(is_Proj(src) && "Proj expected");
		if (get_irn_mode(src) == mode_M)
			continue;

		if (get_Proj_proj(src) == proj)
			return src;
	}
	return NULL;
}

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/**
 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
 */
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static void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node,
                           ir_mode *mode, long pnc) {
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	const ir_node *proj_true;
	const ir_node *proj_false;
	const ir_node *block;
	const ir_node *next_block;
	int flipped = 0;
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	/* get both Proj's */
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	proj_true = get_proj(node, pn_Cond_true);
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	assert(proj_true && "CondJmp without true Proj");
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	proj_false = get_proj(node, pn_Cond_false);
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	assert(proj_false && "CondJmp without false Proj");

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	/* for now, the code works for scheduled and non-schedules blocks */
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	block = get_nodes_block(node);
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	/* we have a block schedule */
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	next_block = next_blk_sched(block);
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	if (get_cfop_target_block(proj_true) == next_block) {
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		/* exchange both proj's so the second one can be omitted */
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		const ir_node *t = proj_true;

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		proj_true  = proj_false;
		proj_false = t;
		flipped    = 1;
		pnc        = get_negated_pnc(pnc, mode);
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	}

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	/* in case of unordered compare, check for parity */
	if (pnc & pn_Cmp_Uo) {
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		ia32_emit_cstring(env, "\tjp ");
		ia32_emit_cfop_target(env, proj_true);
		ia32_emit_finish_line(env, proj_true);
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	}

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	ia32_emit_cstring(env, "\tj");
	ia32_emit_cmp_suffix(env, pnc);
	ia32_emit_char(env, ' ');
	ia32_emit_cfop_target(env, proj_true);
	ia32_emit_finish_line(env, proj_true);
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	/* the second Proj might be a fallthrough */
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	if (get_cfop_target_block(proj_false) != next_block) {
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		ia32_emit_cstring(env, "\tjmp ");
		ia32_emit_cfop_target(env, proj_false);
		ia32_emit_finish_line(env, proj_false);
	} else {
		ia32_emit_cstring(env, "\t/* fallthrough to");
		ia32_emit_cfop_target(env, proj_false);
		ia32_emit_cstring(env, " */");
		ia32_emit_finish_line(env, proj_false);
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	}
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}

/**
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 * Emits code for conditional jump.
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 */
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static void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
	ia32_emit_cstring(env, "\tcmp ");
	ia32_emit_binop(env, node);
	ia32_emit_finish_line(env, node);
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	finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
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}

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/**
 * Emits code for conditional jump with two variables.
 */
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static void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
	CondJmp_emitter(env, node);
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}

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/**
 * Emits code for conditional test and jump.
 */
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static void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
	if(is_ia32_ImmSymConst(node) || is_ia32_ImmConst(node)) {
		ia32_emit_cstring(env, "\ttest $");
		ia32_emit_immediate(env, node);
		ia32_emit_cstring(env, ", ");
		ia32_emit_source_register(env, node, 0);
		ia32_emit_finish_line(env, node);
	} else {
		ia32_emit_cstring(env, "\ttest ");
		ia32_emit_source_register(env, node, 1);
		ia32_emit_cstring(env, ", ");
		ia32_emit_source_register(env, node, 0);
		ia32_emit_finish_line(env, node);
	}
	finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
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}

/**
 * Emits code for conditional test and jump with two variables.
 */
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static void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
	TestJmp_emitter(env, node);
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}

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static void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
	ia32_emit_cstring(env, "/* omitted redundant test */");
	ia32_emit_finish_line(env, node);
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	finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
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}
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static void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
	ia32_emit_cstring(env, "/* omitted redundant test/cmp */");
	ia32_emit_finish_line(env, node);
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	finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
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}
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/**
 * Emits code for conditional SSE floating point jump with two variables.
 */
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static void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
	ia32_emit_cstring(env, "\tucomis");
	ia32_emit_mode_suffix(env, get_irn_mode(node));
	ia32_emit_char(env, ' ');
	ia32_emit_binop(env, node);
	ia32_emit_finish_line(env, node);
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	finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
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}

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/**
 * Emits code for conditional x87 floating point jump with two variables.
 */
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static void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
	ia32_attr_t *attr = get_ia32_attr(node);
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	const char *reg = attr->x87[1]->name;
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	long pnc = get_ia32_pncode(node);
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	switch (get_ia32_irn_opcode(node)) {
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	case iro_ia32_fcomrJmp:
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		pnc = get_inversed_pnc(pnc);
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	case iro_ia32_fcomJmp:
	default:
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		ia32_emit_cstring(env, "\tfucom ");
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		break;
	case iro_ia32_fcomrpJmp:
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		pnc = get_inversed_pnc(pnc);
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	case iro_ia32_fcompJmp:
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		ia32_emit_cstring(env, "\tfucomp ");
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		break;
	case iro_ia32_fcomrppJmp:
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		pnc = get_inversed_pnc(pnc);
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	case iro_ia32_fcomppJmp:
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		ia32_emit_cstring(env, "\tfucompp ");
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		reg = "";
		break;
	}

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	if(reg[0] != '\0') {
		ia32_emit_char(env, '%');
		ia32_emit_string(env, reg);
	}
	ia32_emit_finish_line(env, node);
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	ia32_emit_cstring(env, "\tfnstsw %ax");
	ia32_emit_finish_line(env, node);
	ia32_emit_cstring(env, "\tsahf");
	ia32_emit_finish_line(env, node);
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	finish_CondJmp(env, node, mode_D, pnc);
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}

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static void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
	long pnc = get_ia32_pncode(node);
	int is_PsiCondCMov = is_ia32_PsiCondCMov(node);
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	int idx_left  = 2 - is_PsiCondCMov;
	int idx_right = 3 - is_PsiCondCMov;
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	const arch_register_t *in1, *in2, *out;

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	out = arch_get_irn_register(env->arch_env, node);
	in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_left));
	in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_right));
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	/* we have to emit the cmp first, because the destination register */
	/* could be one of the compare registers                           */
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	if (is_ia32_CmpCMov(node)) {
		ia32_emit_cstring(env, "\tcmp ");
		ia32_emit_source_register(env, node, 1);
		ia32_emit_cstring(env, ", ");
		ia32_emit_source_register(env, node, 0);
	} else if (is_ia32_xCmpCMov(node)) {
		ia32_emit_cstring(env, "\tucomis");
		ia32_emit_mode_suffix(env, get_irn_mode(node));
		ia32_emit_char(env, ' ');
		ia32_emit_source_register(env, node, 1);
		ia32_emit_cstring(env, ", ");
		ia32_emit_source_register(env, node, 0);
	} else if (is_PsiCondCMov) {
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		/* omit compare because flags are already set by And/Or */
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		ia32_emit_cstring(env, "\ttest ");
		ia32_emit_source_register(env, node, 0);
		ia32_emit_cstring(env, ", ");
		ia32_emit_source_register(env, node, 0);
	} else {
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		assert(0 && "unsupported CMov");
	}
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	ia32_emit_finish_line(env, node);
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	if (REGS_ARE_EQUAL(out, in2)) {
		/* best case: default in == out -> do nothing */
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	} else if (REGS_ARE_EQUAL(out, in1)) {
		ir_node *n = (ir_node*) node;
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		/* true in == out -> need complement compare and exchange true and default in */
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		ir_node *t = get_irn_n(n, idx_left);
		set_irn_n(n, idx_left, get_irn_n(n, idx_right));
		set_irn_n(n, idx_right, t);
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		pnc = get_negated_pnc(pnc, get_irn_mode(node));
	} else {
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		/* out is different from in: need copy default -> out */
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		if (is_PsiCondCMov) {
			ia32_emit_cstring(env, "\tmovl ");
			ia32_emit_dest_register(env, node, 2);
			ia32_emit_cstring(env, ", ");
			ia32_emit_dest_register(env, node, 0);
		} else {
			ia32_emit_cstring(env, "\tmovl ");
			ia32_emit_source_register(env, node, 3);
			ia32_emit_cstring(env, ", ");
			ia32_emit_dest_register(env, node, 0);
		}
		ia32_emit_finish_line(env, node);
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	}
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	if (is_PsiCondCMov) {
		ia32_emit_cstring(env, "\tcmov");
		ia32_emit_cmp_suffix(env, pnc);
		ia32_emit_cstring(env, "l ");
		ia32_emit_source_register(env, node, 1);
		ia32_emit_cstring(env, ", ");
		ia32_emit_dest_register(env, node, 0);
	} else {
		ia32_emit_cstring(env, "\tcmov");
		ia32_emit_cmp_suffix(env, pnc);
		ia32_emit_cstring(env, "l ");
		ia32_emit_source_register(env, node, 2);
		ia32_emit_cstring(env, ", ");
		ia32_emit_dest_register(env, node, 0);
	}
	ia32_emit_finish_line(env, node);
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}

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static void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
	CMov_emitter(env, node);
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}

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static void emit_ia32_PsiCondCMov(ia32_emit_env_t *env, const ir_node *node) {
	CMov_emitter(env, node);
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}

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static void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
	CMov_emitter(env, node);
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}

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static void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
	int pnc = get_ia32_pncode(node);
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	const char *reg8bit;
	const arch_register_t *out;

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	out     = arch_get_irn_register(env->arch_env, node);
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	reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);

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	if (is_ia32_CmpSet(node)) {
		ia32_emit_cstring(env, "\tcmp ");
		ia32_emit_binop(env, node);
	} else if (is_ia32_xCmpSet(node)) {
		ia32_emit_cstring(env, "\tucomis");
		ia32_emit_mode_suffix(env, get_irn_mode(get_irn_n(node, 2)));
		ia32_emit_char(env, ' ');
		ia32_emit_binop(env, node);
	} else if (is_ia32_PsiCondSet(node)) {
		ia32_emit_cstring(env, "\tcmp $0, ");
		ia32_emit_source_register(env, node, 0);
	} else {
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		assert(0 && "unsupported Set");
	}
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	ia32_emit_finish_line(env, node);
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	/* use mov to clear target because it doesn't affect the eflags */
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	ia32_emit_cstring(env, "\tmovl $0, %");
	ia32_emit_string(env, arch_register_get_name(out));
	ia32_emit_finish_line(env, node);
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	ia32_emit_cstring(env, "\tset");
	ia32_emit_cmp_suffix(env, pnc);
	ia32_emit_cstring(env, " %");
	ia32_emit_string(env, reg8bit);
	ia32_emit_finish_line(env, node);
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}

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static void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
	Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
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}

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static void emit_ia32_PsiCondSet(ia32_emit_env_t *env, const ir_node *node) {
	Set_emitter(env, node, get_irn_mode(get_irn_n(node, 0)));
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}

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static void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
	Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
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}

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static void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *<