ia32_finish.c 13 KB
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/*
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 * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
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 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

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/**
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 * @file
 * @brief   This file implements functions to finalize the irg for emit.
 * @author  Christian Wuerdig
 * @version $Id$
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 */
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#include "config.h"

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#include "irnode.h"
#include "ircons.h"
#include "irgmod.h"
#include "irgwalk.h"
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#include "iredges.h"
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#include "irprintf.h"
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#include "pdeq.h"
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#include "error.h"
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#include "../bearch.h"
#include "../besched.h"
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#include "../benode.h"
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#include "bearch_ia32_t.h"
#include "ia32_finish.h"
#include "ia32_new_nodes.h"
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#include "ia32_common_transform.h"
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#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
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#include "gen_ia32_regalloc_if.h"
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DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

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COMPILETIME_ASSERT((int)pn_ia32_Sub_res   == pn_ia32_Sbb_res,   pn_ia32_Sub_res);
COMPILETIME_ASSERT((int)pn_ia32_Sub_flags == pn_ia32_Sbb_flags, pn_ia32_Sub_flags);

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/**
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 * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG.
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 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
 */
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static void ia32_transform_sub_to_neg_add(ir_node *irn)
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{
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	ir_graph *irg;
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	ir_node *in1, *in2, *noreg, *nomem, *res;
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	ir_node *noreg_fp, *block;
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	dbg_info *dbgi;
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	const arch_register_t *in1_reg, *in2_reg, *out_reg;
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	/* fix_am will solve this for AddressMode variants */
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	if (get_ia32_op_type(irn) != ia32_Normal)
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		return;

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	irg      = get_irn_irg(irn);
	noreg    = ia32_new_NoReg_gp(irg);
	noreg_fp = ia32_new_NoReg_xmm(irg);
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	nomem    = get_irg_no_mem(irg);
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	in1      = get_irn_n(irn, n_ia32_binary_left);
	in2      = get_irn_n(irn, n_ia32_binary_right);
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	in1_reg  = arch_get_irn_register(in1);
	in2_reg  = arch_get_irn_register(in2);
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	out_reg  = arch_irn_get_register(irn, 0);
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	if (out_reg == in1_reg)
		return;

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	/* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
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	if (out_reg != in2_reg)
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		return;

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	block = get_nodes_block(irn);
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	dbgi   = get_irn_dbg_info(irn);
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	/* generate the neg src2 */
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	if (is_ia32_xSub(irn)) {
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		int size;
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		ir_entity *entity;
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		ir_mode *op_mode = get_ia32_ls_mode(irn);
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		assert(get_irn_mode(irn) != mode_T);

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		res = new_bd_ia32_xXor(dbgi, block, noreg, noreg, nomem, in2, noreg_fp);
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		size = get_mode_size_bits(op_mode);
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		entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
		set_ia32_am_sc(res, entity);
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		set_ia32_op_type(res, ia32_AddrModeS);
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		set_ia32_ls_mode(res, op_mode);
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		arch_set_irn_register(res, in2_reg);
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		/* add to schedule */
		sched_add_before(irn, res);

		/* generate the add */
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		res = new_bd_ia32_xAdd(dbgi, block, noreg, noreg, nomem, res, in1);
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		set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
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		/* exchange the add and the sub */
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		edges_reroute(irn, res);
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		/* add to schedule */
		sched_add_before(irn, res);
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	} else {
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		ir_node         *res_proj   = NULL;
		ir_node         *flags_proj = NULL;
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		ir_node         *carry;
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		const ir_edge_t *edge;

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		if (get_irn_mode(irn) == mode_T) {
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			/* collect the Proj uses */
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			foreach_out_edge(irn, edge) {
				ir_node *proj = get_edge_src_irn(edge);
				long     pn   = get_Proj_proj(proj);
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				if (pn == pn_ia32_Sub_res) {
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					assert(res_proj == NULL);
					res_proj = proj;
				} else {
					assert(pn == pn_ia32_Sub_flags);
					assert(flags_proj == NULL);
					flags_proj = proj;
				}
			}
		}
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		if (is_ia32_Sbb(irn)) {
			/* Feed borrow (in CF) as carry (via CMC) into NOT+ADC. */
			carry = get_irn_n(irn, n_ia32_Sbb_eflags);
			carry = new_bd_ia32_Cmc(dbgi, block, carry);
			goto carry;
		} else if (flags_proj != 0) {
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			/*
			 * ARG, the above technique does NOT set the flags right.
			 * So, we must produce the following code:
			 * t1 = ~b
			 * t2 = a + ~b + Carry
			 * Complement Carry
			 *
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			 * a + -b = a + (~b + 1)  would set the carry flag wrong IFF both a and b are zero.
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			 */
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			ir_node *cmc;
			ir_node *nnot;
			ir_node *adc;
			ir_node *adc_flags;

			carry = new_bd_ia32_Stc(dbgi, block);

carry:
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			nnot = new_bd_ia32_Not(dbgi, block, in2);
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			arch_set_irn_register(nnot, in2_reg);
			sched_add_before(irn, nnot);
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			arch_set_irn_register(carry, &ia32_registers[REG_EFLAGS]);
			sched_add_before(irn, carry);
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			adc = new_bd_ia32_Adc(dbgi, block, noreg, noreg, nomem, nnot, in1, carry);
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			arch_set_irn_register(adc, out_reg);
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			sched_add_before(irn, adc);

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			set_irn_mode(adc, mode_T);
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			adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
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			arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
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			if (flags_proj != NULL) {
				cmc = new_bd_ia32_Cmc(dbgi, block, adc_flags);
				arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
				sched_add_before(irn, cmc);
				exchange(flags_proj, cmc);
			}
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			if (res_proj != NULL) {
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				set_Proj_pred(res_proj, adc);
				set_Proj_proj(res_proj, pn_ia32_Adc_res);
			}

			res = adc;
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		} else {
			res = new_bd_ia32_Neg(dbgi, block, in2);
			arch_set_irn_register(res, in2_reg);

			/* add to schedule */
			sched_add_before(irn, res);

			/* generate the add */
			res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, res, in1);
			arch_set_irn_register(res, out_reg);
			set_ia32_commutative(res);

			/* exchange the add and the sub */
			edges_reroute(irn, res);

			/* add to schedule */
			sched_add_before(irn, res);
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		}
	}

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	set_irn_mode(res, get_irn_mode(irn));

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	SET_IA32_ORIG_NODE(res, irn);
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	/* remove the old sub */
	sched_remove(irn);
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	kill_node(irn);
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	DBG_OPT_SUB2NEGADD(irn, res);
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}

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static inline int need_constraint_copy(ir_node *irn)
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{
	/* TODO this should be determined from the node specification */
	switch (get_ia32_irn_opcode(irn)) {
		case iro_ia32_IMul: {
			/* the 3 operand form of IMul needs no constraint copy */
			ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
			return !is_ia32_Immediate(right);
		}

		case iro_ia32_Lea:
		case iro_ia32_Conv_I2I:
		case iro_ia32_Conv_I2I8Bit:
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		case iro_ia32_CMovcc:
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			return 0;

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		default:
			return 1;
	}
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}

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/**
 * Returns the index of the "same" register.
 * On the x86, we should have only one.
 */
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static int get_first_same(const arch_register_req_t* req)
{
	const unsigned other = req->other_same;
	int i;

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	for (i = 0; i < 32; ++i) {
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		if (other & (1U << i)) return i;
	}
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	panic("same position not found");
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}

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/**
 * Insert copies for all ia32 nodes where the should_be_same requirement
 * is not fulfilled.
 * Transform Sub into Neg -- Add if IN2 == OUT
 */
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static void assure_should_be_same_requirements(ir_node *node)
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{
	const arch_register_t      *out_reg, *in_reg;
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	int                         n_res, i;
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	ir_node                    *in_node, *block;
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	n_res = arch_irn_get_n_outs(node);
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	block = get_nodes_block(node);

	/* check all OUT requirements, if there is a should_be_same */
	for (i = 0; i < n_res; i++) {
		int                          i2, arity;
		int                          same_pos;
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		ir_node                     *uses_out_reg;
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		const arch_register_req_t   *req = arch_get_out_register_req(node, i);
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		const arch_register_class_t *cls;
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		int                         uses_out_reg_pos;
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		if (!arch_register_req_is(req, should_be_same))
			continue;

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		same_pos = get_first_same(req);
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		/* get in and out register */
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		out_reg = arch_irn_get_register(node, i);
		in_node = get_irn_n(node, same_pos);
		in_reg  = arch_get_irn_register(in_node);
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		/* requirement already fulfilled? */
		if (in_reg == out_reg)
			continue;
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		cls = arch_register_get_class(in_reg);
		assert(cls == arch_register_get_class(out_reg));
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		/* check if any other input operands uses the out register */
		arity = get_irn_arity(node);
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		uses_out_reg     = NULL;
		uses_out_reg_pos = -1;
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		for (i2 = 0; i2 < arity; ++i2) {
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			ir_node               *in     = get_irn_n(node, i2);
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			const arch_register_t *other_in_reg;
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			if (!mode_is_data(get_irn_mode(in)))
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				continue;

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			other_in_reg = arch_get_irn_register(in);
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			if (other_in_reg != out_reg)
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				continue;

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			if (uses_out_reg != NULL && in != uses_out_reg) {
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				panic("invalid register allocation");
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			}
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			uses_out_reg = in;
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			if (uses_out_reg_pos >= 0)
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				uses_out_reg_pos = -1; /* multiple inputs... */
			else
				uses_out_reg_pos = i2;
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		}

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		/* no-one else is using the out reg, we can simply copy it
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		 * (the register can't be live since the operation will override it
		 *  anyway) */
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		if (uses_out_reg == NULL) {
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			ir_node *copy = be_new_Copy(cls, block, in_node);
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			DBG_OPT_2ADDRCPY(copy);
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			/* destination is the out register */
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			arch_set_irn_register(copy, out_reg);
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			/* insert copy before the node into the schedule */
			sched_add_before(node, copy);

			/* set copy as in */
			set_irn_n(node, same_pos, copy);

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			DBG((dbg, LEVEL_1,
				"created copy %+F for should be same argument at input %d of %+F\n",
				copy, same_pos, node));
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			continue;
		}

		/* for commutative nodes we can simply swap the left/right */
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		if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
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			ia32_swap_left_right(node);
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			DBG((dbg, LEVEL_1,
				"swapped left/right input of %+F to resolve should be same constraint\n",
				node));
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			continue;
		}

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		panic("Unresolved should_be_same constraint");
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	}
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}

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/**
 * Following Problem:
 * We have a source address mode node with base or index register equal to
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 * result register and unfulfilled should_be_same requirement. The constraint
 * handler will insert a copy from the remaining input operand to the result
 * register -> base or index is broken then.
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 * Solution: Turn back this address mode into explicit Load + Operation.
 */
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static void fix_am_source(ir_node *irn)
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{
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	int                         n_res, i;
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	/* check only ia32 nodes with source address mode */
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	if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
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		return;
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	/* only need to fix binary operations */
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	if (get_ia32_am_support(irn) != ia32_am_binary)
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		return;
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	n_res = arch_irn_get_n_outs(irn);
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	for (i = 0; i < n_res; i++) {
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		const arch_register_req_t *req = arch_get_out_register_req(irn, i);
		const arch_register_t     *out_reg;
		int                        same_pos;
		ir_node                   *same_node;
		const arch_register_t     *same_reg;
		ir_node                   *load_res;
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		if (!arch_register_req_is(req, should_be_same))
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			continue;
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		/* get in and out register */
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		out_reg   = arch_irn_get_register(irn, i);
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		same_pos  = get_first_same(req);
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		same_node = get_irn_n(irn, same_pos);
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		same_reg  = arch_get_irn_register(same_node);
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		/* should_be same constraint is fullfilled, nothing to do */
		if (out_reg == same_reg)
			continue;
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		/* we only need to do something if the out reg is the same as base
			 or index register */
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		if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
				out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
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			continue;
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		load_res = ia32_turn_back_am(irn);
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		arch_set_irn_register(load_res, out_reg);
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		DBG((dbg, LEVEL_3,
			"irg %+F: build back AM source for node %+F, inserted load %+F\n",
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			get_irn_irg(irn), irn, get_Proj_pred(load_res)));
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		break;
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	}
}

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/**
 * Block walker: finishes a block
 */
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static void ia32_finish_irg_walker(ir_node *block, void *env)
{
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	ir_node *irn, *next;
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	(void) env;
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	/* first: turn back AM source if necessary */
	for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
		next = sched_next(irn);
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		fix_am_source(irn);
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	}

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	for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
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		next = sched_next(irn);
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		/* check if there is a sub which need to be transformed */
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		if (is_ia32_Sub(irn) || is_ia32_Sbb(irn) || is_ia32_xSub(irn)) {
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			ia32_transform_sub_to_neg_add(irn);
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		}
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	}

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	/* second: insert copies and finish irg */
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	for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
		next = sched_next(irn);
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		if (is_ia32_irn(irn)) {
			/* some nodes are just a bit less efficient, but need no fixing if the
			 * should be same requirement is not fulfilled */
			if (need_constraint_copy(irn))
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				assure_should_be_same_requirements(irn);
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		}
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	}
}

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/**
 * Block walker: pushes all blocks on a wait queue
 */
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static void ia32_push_on_queue_walker(ir_node *block, void *env)
{
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	waitq *wq = (waitq*)env;
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	waitq_put(wq, block);
}


/**
 * Add Copy nodes for not fulfilled should_be_equal constraints
 */
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void ia32_finish_irg(ir_graph *irg)
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{
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	waitq *wq = new_waitq();

	/* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
	irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);

	while (! waitq_empty(wq)) {
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		ir_node *block = (ir_node*)waitq_get(wq);
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		ia32_finish_irg_walker(block, NULL);
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	}
	del_waitq(wq);
}
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void ia32_init_finish(void)
{
	FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");
}