sparc_transform.c 57.5 KB
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/*
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 * Copyright (C) 1995-2010 University of Karlsruhe.  All right reserved.
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 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

/**
 * @file
 * @brief   code selection (transform FIRM into SPARC FIRM)
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 * @version $Id$
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 */
#include "config.h"

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#include <stdint.h>

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#include "irnode_t.h"
#include "irgraph_t.h"
#include "irmode_t.h"
#include "irgmod.h"
#include "iredges.h"
#include "ircons.h"
#include "irprintf.h"
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#include "iroptimize.h"
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#include "dbginfo.h"
#include "iropt_t.h"
#include "debug.h"
#include "error.h"

#include "../benode.h"
#include "../beirg.h"
#include "../beutil.h"
#include "../betranshlp.h"
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#include "../beabihelper.h"
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#include "bearch_sparc_t.h"

#include "sparc_nodes_attr.h"
#include "sparc_transform.h"
#include "sparc_new_nodes.h"
#include "gen_sparc_new_nodes.h"

#include "gen_sparc_regalloc_if.h"
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#include "sparc_cconv.h"
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#include <limits.h>

DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

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static sparc_code_gen_t      *env_cg;
static beabi_helper_env_t    *abihelper;
static const arch_register_t *sp_reg = &sparc_gp_regs[REG_SP];
static const arch_register_t *fp_reg = &sparc_gp_regs[REG_FRAME_POINTER];
static calling_convention_t  *cconv  = NULL;
static ir_mode               *mode_gp;
static ir_mode               *mode_fp;
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static ir_mode               *mode_fp2;
//static ir_mode               *mode_fp4;
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static pmap                  *node_to_stack;
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static inline int mode_needs_gp_reg(ir_mode *mode)
{
	return mode_is_int(mode) || mode_is_reference(mode);
}

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/**
 * Create an And that will zero out upper bits.
 *
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 * @param dbgi      debug info
 * @param block     the basic block
 * @param op        the original node
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 * @param src_bits  number of lower bits that will remain
 */
static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
                                   int src_bits)
{
	if (src_bits == 8) {
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		return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
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	} else if (src_bits == 16) {
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		ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
		ir_node *rshift = new_bd_sparc_Slr_imm(dbgi, block, lshift, NULL, 16);
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		return rshift;
	} else {
		panic("zero extension only supported for 8 and 16 bits");
	}
}

/**
 * Generate code for a sign extension.
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 *
 * @param dbgi      debug info
 * @param block     the basic block
 * @param op        the original node
 * @param src_bits  number of lower bits that will remain
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 */
static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
                                   int src_bits)
{
	int shift_width = 32 - src_bits;
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	ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
	ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
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	return rshift_node;
}

/**
 * returns true if it is assured, that the upper bits of a node are "clean"
 * which means for a 16 or 8 bit value, that the upper bits in the register
 * are 0 for unsigned and a copy of the last significant bit for signed
 * numbers.
 */
static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
{
	(void) transformed_node;
	(void) mode;
	/* TODO */
	return false;
}

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/**
 * Extend a value to 32 bit signed/unsigned depending on its mode.
 *
 * @param dbgi      debug info
 * @param block     the basic block
 * @param op        the original node
 * @param orig_mode the original mode of op
 */
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static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
                              ir_mode *orig_mode)
{
	int bits = get_mode_size_bits(orig_mode);
	if (bits == 32)
		return op;

	if (mode_is_signed(orig_mode)) {
		return gen_sign_extension(dbgi, block, op, bits);
	} else {
		return gen_zero_extension(dbgi, block, op, bits);
	}
}

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typedef enum {
	MATCH_NONE         = 0,
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	MATCH_COMMUTATIVE  = 1 << 0, /**< commutative operation. */
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} match_flags_t;

typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
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typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
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typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
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typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
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static bool is_value_imm_encodeable(int32_t value)
{
	return -4096 <= value && value <= 4095;
}

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/**
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 * checks if a node's value can be encoded as a immediate
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 */
static bool is_imm_encodeable(const ir_node *node)
{
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	long value;
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	if (!is_Const(node))
		return false;

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	value = get_tarval_long(get_Const_tarval(node));
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	return is_value_imm_encodeable(value);
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}

/**
 * helper function for binop operations
 *
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 * @param new_reg  register generation function ptr
 * @param new_imm  immediate generation function ptr
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 */
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static ir_node *gen_helper_binop_args(ir_node *node,
                                      ir_node *op1, ir_node *op2,
                                      match_flags_t flags,
                                      new_binop_reg_func new_reg,
                                      new_binop_imm_func new_imm)
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{
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	dbg_info *dbgi    = get_irn_dbg_info(node);
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	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *new_op1;
	ir_node  *new_op2;

	if (is_imm_encodeable(op2)) {
		ir_node *new_op1 = be_transform_node(op1);
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		int32_t immediate = get_tarval_long(get_Const_tarval(op2));
		return new_imm(dbgi, block, new_op1, NULL, immediate);
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	}
	new_op2 = be_transform_node(op2);

	if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
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		int32_t immediate = get_tarval_long(get_Const_tarval(op1));
		return new_imm(dbgi, block, new_op2, NULL, immediate);
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	}
	new_op1 = be_transform_node(op1);

	return new_reg(dbgi, block, new_op1, new_op2);
}

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static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
                                 new_binop_reg_func new_reg,
                                 new_binop_imm_func new_imm)
{
	ir_node *op1 = get_binop_left(node);
	ir_node *op2 = get_binop_right(node);
	return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
}

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/**
 * helper function for FP binop operations
 */
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static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
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                                   new_binop_fp_func new_func_single,
                                   new_binop_fp_func new_func_double,
                                   new_binop_fp_func new_func_quad)
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{
	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *op1     = get_binop_left(node);
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	ir_node  *new_op1 = be_transform_node(op1);
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	ir_node  *op2     = get_binop_right(node);
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	ir_node  *new_op2 = be_transform_node(op2);
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	dbg_info *dbgi    = get_irn_dbg_info(node);
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	unsigned  bits    = get_mode_size_bits(mode);

	switch (bits) {
	case 32:
		return new_func_single(dbgi, block, new_op1, new_op2, mode);
	case 64:
		return new_func_double(dbgi, block, new_op1, new_op2, mode);
	case 128:
		return new_func_quad(dbgi, block, new_op1, new_op2, mode);
	default:
		break;
	}
	panic("unsupported mode %+F for float op", mode);
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}

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static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
                                  new_unop_fp_func new_func_single,
                                  new_unop_fp_func new_func_double,
                                  new_unop_fp_func new_func_quad)
{
	ir_node  *block   = be_transform_node(get_nodes_block(node));
	ir_node  *op1     = get_binop_left(node);
	ir_node  *new_op1 = be_transform_node(op1);
	dbg_info *dbgi    = get_irn_dbg_info(node);
	unsigned  bits    = get_mode_size_bits(mode);

	switch (bits) {
	case 32:
		return new_func_single(dbgi, block, new_op1, mode);
	case 64:
		return new_func_double(dbgi, block, new_op1, mode);
	case 128:
		return new_func_quad(dbgi, block, new_op1, mode);
	default:
		break;
	}
	panic("unsupported mode %+F for float op", mode);
}

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static ir_node *get_g0(void)
{
	return be_prolog_get_reg_value(abihelper, &sparc_gp_regs[REG_G0]);
}

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typedef struct address_t {
	ir_node   *base;
	ir_entity *entity;
	int32_t    offset;
} address_t;

static void match_address(ir_node *ptr, address_t *address)
{
	ir_node   *base   = ptr;
	int32_t    offset = 0;
	ir_entity *entity = NULL;

	if (is_Add(base)) {
		ir_node *add_right = get_Add_right(base);
		if (is_Const(add_right)) {
			base    = get_Add_left(base);
			offset += get_tarval_long(get_Const_tarval(add_right));
		}
	}
	/* Note that we don't match sub(x, Const) or chains of adds/subs
	 * because this should all be normalized by now */

	/* we only use the symconst if we're the only user otherwise we probably
	 * won't save anything but produce multiple sethi+or combinations with
	 * just different offsets */
	if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
		dbg_info *dbgi      = get_irn_dbg_info(ptr);
		ir_node  *block     = get_nodes_block(ptr);
		ir_node  *new_block = be_transform_node(block);
		entity = get_SymConst_entity(base);
		base   = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
	} else {
		if (is_value_imm_encodeable(offset)) {
			base = be_transform_node(base);
		} else {
			base   = be_transform_node(ptr);
			offset = 0;
		}
	}

	address->base   = base;
	address->entity = entity;
	address->offset = offset;
}

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/**
 * Creates an sparc Add.
 *
 * @param node   FIRM node
 * @return the created sparc Add node
 */
static ir_node *gen_Add(ir_node *node)
{
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	ir_mode *mode = get_irn_mode(node);
	ir_node *right;
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	if (mode_is_float(mode)) {
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		return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
		                          new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
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	}
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	/* special case: + 0x1000 can be represented as - 0x1000 */
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	right = get_Add_right(node);
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	if (is_Const(right)) {
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		tarval  *tv;
		uint32_t val;
		ir_node *left = get_Add_left(node);
		/* is this simple address arithmetic? then we can let the linker do
		 * the calculation. */
		if (is_SymConst(left)) {
			dbg_info *dbgi  = get_irn_dbg_info(node);
			ir_node  *block = be_transform_node(get_nodes_block(node));
			address_t address;

			match_address(node, &address);
			assert(is_sparc_SetHi(address.base));
			return new_bd_sparc_Or_imm(dbgi, block, address.base,
			                           address.entity, address.offset);
		}

		tv  = get_Const_tarval(right);
		val = get_tarval_long(tv);
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		if (val == 0x1000) {
			dbg_info *dbgi   = get_irn_dbg_info(node);
			ir_node  *block  = be_transform_node(get_nodes_block(node));
			ir_node  *op     = get_Add_left(node);
			ir_node  *new_op = be_transform_node(op);
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			return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
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		}
	}

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	return gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Add_reg,
	                        new_bd_sparc_Add_imm);
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}

/**
 * Creates an sparc Sub.
 *
 * @param node       FIRM node
 * @return the created sparc Sub node
 */
static ir_node *gen_Sub(ir_node *node)
{
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	ir_mode *mode = get_irn_mode(node);
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	if (mode_is_float(mode)) {
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		return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
		                          new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
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	}
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	return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
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}

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static ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
                           ir_node *mem, ir_mode *mode, ir_entity *entity,
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                           long offset, bool is_frame_entity)
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{
	unsigned bits = get_mode_size_bits(mode);
	assert(mode_is_float(mode));
	if (bits == 32) {
		return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
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		                          offset, is_frame_entity);
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	} else if (bits == 64) {
		return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
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		                          offset, is_frame_entity);
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	} else {
		assert(bits == 128);
		return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
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		                          offset, is_frame_entity);
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	}
}

static ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
                           ir_node *value, ir_node *mem, ir_mode *mode,
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                           ir_entity *entity, long offset,
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                           bool is_frame_entity)
{
	unsigned bits = get_mode_size_bits(mode);
	assert(mode_is_float(mode));
	if (bits == 32) {
		return new_bd_sparc_Stf_s(dbgi, block, ptr, value, mem, mode, entity,
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		                          offset, is_frame_entity);
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	} else if (bits == 64) {
		return new_bd_sparc_Stf_d(dbgi, block, ptr, value, mem, mode, entity,
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		                          offset, is_frame_entity);
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	} else {
		assert(bits == 128);
		return new_bd_sparc_Stf_q(dbgi, block, ptr, value, mem, mode, entity,
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		                          offset, is_frame_entity);
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	}
}

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/**
 * Transforms a Load.
 *
 * @param node    the ir Load node
 * @return the created sparc Load node
 */
static ir_node *gen_Load(ir_node *node)
{
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	dbg_info *dbgi     = get_irn_dbg_info(node);
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	ir_mode  *mode     = get_Load_mode(node);
	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *ptr      = get_Load_ptr(node);
	ir_node  *mem      = get_Load_mem(node);
	ir_node  *new_mem  = be_transform_node(mem);
	ir_node  *new_load = NULL;
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	address_t address;

	match_address(ptr, &address);
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	if (mode_is_float(mode)) {
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		new_load = create_ldf(dbgi, block, address.base, new_mem, mode,
		                      address.entity, address.offset, false);
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	} else {
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		new_load = new_bd_sparc_Ld(dbgi, block, address.base, new_mem, mode,
		                           address.entity, address.offset, false);
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	}
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	set_irn_pinned(new_load, get_irn_pinned(node));

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	return new_load;
}

/**
 * Transforms a Store.
 *
 * @param node    the ir Store node
 * @return the created sparc Store node
 */
static ir_node *gen_Store(ir_node *node)
{
	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *ptr      = get_Store_ptr(node);
	ir_node  *mem      = get_Store_mem(node);
	ir_node  *new_mem  = be_transform_node(mem);
	ir_node  *val      = get_Store_value(node);
	ir_node  *new_val  = be_transform_node(val);
	ir_mode  *mode     = get_irn_mode(val);
	dbg_info *dbgi     = get_irn_dbg_info(node);
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	ir_node  *new_store = NULL;
	address_t address;

	match_address(ptr, &address);
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	if (mode_is_float(mode)) {
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		new_store = create_stf(dbgi, block, address.base, new_val, new_mem,
		                       mode, address.entity, address.offset, false);
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	} else {
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		new_store = new_bd_sparc_St(dbgi, block, address.base, new_val, new_mem,
		                            mode, address.entity, address.offset,
		                            false);
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	}
	set_irn_pinned(new_store, get_irn_pinned(node));
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	return new_store;
}

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/**
 * Creates an sparc Mul.
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 * returns the lower 32bits of the 64bit multiply result
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 *
 * @return the created sparc Mul node
 */
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static ir_node *gen_Mul(ir_node *node)
{
	ir_mode *mode = get_irn_mode(node);
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	if (mode_is_float(mode)) {
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		return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
		                          new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
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	}
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	assert(mode_is_data(mode));
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	return gen_helper_binop(node, MATCH_COMMUTATIVE,
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	                        new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
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}

/**
 * Creates an sparc Mulh.
 * Mulh returns the upper 32bits of a mul instruction
 *
 * @return the created sparc Mulh node
 */
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static ir_node *gen_Mulh(ir_node *node)
{
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	ir_mode *mode = get_irn_mode(node);
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	ir_node *mul;
	ir_node *proj_res_hi;

	if (mode_is_float(mode))
		panic("FP not supported yet");


	assert(mode_is_data(mode));
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	mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Mulh_reg, new_bd_sparc_Mulh_imm);
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	//arch_irn_add_flags(mul, arch_irn_flags_modify_flags);
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	proj_res_hi = new_r_Proj(mul, mode_gp, pn_sparc_Mulh_low);
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	return proj_res_hi;
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}
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static ir_node *gen_sign_extension_value(ir_node *node)
{
	ir_node *block     = get_nodes_block(node);
	ir_node *new_block = be_transform_node(block);
	ir_node *new_node  = be_transform_node(node);
	/* TODO: we could do some shortcuts for some value types probably.
	 * (For constants or other cases where we know the sign bit in
	 *  advance) */
	return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
}

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/**
 * Creates an sparc Div.
 *
 * @return the created sparc Div node
 */
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static ir_node *gen_Div(ir_node *node)
{
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	dbg_info *dbgi      = get_irn_dbg_info(node);
	ir_node  *block     = get_nodes_block(node);
	ir_node  *new_block = be_transform_node(block);
	ir_mode  *mode      = get_Div_resmode(node);
	ir_node  *left      = get_Div_left(node);
	ir_node  *left_low  = be_transform_node(left);
	ir_node  *right     = get_Div_right(node);
	ir_node  *res;
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	assert(!mode_is_float(mode));
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	if (mode_is_signed(mode)) {
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		ir_node *left_high = gen_sign_extension_value(left);

		if (is_imm_encodeable(right)) {
			int32_t immediate = get_tarval_long(get_Const_tarval(right));
			res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
			                            NULL, immediate);
		} else {
			ir_node *new_right = be_transform_node(right);
			res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
			                            new_right);
		}
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	} else {
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		ir_node *left_high = get_g0();
		if (is_imm_encodeable(right)) {
			int32_t immediate = get_tarval_long(get_Const_tarval(right));
			res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
			                            NULL, immediate);
		} else {
			ir_node *new_right = be_transform_node(right);
			res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
			                            new_right);
		}
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	}
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	return res;
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}

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static ir_node *gen_Quot(ir_node *node)
{
	ir_mode *mode = get_Quot_resmode(node);
	assert(mode_is_float(mode));
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	return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
	                          new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
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}
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static ir_node *gen_Abs(ir_node *node)
{
	ir_mode *const mode = get_irn_mode(node);
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	if (mode_is_float(mode)) {
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		return gen_helper_unfpop(node, mode, new_bd_sparc_fabs_s,
		                         new_bd_sparc_fabs_d, new_bd_sparc_fabs_q);
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	} else {
		ir_node  *const block  = be_transform_node(get_nodes_block(node));
		dbg_info *const dbgi   = get_irn_dbg_info(node);
		ir_node  *const op     = get_Abs_op(node);
		ir_node  *const new_op = be_transform_node(op);
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		ir_node  *const sra    = new_bd_sparc_Sra_imm(dbgi, block, new_op, NULL, 31);
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		ir_node  *const xor    = new_bd_sparc_Xor_reg(dbgi, block, new_op, sra);
		ir_node  *const sub    = new_bd_sparc_Sub_reg(dbgi, block, xor,    sra);
		return sub;
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	}
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}

/**
 * Transforms a Not node.
 *
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 * @return the created sparc Not node
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 */
static ir_node *gen_Not(ir_node *node)
{
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	ir_node  *op     = get_Not_op(node);
	ir_node  *zero   = get_g0();
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	dbg_info *dbgi   = get_irn_dbg_info(node);
	ir_node  *block  = be_transform_node(get_nodes_block(node));
	ir_node  *new_op = be_transform_node(op);
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	/* Note: Not(Eor()) is normalize in firm locatopts already so
	 * we don't match it for xnor here */

	/* Not can be represented with xnor 0, n */
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	return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
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}

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static ir_node *gen_And(ir_node *node)
{
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	ir_node *left  = get_And_left(node);
	ir_node *right = get_And_right(node);

	if (is_Not(right)) {
		ir_node *not_op = get_Not_op(right);
		return gen_helper_binop_args(node, left, not_op, MATCH_NONE,
		                             new_bd_sparc_AndN_reg,
		                             new_bd_sparc_AndN_imm);
	}
	if (is_Not(left)) {
		ir_node *not_op = get_Not_op(left);
		return gen_helper_binop_args(node, right, not_op, MATCH_NONE,
		                             new_bd_sparc_AndN_reg,
		                             new_bd_sparc_AndN_imm);
	}

	return gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_And_reg,
	                        new_bd_sparc_And_imm);
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}

static ir_node *gen_Or(ir_node *node)
{
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	ir_node *left  = get_Or_left(node);
	ir_node *right = get_Or_right(node);

	if (is_Not(right)) {
		ir_node *not_op = get_Not_op(right);
		return gen_helper_binop_args(node, left, not_op, MATCH_NONE,
		                             new_bd_sparc_OrN_reg,
		                             new_bd_sparc_OrN_imm);
	}
	if (is_Not(left)) {
		ir_node *not_op = get_Not_op(left);
		return gen_helper_binop_args(node, right, not_op, MATCH_NONE,
		                             new_bd_sparc_OrN_reg,
		                             new_bd_sparc_OrN_imm);
	}

	return gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Or_reg,
	                        new_bd_sparc_Or_imm);
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}

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static ir_node *gen_Eor(ir_node *node)
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{
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	ir_node *left  = get_Eor_left(node);
	ir_node *right = get_Eor_right(node);

	if (is_Not(right)) {
		ir_node *not_op = get_Not_op(right);
		return gen_helper_binop_args(node, left, not_op, MATCH_COMMUTATIVE,
		                             new_bd_sparc_XNor_reg,
		                             new_bd_sparc_XNor_imm);
	}
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	if (is_Not(left)) {
		ir_node *not_op = get_Not_op(left);
		return gen_helper_binop_args(node, not_op, right,
		                             MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
		                             new_bd_sparc_XNor_reg,
		                             new_bd_sparc_XNor_imm);
	}
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	return gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Xor_reg,
	                        new_bd_sparc_Xor_imm);
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}

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static ir_node *gen_Shl(ir_node *node)
{
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	return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
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}

static ir_node *gen_Shr(ir_node *node)
{
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	return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Slr_reg, new_bd_sparc_Slr_imm);
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}
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static ir_node *gen_Shrs(ir_node *node)
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{
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	return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
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}

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/**
 * Transforms a Minus node.
 */
static ir_node *gen_Minus(ir_node *node)
{
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	ir_mode  *mode = get_irn_mode(node);
	ir_node  *op;
	ir_node  *block;
	ir_node  *new_op;
	ir_node  *zero;
	dbg_info *dbgi;
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	if (mode_is_float(mode)) {
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		return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
		                         new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
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	}
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	block  = be_transform_node(get_nodes_block(node));
	dbgi   = get_irn_dbg_info(node);
	op     = get_Minus_op(node);
	new_op = be_transform_node(op);
	zero   = get_g0();
	return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
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}

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/**
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 * Create an entity for a given (floating point) tarval
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 */
static ir_entity *create_float_const_entity(tarval *tv)
{
	ir_entity        *entity = (ir_entity*) pmap_get(env_cg->constants, tv);
	ir_initializer_t *initializer;
	ir_mode          *mode;
	ir_type          *type;
	ir_type          *glob;

	if (entity != NULL)
		return entity;

	mode   = get_tarval_mode(tv);
	type   = get_type_for_mode(mode);
	glob   = get_glob_type();
	entity = new_entity(glob, id_unique("C%u"), type);
	set_entity_visibility(entity, ir_visibility_private);
	add_entity_linkage(entity, IR_LINKAGE_CONSTANT);

	initializer = create_initializer_tarval(tv);
	set_entity_initializer(entity, initializer);

	pmap_insert(env_cg->constants, tv, entity);
	return entity;
}

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static ir_node *gen_Const(ir_node *node)
{
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	ir_node  *block = be_transform_node(get_nodes_block(node));
	ir_mode  *mode  = get_irn_mode(node);
	dbg_info *dbgi  = get_irn_dbg_info(node);
	tarval   *tv;
	long      value;
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	if (mode_is_float(mode)) {
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		tarval    *tv     = get_Const_tarval(node);
		ir_entity *entity = create_float_const_entity(tv);
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		ir_node   *hi     = new_bd_sparc_SetHi(dbgi, block, entity, 0);
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		ir_node   *mem    = new_NoMem();
		ir_node   *new_op
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			= create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
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		ir_node   *proj   = new_Proj(new_op, mode, pn_sparc_Ldf_res);
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		be_dep_on_frame(hi);
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		set_irn_pinned(new_op, op_pin_state_floats);
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		return proj;
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	}
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	tv    = get_Const_tarval(node);
	value = get_tarval_long(tv);
	if (value == 0) {
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		return get_g0();
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	} else if (-4096 <= value && value <= 4095) {
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		return new_bd_sparc_Or_imm(dbgi, block, get_g0(), NULL, value);
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	} else {
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		ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
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		be_dep_on_frame(hi);
		if ((value & 0x3ff) != 0) {
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			return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
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		} else {
			return hi;
		}
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	}
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}

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static ir_mode *get_cmp_mode(ir_node *b_value)
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{
	ir_node *pred;
	ir_node *op;

	if (!is_Proj(b_value))
		panic("can't determine cond signednes");
	pred = get_Proj_pred(b_value);
	if (!is_Cmp(pred))
		panic("can't determine cond signednes (no cmp)");
	op = get_Cmp_left(pred);
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	return get_irn_mode(op);
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}

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/**
 * Transform Cond nodes
 */
static ir_node *gen_Cond(ir_node *node)
{
	ir_node  *selector = get_Cond_selector(node);
	ir_mode  *mode     = get_irn_mode(selector);
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	ir_mode  *cmp_mode;
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	ir_node  *block;
	ir_node  *flag_node;
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	bool      is_unsigned;
	pn_Cmp    pnc;
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	dbg_info *dbgi;

	// switch/case jumps
	if (mode != mode_b) {
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		panic("SwitchJump not implemented yet");
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	}

	// regular if/else jumps
	assert(is_Proj(selector));
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	assert(is_Cmp(get_Proj_pred(selector)));
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	cmp_mode = get_cmp_mode(selector);

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	block       = be_transform_node(get_nodes_block(node));
	dbgi        = get_irn_dbg_info(node);
	flag_node   = be_transform_node(get_Proj_pred(selector));
	pnc         = get_Proj_proj(selector);
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	is_unsigned = !mode_is_signed(cmp_mode);
	if (mode_is_float(cmp_mode)) {
		assert(!is_unsigned);
		return new_bd_sparc_fbfcc(dbgi, block, flag_node, pnc);
	} else {
		return new_bd_sparc_Bicc(dbgi, block, flag_node, pnc, is_unsigned);
	}
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}

/**
 * transform Cmp
 */
static ir_node *gen_Cmp(ir_node *node)
{
	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *op1      = get_Cmp_left(node);
	ir_node  *op2      = get_Cmp_right(node);
	ir_mode  *cmp_mode = get_irn_mode(op1);
	dbg_info *dbgi     = get_irn_dbg_info(node);
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	ir_node  *new_op1  = be_transform_node(op1);
	ir_node  *new_op2  = be_transform_node(op2);
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	assert(get_irn_mode(op2) == cmp_mode);

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	if (mode_is_float(cmp_mode)) {
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		unsigned bits = get_mode_size_bits(cmp_mode);
		if (bits == 32) {
			return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
		} else if (bits == 64) {
			return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
		} else {
			assert(bits == 128);
			return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
		}
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	}

	/* integer compare */
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	new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
	new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
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	return new_bd_sparc_Cmp_reg(dbgi, block, new_op1, new_op2);
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}

/**
 * Transforms a SymConst node.
 */
static ir_node *gen_SymConst(ir_node *node)
{
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	ir_entity *entity    = get_SymConst_entity(node);
	dbg_info  *dbgi      = get_irn_dbg_info(node);
	ir_node   *block     = get_nodes_block(node);
	ir_node   *new_block = be_transform_node(block);
	ir_node   *hi        = new_bd_sparc_SetHi(dbgi, new_block, entity, 0);
	ir_node   *low       = new_bd_sparc_Or_imm(dbgi, new_block, hi, entity, 0);
	be_dep_on_frame(hi);
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	return low;
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}

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static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
                             ir_mode *src_mode, ir_mode *dst_mode)
{
	unsigned src_bits = get_mode_size_bits(src_mode);
	unsigned dst_bits = get_mode_size_bits(dst_mode);
	if (src_bits == 32) {
		if (dst_bits == 64) {
			return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
		} else {
			assert(dst_bits == 128);
			return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
		}
	} else if (src_bits == 64) {
		if (dst_bits == 32) {
			return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
		} else {
			assert(dst_bits == 128);
			return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
		}
	} else {
		assert(src_bits == 128);
		if (dst_bits == 32) {
			return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
		} else {
			assert(dst_bits == 64);
			return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
		}
	}
}

static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
                            ir_mode *src_mode)
{
	unsigned bits = get_mode_size_bits(src_mode);
	if (bits == 32) {
		return new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
	} else if (bits == 64) {
		return new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
	} else {
		assert(bits == 128);
		return new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
	}
}

static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
                            ir_mode *dst_mode)
{
	unsigned bits = get_mode_size_bits(dst_mode);
	if (bits == 32) {
		return new_bd_sparc_fitof_s(dbgi, block, op, dst_mode);
	} else if (bits == 64) {
		return new_bd_sparc_fitof_d(dbgi, block, op, dst_mode);
	} else {
		assert(bits == 128);
		return new_bd_sparc_fitof_q(dbgi, block, op, dst_mode);
	}
}

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/**
 * Transforms a Conv node.
 *
 */
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static ir_node *gen_Conv(ir_node *node)
{
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	ir_node  *block    = be_transform_node(get_nodes_block(node));
	ir_node  *op       = get_Conv_op(node);
	ir_node  *new_op   = be_transform_node(op);
	ir_mode  *src_mode = get_irn_mode(op);
	ir_mode  *dst_mode = get_irn_mode(node);
	dbg_info *dbg      = get_irn_dbg_info(node);

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	int src_bits = get_mode_size_bits(src_mode);
	int dst_bits = get_mode_size_bits(dst_mode);

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	if (src_mode == dst_mode)
		return new_op;

	if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
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		assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");

		if (mode_is_float(src_mode)) {
			if (mode_is_float(dst_mode)) {
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				/* float -> float conv */
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				return create_fftof(dbg, block, new_op, src_mode, dst_mode);
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			} else {
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				/* float -> int conv */
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				if (!mode_is_signed(dst_mode))
					panic("float to unsigned not implemented yet");
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				return create_ftoi(dbg, block, new_op, src_mode);
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			}
		} else {
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			/* int -> float conv */
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			if (!mode_is_signed(src_mode))
				panic("unsigned to float not implemented yet");
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			return create_itof(dbg, block, new_op, dst_mode);
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		}
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	} else { /* complete in gp registers */
		int min_bits;
		ir_mode *min_mode;

		if (src_bits == dst_bits) {
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			/* kill unnecessary conv */
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			return new_op;
		}

		if (src_bits < dst_bits) {
			min_bits = src_bits;
			min_mode = src_mode;
		} else {
			min_bits = dst_bits;
			min_mode = dst_mode;
		}

		if (upper_bits_clean(new_op, min_mode)) {
			return new_op;
		}

		if (mode_is_signed(min_mode)) {
			return gen_sign_extension(dbg, block, new_op, min_bits);
		} else {
			return gen_zero_extension(dbg, block, new_op, min_bits);
		}
	}
}

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static ir_node *gen_Unknown(ir_node *node)
{
	/* just produce a 0 */
	ir_mode *mode = get_irn_mode(node);
	if (mode_is_float(mode)) {
		panic("FP not implemented");
		be_dep_on_frame(node);
		return node;
	} else if (mode_needs_gp_reg(mode)) {
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		return get_g0();
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	}

	panic("Unexpected Unknown mode");
}

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/**
 * Produces the type which sits between the stack args and the locals on the
 * stack.
 */
static ir_type *sparc_get_between_type(void)
{
	static ir_type *between_type = NULL;

	if (between_type == NULL) {
		between_type = new_type_class(new_id_from_str("sparc_between_type"));
		set_type_size_bytes(between_type, SPARC_MIN_STACKSIZE);
	}

	return between_type;
}

static void create_stacklayout(ir_graph *irg)
{
	ir_entity         *entity        = get_irg_entity(irg);
	ir_type           *function_type = get_entity_type(entity);
	be_stack_layout_t *layout        = be_get_irg_stack_layout(irg);
	ir_type           *arg_type;
	int                p;
	int                n_params;

	/* calling conventions must be decided by now */
	assert(cconv != NULL);

	/* construct argument type */
	arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
	n_params = get_method_n_params(function_type);
	for (p = 0; p < n_params; ++p) {
		reg_or_stackslot_t *param = &cconv->parameters[p];
		char                buf[128];
		ident              *id;

		if (param->type == NULL)
			continue;

		snprintf(buf, sizeof(buf), "param_%d", p);
		id            = new_id_from_str(buf);
		param->entity = new_entity(arg_type, id, param->type);
		set_entity_offset(param->entity, param->offset);
	}

	memset(layout, 0, sizeof(*layout));

	layout->frame_type     = get_irg_frame_type(irg);
	layout->between_type   = sparc_get_between_type();
	layout->arg_type       = arg_type;
	layout->initial_offset = 0;
	layout->initial_bias   = 0;
	layout->stack_dir      = -1;
	layout->sp_relative    = false;

	assert(N_FRAME_TYPES == 3);
	layout->order[0] = layout->frame_type;
	layout->order[1] = layout->between_type;
	layout->order[2] = layout->arg_type;
}

/**
 * transform the start node to the prolog code + initial barrier
 */
static ir_node *gen_Start(ir_node *node)
{
	ir_graph  *irg           = get_irn_irg(node);
	ir_entity *entity        = get_irg_entity(irg);
	ir_type   *function_type = get_entity_type(entity);
	ir_node   *block         = get_nodes_block(node);
	ir_node   *new_block     = be_transform_node(block);
	dbg_info  *dbgi          = get_irn_dbg_info(node);
	ir_node   *mem;
	ir_node   *start;
	ir_node   *sp;
	ir_node   *fp;
	ir_node   *barrier;
	ir_node   *save;
	int        i;

	/* stackpointer is important at function prolog */
	be_prolog_add_reg(abihelper, sp_reg,
			arch_register_req_type_produces_sp | arch_register_req_type_ignore);
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	be_prolog_add_reg(abihelper, &sparc_gp_regs[REG_G0],
	        arch_register_req_type_ignore);
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	/* function parameters in registers */
	for (i = 0; i < get_method_n_params(function_type); ++i) {
		const reg_or_stackslot_t *param = &cconv->parameters[i];
		if (param->reg0 != NULL)
			be_prolog_add_reg(abihelper, param->reg0, 0);
		if (param->reg1 != NULL)
			be_prolog_add_reg(abihelper, param->reg1, 0);
	}

	start = be_prolog_create_start(abihelper, dbgi, new_block);

	mem  = be_prolog_get_memory(abihelper);
	sp   = be_prolog_get_reg_value(abihelper, sp_reg);
	save = new_bd_sparc_Save(NULL, block, sp, mem, SPARC_MIN_STACKSIZE);
	fp   = new_r_Proj(save, mode_gp, pn_sparc_Save_frame);
	sp   = new_r_Proj(save, mode_gp, pn_sparc_Save_stack);
	mem  = new_r_Proj(save, mode_M, pn_sparc_Save_mem);
	arch_set_irn_register(fp, fp_reg);
	arch_set_irn_register(sp, sp_reg);

	be_prolog_add_reg(abihelper, fp_reg, arch_register_req_type_ignore);
	be_prolog_set_reg_value(abihelper, fp_reg, fp);

	sp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
	be_prolog_set_reg_value(abihelper, sp_reg, sp);
	be_prolog_set_memory(abihelper, mem);

	barrier = be_prolog_create_barrier(abihelper, new_block);

	return barrier;
}

static ir_node *get_stack_pointer_for(ir_node *node)
{
	/* get predecessor in stack_order list */
	ir_node *stack_pred = be_get_stack_pred(abihelper, node);
	ir_node *stack_pred_transformed;
	ir_node *stack;

	if (stack_pred == NULL) {
		/* first stack user in the current block. We can simply use the
		 * initial sp_proj for it */
		ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
		return sp_proj;
	}

	stack_pred_transformed = be_transform_node(stack_pred);
	stack                  = pmap_get(node_to_stack, stack_pred);
	if (stack == NULL) {
		return get_stack_pointer_for(stack_pred);
	}

	return stack;
}

/**
 * transform a Return node into epilogue code + return statement
 */
static ir_node *gen_Return(ir_node *node)
{
	ir_node  *block          = get_nodes_block(node);
	ir_node  *new_block      = be_transform_node(block);
	dbg_info *dbgi           = get_irn_dbg_info(node);
	ir_node  *mem            = get_Return_mem(node);
	ir_node  *new_mem        = be_transform_node(mem);
	ir_node  *sp_proj        = get_stack_pointer_for(node);
	int       n_res          = get_Return_n_ress(node);
	ir_node  *bereturn;
	ir_node  *incsp;
	int       i;

	be_epilog_begin(abihelper);
	be_epilog_set_memory(abihelper, new_mem);
	/* connect stack pointer with initial stack pointer. fix_stack phase
	   will later serialize all stack pointer adjusting nodes */
	be_epilog_add_reg(abihelper, sp_reg,
			arch_register_req_type_produces_sp | arch_register_req_type_ignore,
			sp_proj);

	/* result values */
	for (i = 0; i < n_res; ++i) {
		ir_node                  *res_value     = get_Return_res(node, i);
		ir_node                  *new_res_value = be_transform_node(res_value);
		const reg_or_stackslot_t *slot          = &cconv->results[i];
		const arch_register_t    *reg           = slot->reg0;
		assert(slot->reg1 == NULL);
		be_epilog_add_reg(abihelper, reg, 0, new_res_value);
	}

	/* create the barrier before the epilog code */
	be_epilog_create_barrier(abihelper, new_block);

	/* epilog code: an incsp */
	sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
	incsp   = be_new_IncSP(sp_reg, new_block, sp_proj,
	                       BE_STACK_FRAME_SIZE_SHRINK, 0);
	be_epilog_set_reg_value(abihelper, sp_reg, incsp);

	bereturn = be_epilog_create_return(abihelper, dbgi, new_block);

	return bereturn;
}

static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
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{
	ir_graph *irg   = current_ir_graph;
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	ir_node  *sp    = get_irg_frame(irg);
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	ir_node  *nomem = new_NoMem();
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	ir_node  *st    = new_bd_sparc_St(dbgi, block, sp, value0, nomem, mode_gp,
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	                                  NULL, 0, true);
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	ir_mode  *mode;
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	ir_node  *ldf;
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	ir_node  *mem;
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	set_irn_pinned(st, op_pin_state_floats);

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	if (value1 != NULL) {
		ir_node *st1 = new_bd_sparc_St(dbgi, block, sp, value1, nomem, mode_gp,
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		ir_node *in[2] = { st, st1 };
		ir_node *sync  = new_r_Sync(block, 2, in);
		set_irn_pinned(st1, op_pin_state_floats);
		mem  = sync;
		mode = mode_fp2;
	} else {
		mem  = st;
		mode = mode_fp;
	}

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	ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
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	set_irn_pinned(ldf, op_pin_state_floats);

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	return new_Proj(ldf, mode, pn_sparc_Ldf_res);
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}

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static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
                                 ir_node *node, ir_mode *float_mode,
                                 ir_node **result)
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{
	ir_graph *irg   = current_ir_graph;
	ir_node  *stack = get_irg_frame(irg);
	ir_node  *nomem = new_NoMem();
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	int       bits  = get_mode_size_bits(float_mode);
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	ir_node  *ld;
	set_irn_pinned(stf, op_pin_state_floats);

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	ld = new_bd_sparc_Ld(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
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	set_irn_pinned(ld, op_pin_state_floats);
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	result[0] = new_Proj(ld, mode_gp, pn_sparc_Ld_res);
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	if (bits == 64) {
		ir_node *ld2 = new_bd_sparc_Ld(dbgi, block, stack, stf, mode_gp,
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		                               NULL, 4, true);
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		set_irn_pinned(ld, op_pin_state_floats);
		result[1] = new_Proj(ld2, mode_gp, pn_sparc_Ld_res);

		arch_irn_add_flags(ld, sparc_arch_irn_flag_needs_64bit_spillslot);
		arch_irn_add_flags(ld2, sparc_arch_irn_flag_needs_64bit_spillslot);
	} else {
		assert(bits == 32);
		result[1] = NULL;
	}
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}

static ir_node *gen_Call(ir_node *node)
{
	ir_graph        *irg          = get_irn_irg(node);
	ir_node         *callee       = get_Call_ptr(node);
	ir_node         *block        = get_nodes_block(node);
	ir_node         *new_block    = be_transform_node(block);
	ir_node         *mem          = get_Call_mem(node);
	ir_node         *new_mem      = be_transform_node(mem);
	dbg_info        *dbgi         = get_irn_dbg_info(node);
	ir_type         *type         = get_Call_type(node);
	int              n_params     = get_Call_n_params(node);
	int              n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
	/* max inputs: memory, callee, register arguments */
	int              max_inputs   = 2 + n_param_regs;
	ir_node        **in           = ALLOCAN(ir_node*, max_inputs);
	ir_node        **sync_ins     = ALLOCAN(ir_node*, max_inputs);
	struct obstack  *obst         = be_get_be_obst(irg);
	const arch_register_req_t **in_req
		= OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
	calling_convention_t *cconv
		= sparc_decide_calling_convention(type, true);
	int              in_arity     = 0;
	int              sync_arity   = 0;
	int              n_caller_saves
		= sizeof(caller_saves)/sizeof(caller_saves[0]);
	ir_entity       *entity       = NULL;
	ir_node         *new_frame    = get_stack_pointer_for(node);
	ir_node         *incsp;
	int              mem_pos;
	ir_node         *res;
	int              p;
	int              i;
	int              o;
	int              out_arity;

	assert(n_params == get_method_n_params(type));

	/* construct arguments */

	/* memory input */
	in_req[in_arity] = arch_no_register_req;
	mem_pos          = in_arity;
	++in_arity;

	/* stack pointer input */
	/* construct an IncSP -> we have to always be sure that the stack is
	 * aligned even if we don't push arguments on it */
	incsp = be_new_IncSP(sp_reg, new_block, new_frame,
	                     cconv->param_stack_size, 1);
	in_req[in_arity] = sp_reg->single_req;
	in[in_arity]     = incsp;
	++in_arity;

	/* parameters */
	for (p = 0; p < n_params; ++p) {
		ir_node                  *value      = get_Call_param(node, p);
		ir_node                  *new_value  = be_transform_node(value);
		const reg_or_stackslot_t *param      = &cconv->parameters[p];
		ir_type                  *param_type = get_method_param_type(type, p);
		ir_mode                  *mode       = get_type_mode(param_type);
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		ir_node                  *new_values[2];
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		ir_node                  *str;

		if (mode_is_float(mode) && param->reg0 != NULL) {
			unsigned size_bits = get_mode_size_bits(mode);
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			assert(size_bits <= 64);
			bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
		} else {
			new_values[0] = new_value;
			new_values[1] = NULL;
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		}

		/* put value into registers */
		if (param->reg0 != NULL) {
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			in[in_arity]     = new_values[0];
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			in_req[in_arity] = param->reg0->single_req;
			++in_arity;
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