ia32_common_transform.c 27.1 KB
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/*
 * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

/**
 * @file
 * @brief       This file implements the common parts of IR transformation from
 *              firm into ia32-Firm.
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 * @author      Matthias Braun, Sebastian Buchwald
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 */
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#include "config.h"
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#include "error.h"
#include "ircons.h"
#include "irprintf.h"
#include "typerep.h"
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#include "bitset.h"
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#include "heights.h"
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#include "betranshlp.h"
#include "beirg.h"
#include "beabi.h"
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#include "ia32_architecture.h"
#include "ia32_common_transform.h"
#include "ia32_new_nodes.h"

#include "gen_ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"

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ir_heights_t *ia32_heights = NULL;
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static int check_immediate_constraint(long val, char immediate_constraint_type)
{
	switch (immediate_constraint_type) {
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		case 0:
		case 'i': return 1;

		case 'I': return    0 <= val && val <=  31;
		case 'J': return    0 <= val && val <=  63;
		case 'K': return -128 <= val && val <= 127;
		case 'L': return val == 0xff || val == 0xffff;
		case 'M': return    0 <= val && val <=   3;
		case 'N': return    0 <= val && val <= 255;
		case 'O': return    0 <= val && val <= 127;

		default: panic("Invalid immediate constraint found");
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	}
}

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ir_type *ia32_get_prim_type(const ir_mode *mode)
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{
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	if (mode == ia32_mode_E) {
		return ia32_type_E;
	} else {
		return get_type_for_mode(mode);
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	}
}

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ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
                                          ident *name)
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{
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	ir_entity        *res = pmap_get(ir_entity, isa->tv_ent, tv);
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	ir_initializer_t *initializer;
	ir_mode          *mode;
	ir_type          *tp;

	if (res != NULL)
		return res;

	mode = get_tarval_mode(tv);

	if (! ia32_cg_config.use_sse2) {
		/* try to reduce the mode to produce smaller sized entities */
		if (mode != mode_F) {
			if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
				mode = mode_F;
				tv = tarval_convert_to(tv, mode);
			} else if (mode != mode_D) {
				if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
					mode = mode_D;
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					tv = tarval_convert_to(tv, mode);
				}
			}
		}
	}

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	if (name == NULL)
		name = id_unique("C%u");

	tp  = ia32_get_prim_type(mode);
	res = new_entity(get_glob_type(), name, tp);
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	set_entity_ld_ident(res, get_entity_ident(res));
	set_entity_visibility(res, ir_visibility_private);
	add_entity_linkage(res, IR_LINKAGE_CONSTANT);

	initializer = create_initializer_tarval(tv);
	set_entity_initializer(res, initializer);

	pmap_insert(isa->tv_ent, tv, res);
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	return res;
}

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ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
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{
	ir_graph *irg         = current_ir_graph;
	ir_node  *start_block = get_irg_start_block(irg);
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	ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
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			symconst_sign, ia32_no_pic_adjust, val);
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	arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
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	return immediate;
}

const arch_register_t *ia32_get_clobber_register(const char *clobber)
{
	const arch_register_t       *reg = NULL;
	int                          c;
	size_t                       r;
	const arch_register_class_t *cls;

	/* TODO: construct a hashmap instead of doing linear search for clobber
	 * register */
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	for (c = 0; c < N_IA32_CLASSES; ++c) {
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		cls = & ia32_reg_classes[c];
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		for (r = 0; r < cls->n_regs; ++r) {
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			const arch_register_t *temp_reg = arch_register_for_index(cls, r);
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			if (strcmp(temp_reg->name, clobber) == 0
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					|| (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
				reg = temp_reg;
				break;
			}
		}
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		if (reg != NULL)
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			break;
	}

	return reg;
}

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int ia32_mode_needs_gp_reg(ir_mode *mode)
{
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	if (mode == ia32_mode_fpcw)
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		return 0;
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	if (get_mode_size_bits(mode) > 32)
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		return 0;
	return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
}

static void parse_asm_constraints(constraint_t *constraint, const char *c,
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                                  bool is_output)
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{
	char                         immediate_type     = '\0';
	unsigned                     limited            = 0;
	const arch_register_class_t *cls                = NULL;
	int                          memory_possible       = 0;
	int                          all_registers_allowed = 0;
	int                          p;
	int                          same_as = -1;

	memset(constraint, 0, sizeof(constraint[0]));
	constraint->same_as = -1;

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	if (*c == 0) {
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		/* a memory constraint: no need to do anything in backend about it
		 * (the dependencies are already respected by the memory edge of
		 * the node) */
		return;
	}

	/* TODO: improve error messages with node and source info. (As users can
	 * easily hit these) */
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	while (*c != 0) {
		switch (*c) {
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		case ' ':
		case '\t':
		case '\n':
			break;

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		/* Skip out/in-out marker */
		case '=': break;
		case '+': break;
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		case '&': break;

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		case '*':
			++c;
			break;
		case '#':
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			while (*c != 0 && *c != ',')
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				++c;
			break;

		case 'a':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_EAX;
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			break;
		case 'b':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_EBX;
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			break;
		case 'c':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_ECX;
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			break;
		case 'd':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_EDX;
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			break;
		case 'D':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_EDI;
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			break;
		case 'S':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_ESI;
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			break;
		case 'Q':
		case 'q':
			/* q means lower part of the regs only, this makes no
			 * difference to Q for us (we only assign whole registers) */
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
			           1 << REG_GP_EDX;
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			break;
		case 'A':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
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			break;
		case 'l':
			assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
			cls      = &ia32_reg_classes[CLASS_ia32_gp];
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			limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
			           1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
			           1 << REG_GP_EBP;
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			break;

		case 'R':
		case 'r':
		case 'p':
			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
				panic("multiple register classes not supported");
			cls                   = &ia32_reg_classes[CLASS_ia32_gp];
			all_registers_allowed = 1;
			break;

		case 'f':
		case 't':
		case 'u':
			/* TODO: mark values so the x87 simulator knows about t and u */
			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
				panic("multiple register classes not supported");
			cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
			all_registers_allowed = 1;
			break;

		case 'Y':
		case 'x':
			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
				panic("multiple register classes not supproted");
			cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
			all_registers_allowed = 1;
			break;

		case 'I':
		case 'J':
		case 'K':
		case 'L':
		case 'M':
		case 'N':
		case 'O':
			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
				panic("multiple register classes not supported");
			if (immediate_type != '\0')
				panic("multiple immediate types not supported");
			cls            = &ia32_reg_classes[CLASS_ia32_gp];
			immediate_type = *c;
			break;
		case 'n':
		case 'i':
			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
				panic("multiple register classes not supported");
			if (immediate_type != '\0')
				panic("multiple immediate types not supported");
			cls            = &ia32_reg_classes[CLASS_ia32_gp];
			immediate_type = 'i';
			break;

		case 'X':
		case 'g':
			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
				panic("multiple register classes not supported");
			if (immediate_type != '\0')
				panic("multiple immediate types not supported");
			immediate_type        = 'i';
			cls                   = &ia32_reg_classes[CLASS_ia32_gp];
			all_registers_allowed = 1;
			memory_possible       = 1;
			break;

		case '0':
		case '1':
		case '2':
		case '3':
		case '4':
		case '5':
		case '6':
		case '7':
		case '8':
		case '9':
			if (is_output)
				panic("can only specify same constraint on input");

			sscanf(c, "%d%n", &same_as, &p);
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			if (same_as >= 0) {
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				c += p;
				continue;
			}
			break;

		case 'm':
		case 'o':
		case 'V':
			/* memory constraint no need to do anything in backend about it
			 * (the dependencies are already respected by the memory edge of
			 * the node) */
			memory_possible = 1;
			break;

		case 'E': /* no float consts yet */
		case 'F': /* no float consts yet */
		case 's': /* makes no sense on x86 */
		case '<': /* no autodecrement on x86 */
		case '>': /* no autoincrement on x86 */
		case 'C': /* sse constant not supported yet */
		case 'G': /* 80387 constant not supported yet */
		case 'y': /* we don't support mmx registers yet */
		case 'Z': /* not available in 32 bit mode */
		case 'e': /* not available in 32 bit mode */
			panic("unsupported asm constraint '%c' found in (%+F)",
			      *c, current_ir_graph);
		default:
			panic("unknown asm constraint '%c' found in (%+F)", *c,
			      current_ir_graph);
		}
		++c;
	}

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	if (same_as >= 0) {
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		if (cls != NULL)
			panic("same as and register constraint not supported");
		if (immediate_type != '\0')
			panic("same as and immediate constraint not supported");
	}

	if (cls == NULL && same_as < 0) {
		if (!memory_possible)
			panic("no constraint specified for assembler input");
	}

	constraint->same_as               = same_as;
	constraint->cls                   = cls;
	constraint->allowed_registers     = limited;
	constraint->all_registers_allowed = all_registers_allowed;
	constraint->memory_possible       = memory_possible;
	constraint->immediate_type        = immediate_type;
}

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static bool can_match(const arch_register_req_t *in,
                      const arch_register_req_t *out)
{
	if (in->cls != out->cls)
		return false;
	if ( (in->type & arch_register_req_type_limited) == 0
		|| (out->type & arch_register_req_type_limited) == 0 )
		return true;

	return (*in->limited & *out->limited) != 0;
}

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static inline ir_node *get_new_node(ir_node *node)
{
#ifdef FIRM_GRGEN_BE
	if (be_transformer == TRANSFORMER_DEFAULT) {
		return be_transform_node(node);
	} else {
		return node;
	}
#else
	return be_transform_node(node);
#endif
}

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ir_node *ia32_gen_ASM(ir_node *node)
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{
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	ir_node        *block        = get_nodes_block(node);
	ir_node        *new_block    = get_new_node(block);
	dbg_info       *dbgi         = get_irn_dbg_info(node);
	int             n_inputs     = get_ASM_n_inputs(node);
	int             n_ins        = n_inputs+1;
	ir_node       **in           = ALLOCANZ(ir_node*, n_ins);
	size_t          n_clobbers   = 0;
	ident         **clobbers     = get_ASM_clobbers(node);
	unsigned        reg_map_size = 0;
	ir_graph       *irg          = get_irn_irg(node);
	struct obstack *obst         = get_irg_obstack(irg);
	unsigned        clobber_bits[N_IA32_CLASSES];
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	memset(&clobber_bits, 0, sizeof(clobber_bits));
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	for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
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		const char                *clobber = get_id_str(clobbers[c]);
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		const arch_register_req_t *req     = ia32_parse_clobber(clobber);
		if (req == NULL)
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			continue;
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		clobber_bits[req->cls->index] |= *req->limited;
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		assert(req->cls->n_regs <= sizeof(unsigned)*8);
		++n_clobbers;
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	}
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	size_t n_out_constraints = get_ASM_n_output_constraints(node);
	size_t out_arity         = n_out_constraints + n_clobbers;
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	const ir_asm_constraint *in_constraints  = get_ASM_input_constraints(node);
	const ir_asm_constraint *out_constraints = get_ASM_output_constraints(node);
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	/* determine size of register_map */
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	for (size_t out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
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		const ir_asm_constraint *constraint = &out_constraints[out_idx];
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		if (constraint->pos+1 > reg_map_size)
			reg_map_size = constraint->pos+1;
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	}
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	for (int i = 0; i < n_inputs; ++i) {
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		const ir_asm_constraint *constraint = &in_constraints[i];
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		if (constraint->pos+1 > reg_map_size)
			reg_map_size = constraint->pos+1;
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	}

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	ia32_asm_reg_t *register_map
		= NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
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	memset(register_map, 0, reg_map_size * sizeof(register_map[0]));

	/* construct output constraints */
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	size_t                      out_size = out_arity + 1;
	const arch_register_req_t **out_reg_reqs
		= OALLOCN(obst, const arch_register_req_t*, out_size);
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	size_t out_idx;
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	for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
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		constraint_t             parsed_constraint;
		const ir_asm_constraint *constraint = &out_constraints[out_idx];
		const char              *c          = get_id_str(constraint->constraint);
		unsigned                 pos        = constraint->pos;
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		parse_asm_constraints(&parsed_constraint, c, true);
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		const arch_register_req_t *req
			= ia32_make_register_req(&parsed_constraint, n_out_constraints,
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		                             out_reg_reqs, out_idx);
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		out_reg_reqs[out_idx] = req;

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		/* multiple constraints for same pos. This can happen for example when
		 * a =A constraint gets lowered to two constraints: =a and =d for the
		 * same pos */
		if (register_map[pos].valid)
			continue;

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		register_map[pos].use_input = 0;
		register_map[pos].valid     = 1;
		register_map[pos].memory    = 0;
		register_map[pos].inout_pos = out_idx;
		register_map[pos].mode      = constraint->mode;
	}

	/* inputs + input constraints */
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	const arch_register_req_t **in_reg_reqs
		= OALLOCN(obst, const arch_register_req_t*, n_ins);
	for (int i = 0; i < n_inputs; ++i) {
		constraint_t               parsed_constraint;
		ir_node                   *pred         = get_ASM_input(node, i);
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		const ir_asm_constraint   *constraint   = &in_constraints[i];
		ident                     *constr_id    = constraint->constraint;
		const char                *c            = get_id_str(constr_id);
		unsigned                   pos          = constraint->pos;
		int                        is_memory_op = 0;
		ir_node                   *input        = NULL;

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		parse_asm_constraints(&parsed_constraint, c, false);
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		if (parsed_constraint.cls != NULL) {
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			unsigned r_clobber_bits
				= clobber_bits[parsed_constraint.cls->index];
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			if (r_clobber_bits != 0) {
				if (parsed_constraint.all_registers_allowed) {
					parsed_constraint.all_registers_allowed = 0;
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					be_set_allocatable_regs(irg,
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							parsed_constraint.cls,
							&parsed_constraint.allowed_registers);
				}
				parsed_constraint.allowed_registers &= ~r_clobber_bits;
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			}
		}

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		const arch_register_req_t *req
			= ia32_make_register_req(&parsed_constraint, n_out_constraints,
		                             out_reg_reqs, i);
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		in_reg_reqs[i] = req;

		if (parsed_constraint.immediate_type != '\0') {
			char imm_type = parsed_constraint.immediate_type;
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			input = ia32_try_create_Immediate(pred, imm_type);
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		}

		if (input == NULL) {
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			input = get_new_node(pred);
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			if (parsed_constraint.cls == NULL
					&& parsed_constraint.same_as < 0) {
				is_memory_op = 1;
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				in_reg_reqs[i] = ia32_reg_classes[CLASS_ia32_gp].class_req;
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			} else if (parsed_constraint.memory_possible) {
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				/* TODO: match Load or Load/Store if memory possible is set */
			}
		}
		in[i] = input;

		register_map[pos].use_input = 1;
		register_map[pos].valid     = 1;
		register_map[pos].memory    = is_memory_op;
		register_map[pos].inout_pos = i;
		register_map[pos].mode      = constraint->mode;
	}

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	assert(n_inputs == n_ins-1);
	ir_node *mem = get_ASM_mem(node);
	in[n_inputs]          = be_transform_node(mem);
	in_reg_reqs[n_inputs] = arch_no_register_req;

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	/* parse clobbers */
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	for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
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		const char                *clobber = get_id_str(clobbers[c]);
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		const arch_register_req_t *req     = ia32_parse_clobber(clobber);
		if (req == NULL)
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			continue;
		out_reg_reqs[out_idx] = req;
		++out_idx;
	}

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	/* Attempt to make ASM node register pressure faithful.
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	 * (This does not work for complicated cases yet!)
	 *
	 * Algorithm: Check if there are fewer inputs or outputs (I will call this
	 * the smaller list). Then try to match each constraint of the smaller list
	 * to 1 of the other list. If we can't match it, then we have to add a dummy
	 * input/output to the other list
	 *
	 * FIXME: This is still broken in lots of cases. But at least better than
	 *        before...
	 * FIXME: need to do this per register class...
	 */
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	if (out_arity <= (size_t)n_inputs) {
		int       orig_inputs = n_ins;
		int       in_size     = n_ins;
		bitset_t *used_ins    = bitset_alloca(n_ins);
		for (size_t o = 0; o < out_arity; ++o) {
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			const arch_register_req_t *outreq = out_reg_reqs[o];

			if (outreq->cls == NULL) {
				continue;
			}

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			int i;
			for (i = 0; i < orig_inputs; ++i) {
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				if (bitset_is_set(used_ins, i))
					continue;
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				const arch_register_req_t *inreq = in_reg_reqs[i];
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				if (!can_match(outreq, inreq))
					continue;
				bitset_set(used_ins, i);
				break;
			}
			/* did we find any match? */
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			if (i < orig_inputs)
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				continue;

			/* we might need more space in the input arrays */
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			if (n_ins >= in_size) {
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				in_size *= 2;
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				const arch_register_req_t **new_in_reg_reqs
					= OALLOCN(obst, const arch_register_req_t*,
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				                          in_size);
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				memcpy(new_in_reg_reqs, in_reg_reqs,
				       n_ins*sizeof(new_in_reg_reqs[0]));
				ir_node **new_in = ALLOCANZ(ir_node*, in_size);
				memcpy(new_in, in, n_ins*sizeof(new_in[0]));
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				in_reg_reqs = new_in_reg_reqs;
				in          = new_in;
			}

			/* add a new (dummy) input which occupies the register */
			assert(outreq->type & arch_register_req_type_limited);
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			in_reg_reqs[n_ins] = outreq;
			in[n_ins]          = new_bd_ia32_ProduceVal(NULL, block);
			++n_ins;
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		}
	} else {
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		bitset_t *used_outs      = bitset_alloca(out_arity);
		size_t    orig_out_arity = out_arity;
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		for (int i = 0; i < n_inputs; ++i) {
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			const arch_register_req_t *inreq = in_reg_reqs[i];

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			if (inreq->cls == NULL)
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				continue;

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			size_t o;
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			for (o = 0; o < orig_out_arity; ++o) {
				const arch_register_req_t *outreq;
				if (bitset_is_set(used_outs, o))
					continue;
				outreq = out_reg_reqs[o];
				if (!can_match(outreq, inreq))
					continue;
				bitset_set(used_outs, i);
				break;
			}
			/* did we find any match? */
			if (o < orig_out_arity)
				continue;

			/* we might need more space in the output arrays */
			if (out_arity >= out_size) {
				const arch_register_req_t **new_out_reg_reqs;

				out_size *= 2;
				new_out_reg_reqs
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					= OALLOCN(obst, const arch_register_req_t*, out_size);
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				memcpy(new_out_reg_reqs, out_reg_reqs,
				       out_arity * sizeof(new_out_reg_reqs[0]));
				out_reg_reqs = new_out_reg_reqs;
			}

			/* add a new (dummy) output which occupies the register */
			assert(inreq->type & arch_register_req_type_limited);
			out_reg_reqs[out_arity] = inreq;
			++out_arity;
		}
	}

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	/* append none register requirement for the memory output */
	if (out_arity + 1 >= out_size) {
		const arch_register_req_t **new_out_reg_reqs;

		out_size = out_arity + 1;
		new_out_reg_reqs
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			= OALLOCN(obst, const arch_register_req_t*, out_size);
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		memcpy(new_out_reg_reqs, out_reg_reqs,
			   out_arity * sizeof(new_out_reg_reqs[0]));
		out_reg_reqs = new_out_reg_reqs;
	}

	/* add a new (dummy) output which occupies the register */
	out_reg_reqs[out_arity] = arch_no_register_req;
	++out_arity;

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	ir_node *new_node = new_bd_ia32_Asm(dbgi, new_block, n_ins, in, out_arity,
	                                    get_ASM_text(node), register_map);
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	backend_info_t *info = be_get_info(new_node);
	for (size_t o = 0; o < out_arity; ++o) {
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		info->out_infos[o].req = out_reg_reqs[o];
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	}
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	arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
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	SET_IA32_ORIG_NODE(new_node, node);
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	return new_node;
}

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ir_node *ia32_gen_CopyB(ir_node *node)
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{
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	ir_node  *block    = get_new_node(get_nodes_block(node));
	ir_node  *src      = get_CopyB_src(node);
	ir_node  *new_src  = get_new_node(src);
	ir_node  *dst      = get_CopyB_dst(node);
	ir_node  *new_dst  = get_new_node(dst);
	ir_node  *mem      = get_CopyB_mem(node);
	ir_node  *new_mem  = get_new_node(mem);
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	ir_node  *res      = NULL;
	dbg_info *dbgi     = get_irn_dbg_info(node);
	int      size      = get_type_size_bytes(get_CopyB_type(node));
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	int      throws_exception = ir_throws_exception(node);
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	int      rem;

	/* If we have to copy more than 32 bytes, we use REP MOVSx and */
	/* then we need the size explicitly in ECX.                    */
	if (size >= 32 * 4) {
		rem = size & 0x3; /* size % 4 */
		size >>= 2;

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		res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
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		res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
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	} else {
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		if (size == 0) {
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			ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
			           node);
		}
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		res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
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	}
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	ir_set_throws_exception(res, throws_exception);
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	SET_IA32_ORIG_NODE(res, node);
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	return res;
}

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ir_node *ia32_gen_Proj_tls(ir_node *node)
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{
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	ir_node *block = get_new_node(get_nodes_block(node));
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	ir_node *res   = new_bd_ia32_LdTls(NULL, block);
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	return res;
}

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ir_node *ia32_gen_Unknown(ir_node *node)
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{
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	ir_mode  *mode  = get_irn_mode(node);
	ir_graph *irg   = current_ir_graph;
	dbg_info *dbgi  = get_irn_dbg_info(node);
	ir_node  *block = get_irg_start_block(irg);
	ir_node  *res   = NULL;
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	if (mode_is_float(mode)) {
		if (ia32_cg_config.use_sse2) {
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			res = new_bd_ia32_xUnknown(dbgi, block);
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		} else {
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			res = new_bd_ia32_vfldz(dbgi, block);
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		}
	} else if (ia32_mode_needs_gp_reg(mode)) {
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		res = new_bd_ia32_Unknown(dbgi, block);
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	} else {
		panic("unsupported Unknown-Mode");
	}
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	return res;
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}

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const arch_register_req_t *ia32_make_register_req(
		const constraint_t *constraint,  int n_outs,
		const arch_register_req_t **out_reqs, int pos)
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{
	struct obstack      *obst    = get_irg_obstack(current_ir_graph);
	int                  same_as = constraint->same_as;
	arch_register_req_t *req;

	if (same_as >= 0) {
		const arch_register_req_t *other_constr;

		if (same_as >= n_outs)
			panic("invalid output number in same_as constraint");

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		other_constr     = out_reqs[same_as];

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		req              = OALLOC(obst, arch_register_req_t);
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		*req             = *other_constr;
		req->type       |= arch_register_req_type_should_be_same;
		req->other_same  = 1U << pos;
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		req->width       = 1;
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		/* switch constraints. This is because in firm we have same_as
		 * constraints on the output constraints while in the gcc asm syntax
		 * they are specified on the input constraints */
		out_reqs[same_as] = req;
		return other_constr;
	}

	/* pure memory ops */
	if (constraint->cls == NULL) {
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		return arch_no_register_req;
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	}

	if (constraint->allowed_registers != 0
			&& !constraint->all_registers_allowed) {
		unsigned *limited_ptr;

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		req         = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
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		memset(req, 0, sizeof(req[0]));
		limited_ptr = (unsigned*) (req+1);

		req->type    = arch_register_req_type_limited;
		*limited_ptr = constraint->allowed_registers;
		req->limited = limited_ptr;
	} else {
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		req       = OALLOCZ(obst, arch_register_req_t);
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		req->type = arch_register_req_type_normal;
	}
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	req->cls   = constraint->cls;
	req->width = 1;
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	return req;
}

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const arch_register_req_t *ia32_parse_clobber(const char *clobber)
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{
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	if (strcmp(clobber, "memory") == 0 || strcmp(clobber, "cc") == 0)
		return NULL;

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	struct obstack        *obst = get_irg_obstack(current_ir_graph);
	const arch_register_t *reg  = ia32_get_clobber_register(clobber);
	arch_register_req_t   *req;
	unsigned              *limited;

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	if (reg == NULL) {
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		panic("Register '%s' mentioned in asm clobber is unknown", clobber);
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	}

	assert(reg->index < 32);

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	limited  = OALLOC(obst, unsigned);
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	*limited = 1 << reg->index;

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	req          = OALLOCZ(obst, arch_register_req_t);
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	req->type    = arch_register_req_type_limited;
	req->cls     = arch_register_get_class(reg);
	req->limited = limited;
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	req->width   = 1;
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	return req;
}

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int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
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                       ir_node *const other)
{
	if (get_nodes_block(other) != block)
		return 0;

	if (is_Sync(other)) {
		int i;

		for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
			ir_node *const pred = get_Sync_pred(other, i);

			if (get_nodes_block(pred) != block)
				continue;

			/* Do not block ourselves from getting eaten */
			if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
				continue;

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			if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
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				continue;

			return 1;
		}

		return 0;
	} else {
		/* Do not block ourselves from getting eaten */
		if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
			return 0;

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		if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
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			return 0;

		return 1;
	}
}

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ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
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{
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	long       val = 0;
	ir_entity *symconst_ent  = NULL;
	ir_mode   *mode;
	ir_node   *cnst          = NULL;
	ir_node   *symconst      = NULL;
	ir_node   *new_node;
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	mode = get_irn_mode(node);
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	if (!mode_is_int(mode) && !mode_is_reference(mode)) {
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		return NULL;
	}

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	if (is_Const(node)) {
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		cnst     = node;
		symconst = NULL;
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	} else if (is_SymConst_addr_ent(node)
			&& get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
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		cnst     = NULL;
		symconst = node;
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	} else if (is_Add(node)) {
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		ir_node *left  = get_Add_left(node);
		ir_node *right = get_Add_right(node);
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		if (is_Const(left) && is_SymConst_addr_ent(right)) {
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			cnst     = left;
			symconst = right;
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		} else if (is_SymConst_addr_ent(left) && is_Const(right)) {
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			cnst     = right;
			symconst = left;
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		}
	} else {
		return NULL;
	}

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	if (cnst != NULL) {
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		ir_tarval *offset = get_Const_tarval(cnst);
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		if (!tarval_is_long(offset)) {
			ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
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			return NULL;
		}

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		val = get_tarval_long(offset);
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		if (!check_immediate_constraint(val, immediate_constraint_type))
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			return NULL;
	}
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	if (symconst != NULL) {
		if (immediate_constraint_type != 0) {
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			/* we need full 32bits for symconsts */
			return NULL;
		}

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		symconst_ent = get_SymConst_entity(symconst);
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	}
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	if (cnst == NULL && symconst == NULL)
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		return NULL;

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	new_node = ia32_create_Immediate(symconst_ent, 0, val);
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	return new_node;
}