amd64_bearch.c 26 KB
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/*
 * This file is part of libFirm.
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 * Copyright (C) 2012 University of Karlsruhe.
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 */

/**
 * @file
 * @brief    The main amd64 backend driver file.
 */
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#include "amd64_bearch_t.h"
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#include "amd64_emitter.h"
#include "amd64_finish.h"
#include "amd64_new_nodes.h"
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#include "amd64_optimize.h"
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#include "amd64_transform.h"
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#include "amd64_varargs.h"
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#include "beflags.h"
#include "beirg.h"
#include "bemodule.h"
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#include "bera.h"
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#include "besched.h"
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#include "bespillslots.h"
#include "bestack.h"
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#include "beutil.h"
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#include "debug.h"
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#include "gen_amd64_regalloc_if.h"
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#include "irarch_t.h"
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#include "ircons.h"
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#include "iredges_t.h"
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#include "irgmod.h"
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#include "irgopt.h"
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#include "irgwalk.h"
#include "iropt_t.h"
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#include "irtools.h"
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#include "lower_alloc.h"
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#include "lower_builtins.h"
#include "lower_calls.h"
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#include "lower_mode_b.h"
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#include "lowering.h"
#include "panic.h"
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DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

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pmap *amd64_constants;

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ir_mode *amd64_mode_xmm;
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static int get_insn_size_bytes(amd64_insn_size_t size)
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{
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	switch (size) {
	case INSN_SIZE_8:       return 1;
	case INSN_SIZE_16:      return 2;
	case INSN_SIZE_32:      return 4;
	case INSN_SIZE_64:      return 8;
	case INSN_SIZE_128:     return 16;
	case INSN_SIZE_80:      break;
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	}
	panic("bad insn mode");
}

static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp,
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                            ir_node *mem, ir_entity *ent,
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                            amd64_insn_size_t size)
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{
	dbg_info *dbgi  = get_irn_dbg_info(node);
	ir_node  *block = get_nodes_block(node);
	ir_graph *irg   = get_irn_irg(node);
	ir_node  *frame = get_irg_frame(irg);

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	x86_addr_t addr = {
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		.immediate = {
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			.kind   = X86_IMM_FRAMEENT,
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			.entity = ent,
		},
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		.variant    = X86_ADDR_BASE,
		.base_input = 1,
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	};
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	ir_node *in[] = { sp, frame, mem };
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	ir_node *const push = new_bd_amd64_push_am(dbgi, block, ARRAY_SIZE(in), in, rsp_reg_mem_reqs, size, addr);
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	sched_add_before(schedpoint, push);
	return push;
}

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static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp,
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                           ir_entity *ent, amd64_insn_size_t size)
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{
	dbg_info *dbgi  = get_irn_dbg_info(node);
	ir_node  *block = get_nodes_block(node);
	ir_graph *irg   = get_irn_irg(node);
	ir_node  *frame = get_irg_frame(irg);

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	x86_addr_t addr = {
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		.immediate = {
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			.kind   = X86_IMM_FRAMEENT,
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			.entity = ent,
		},
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		.variant     = X86_ADDR_BASE,
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		.base_input  = 1,
	};
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	ir_node *in[] = { sp, frame, get_irg_no_mem(irg) };

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	ir_node *const pop = new_bd_amd64_pop_am(dbgi, block, ARRAY_SIZE(in), in, rsp_reg_mem_reqs, size, addr);
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	sched_add_before(schedpoint, pop);

	return pop;
}

static ir_node* create_spproj(ir_node *pred, int pos)
{
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	return be_new_Proj_reg(pred, pos, &amd64_registers[REG_RSP]);
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}

/**
 * Transform MemPerm, currently we do this the ugly way and produce
 * push/pop into/from memory cascades. This is possible without using
 * any registers.
 */
static void transform_MemPerm(ir_node *node)
{
	ir_graph *irg   = get_irn_irg(node);
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	ir_node  *sp    = be_get_Start_proj(irg, &amd64_registers[REG_RSP]);
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	int       arity = be_get_MemPerm_entity_arity(node);
	ir_node **pops  = ALLOCAN(ir_node*, arity);

	/* create Pushs */
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	for (int i = 0; i < arity; ++i) {
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		ir_entity *inent = be_get_MemPerm_in_entity(node, i);
		ir_entity *outent = be_get_MemPerm_out_entity(node, i);
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		assert(inent->kind == IR_ENTITY_SPILLSLOT);
		assert(outent->kind == IR_ENTITY_SPILLSLOT);
		unsigned entsize = inent->attr.spillslot.size;
		unsigned entsize2 = outent->attr.spillslot.size;
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		ir_node *mem = get_irn_n(node, i);
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		/* work around cases where entities have different sizes */
		if (entsize2 < entsize)
			entsize = entsize2;

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		int offset = 0;
		do {
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			amd64_insn_size_t size;
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			if (entsize%2 == 1) {
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				size = INSN_SIZE_8;
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			} else if (entsize % 4 == 2) {
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				size = INSN_SIZE_16;
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			} else if (entsize % 8 == 4) {
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				size = INSN_SIZE_32;
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			} else {
				assert(entsize%8 == 0);
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				size = INSN_SIZE_64;
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			}

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			ir_node *push = create_push(node, node, sp, mem, inent, size);
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			sp = create_spproj(push, pn_amd64_push_am_stack);
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			get_amd64_addr_attr(push)->addr.immediate.offset = offset;

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			unsigned bytes = get_insn_size_bytes(size);
			offset  += bytes;
			entsize -= bytes;
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		} while(entsize > 0);
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		set_irn_n(node, i, new_r_Bad(irg, mode_X));
	}

	/* create pops */
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	for (int i = arity; i-- > 0; ) {
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		ir_entity *inent = be_get_MemPerm_in_entity(node, i);
		ir_entity *outent = be_get_MemPerm_out_entity(node, i);
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		assert(inent->kind == IR_ENTITY_SPILLSLOT);
		assert(outent->kind == IR_ENTITY_SPILLSLOT);
		unsigned entsize = outent->attr.spillslot.size;
		unsigned entsize2 = inent->attr.spillslot.size;
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		/* work around cases where entities have different sizes */
		if (entsize2 < entsize)
			entsize = entsize2;

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		int      offset = entsize;
		ir_node *pop;
		do {
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			amd64_insn_size_t size;
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			if (entsize%2 == 1) {
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				size = INSN_SIZE_8;
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			} else if (entsize % 4 == 2) {
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				size = INSN_SIZE_16;
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			} else if (entsize % 8 == 4) {
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				size = INSN_SIZE_32;
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			} else {
				assert(entsize%8 == 0);
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				size = INSN_SIZE_64;
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			}

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			pop = create_pop(node, node, sp, outent, size);
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			sp  = create_spproj(pop, pn_amd64_pop_am_stack);
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			unsigned bytes = get_insn_size_bytes(size);
			offset  -= bytes;
			entsize -= bytes;
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			get_amd64_addr_attr(pop)->addr.immediate.offset = offset;
		} while(entsize > 0);
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		pops[i] = pop;
	}

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	ir_node *const keep = be_new_Keep_one(sp);
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	sched_replace(node, keep);

	/* exchange memprojs */
	foreach_out_edge_safe(node, edge) {
		ir_node *proj = get_edge_src_irn(edge);
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		int p = get_Proj_num(proj);
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		assert(p < arity);

		set_Proj_pred(proj, pops[p]);
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		set_Proj_num(proj, pn_amd64_pop_am_M);
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	}

	/* remove memperm */
	kill_node(node);
}

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static void amd64_after_ra_walker(ir_node *block, void *data)
{
	(void) data;

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	sched_foreach_reverse_safe(block, node) {
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		if (be_is_MemPerm(node)) {
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			transform_MemPerm(node);
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		}
	}
}

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/**
 * rewrite unsigned long -> float/double conversion
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 * x86_64 only has a signed conversion so we do some crazy sse construction
 * instead (first seen this pattern in llvm): We split the 64bit value into
 * 2 32bit vals and place them into the mantissa parts of apropriately choosen
 * float values and later add the 2 floats together. In pseudo code:
 *
 * a = (vector unsigned long, unsigned long) x;
 * b = (vector unsigned, unsigned, unsigned, unsigned)
 *       upper half of 0x1p+52, upper half of 0x1p+84, 0, 0
 * c = repack (a[0], b[0], a[1], b[1])
 * d = (vector double) 0x1p+52, 0x1p+84
 * e = c - d
 * f = e[0] + e[1]
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 */
static void rewrite_unsigned_float_Conv(ir_node *node)
{
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	ir_graph  *irg    = get_irn_irg(node);
	dbg_info  *dbgi   = get_irn_dbg_info(node);
	ir_node   *block  = get_nodes_block(node);
	ir_node   *in     = get_Conv_op(node);
	ir_node   *in_xmm = new_r_Conv(block, in, amd64_mode_xmm);
	ir_tarval *magic0
		= new_integer_tarval_from_str("4530000043300000", 16, 0, 16,
		                              amd64_mode_xmm);
	ir_node   *const0 = new_r_Const(irg, magic0);
	collect_new_start_block_node(const0);
	ir_node   *punpck = new_bd_amd64_l_punpckldq(dbgi, block, in_xmm, const0);
	ir_tarval *magic1
		= new_integer_tarval_from_str("45300000000000004330000000000000", 32,
		                              0, 16, amd64_mode_xmm);
	ir_node   *const1 = new_r_Const(irg, magic1);
	collect_new_start_block_node(const1);
	ir_node   *subpd  = new_bd_amd64_l_subpd(dbgi, block, punpck, const1);
	ir_node   *haddpd = new_bd_amd64_l_haddpd(dbgi, block, subpd, subpd);
	ir_mode   *mode   = get_irn_mode(node);
	ir_node   *conv   = new_r_Conv(block, haddpd, mode);
	exchange(node, conv);
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}

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/* Creates a 64-bit constant with only the sign bit set,
 * i.e. returns 0x8000000000000000
 */
static ir_node *create_sign_bit_const(ir_graph *irg)
{
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	ir_tarval *sign_tv = create_sign_tv(mode_Ls);
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	return new_r_Const(irg, sign_tv);
}

/* rewrite float/double -> unsigned long conversion
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 * x86_64 only has a signed conversion so we rewrite to the following:
 *
 * if (x >= 9223372036854775808.) {
 *   converted ^= (int)(x-9223372036854775808.) ^ 0x8000000000000000;
 * } else {
 *   converted = (int)x;
 * }
 * return (unsigned)converted;
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 */
static void rewrite_float_unsigned_Conv(ir_node *node)
{
	ir_graph *irg        = get_irn_irg(node);
	dbg_info *dbgi       = get_irn_dbg_info(node);
	ir_node *lower_block = get_nodes_block(node);
	ir_mode *dest_mode   = get_irn_mode(node);

	part_block(node);

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	ir_node   *block    = get_nodes_block(node);
	ir_node   *fp_x     = get_Conv_op(node);
	ir_mode   *src_mode = get_irn_mode(fp_x);
	double     d_const  = 9223372036854775808.;
	ir_tarval *tv       = new_tarval_from_double(d_const, src_mode);
	ir_node   *fp_const = new_r_Const(irg, tv);
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	collect_new_start_block_node(fp_const);
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	/* Test if the sign bit is needed */
	ir_node *cmp         = new_rd_Cmp(dbgi, block, fp_x, fp_const,
	                                 ir_relation_greater_equal);
	ir_node *cond        = new_rd_Cond(dbgi, block, cmp);
	ir_node *proj_true   = new_r_Proj(cond, mode_X, pn_Cond_true);
	ir_node *proj_false  = new_r_Proj(cond, mode_X, pn_Cond_false);
	ir_node *in_true[1]  = { proj_true };
	ir_node *in_false[1] = { proj_false };

	/* true block: Do some arithmetic to use the signed conversion */
	ir_node *true_block  = new_r_Block(irg, ARRAY_SIZE(in_true), in_true);
	ir_node *true_jmp    = new_r_Jmp(true_block);
	ir_node *sub         = new_r_Sub(true_block, fp_const, fp_x, src_mode);
	ir_node *sub_conv    = new_rd_Conv(dbgi, true_block, sub, mode_Ls);
	ir_node *sign_bit    = create_sign_bit_const(irg);
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	collect_new_start_block_node(sign_bit);
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	ir_node *xor         = new_r_Eor(true_block, sub_conv, sign_bit, mode_Ls);
	ir_node *true_res    = new_rd_Conv(dbgi, true_block, xor, dest_mode);

	/* false block: Simply convert */
	ir_node *false_block  = new_r_Block(irg, ARRAY_SIZE(in_false), in_false);
	ir_node *false_jmp    = new_r_Jmp(false_block);
	ir_node *false_signed = new_rd_Conv(dbgi, false_block, fp_x, mode_Ls);
	ir_node *false_res    = new_rd_Conv(dbgi, false_block, false_signed,
	                                    dest_mode);

	/* lower block */
	ir_node *lower_in[2] = { true_jmp, false_jmp };
	ir_node *phi_in[2]   = { true_res, false_res };

	set_irn_in(lower_block, ARRAY_SIZE(lower_in), lower_in);
	ir_node *phi = new_r_Phi(lower_block, ARRAY_SIZE(phi_in), phi_in,
	                         dest_mode);
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	collect_new_phi_node(phi);
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	exchange(node, phi);
}

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static bool amd64_rewrite_Conv(ir_node *node)
{
	ir_mode *to_mode    = get_irn_mode(node);
	ir_node *op         = get_Conv_op(node);
	ir_mode *from_mode  = get_irn_mode(op);
	bool     to_float   = mode_is_float(to_mode);
	bool     from_float = mode_is_float(from_mode);

	if (to_float && !from_float && !mode_is_signed(from_mode)
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	    && get_mode_size_bits(from_mode) == 64
	    && to_mode != x86_mode_E) {
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		rewrite_unsigned_float_Conv(node);
		return true;
	} else if (from_float && !to_float && !mode_is_signed(to_mode)
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	           && get_mode_size_bits(to_mode) == 64
	           && from_mode != x86_mode_E) {
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		rewrite_float_unsigned_Conv(node);
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		return true;
	}

	return false;
}

static void amd64_intrinsics_walker(ir_node *node, void *data)
{
	bool *changed = (bool*)data;
	if (is_Conv(node)) {
		if (amd64_rewrite_Conv(node))
			*changed = true;
	}
}

static void amd64_handle_intrinsics(ir_graph *irg)
{
	ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK | IR_RESOURCE_PHI_LIST);
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	collect_phiprojs_and_start_block_nodes(irg);
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	bool changed = false;
	irg_walk_graph(irg, amd64_intrinsics_walker, NULL, &changed);
	ir_free_resources(irg, IR_RESOURCE_IRN_LINK | IR_RESOURCE_PHI_LIST);

	if (changed) {
		confirm_irg_properties(irg,
		        IR_GRAPH_PROPERTY_NO_BADS
		        | IR_GRAPH_PROPERTY_NO_CRITICAL_EDGES
		        | IR_GRAPH_PROPERTY_MANY_RETURNS
		        | IR_GRAPH_PROPERTY_ONE_RETURN);
	}
}

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static void amd64_set_frame_entity(ir_node *node, ir_entity *entity,
                                   const ir_type *type)
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{
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	(void)type;
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	amd64_addr_attr_t *attr = get_amd64_addr_attr(node);
	attr->addr.immediate.entity = entity;
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}

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static ir_type *get_type_for_insn_size(amd64_insn_size_t const size)
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{
	/* TODO: do not hardcode node names here */
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	switch (size) {
	case INSN_SIZE_128: return get_type_for_mode(amd64_mode_xmm);
	case INSN_SIZE_80:  return x86_type_E;
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	default:            return get_type_for_mode(mode_Lu);
	}
}

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/**
 * Collects nodes that need frame entities assigned.
 */
static void amd64_collect_frame_entity_nodes(ir_node *node, void *data)
{
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	if (!is_amd64_irn(node))
		return;
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	/* Disable coalescing for "returns twice" calls: In case of setjmp/longjmp
	 * our control flow graph isn't completely correct: There are no backedges
	 * from longjmp to the setjmp => coalescing would produce wrong results. */
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	be_fec_env_t *const env = (be_fec_env_t*)data;
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	if (is_amd64_call(node)) {
		const amd64_call_addr_attr_t    *attrs = get_amd64_call_addr_attr_const(node);
		const ir_type                   *type  = attrs->call_tp;
		const mtp_additional_properties  mtp
			= get_method_additional_properties(type);
		if (mtp & mtp_property_returns_twice)
			be_forbid_coalescing(env);
	}

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	/* we are only interested to report Load nodes */
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	if (!amd64_loads(node))
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		return;

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	const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node);
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	x86_imm32_t       const *imm  = &attr->addr.immediate;
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	if (imm->kind == X86_IMM_FRAMEENT && imm->entity == NULL) {
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		const ir_type *type = get_type_for_insn_size(attr->base.size);
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		be_load_needs_frame_entity(env, node, type);
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	}
}

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static int determine_rbp_input(ir_node *ret)
{
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	arch_register_t const *const bp = &amd64_registers[REG_RBP];
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	foreach_irn_in(ret, i, input) {
		if (arch_get_irn_register(input) == bp)
			return i;
	}
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	panic("no rbp input found at %+F", ret);
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}

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/**
 * prepare graph and perform code selection.
 */
static void amd64_select_instructions(ir_graph *irg)
{
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	amd64_adjust_pic(irg);

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	be_timer_push(T_CODEGEN);
	amd64_transform_graph(irg);
	be_timer_pop(T_CODEGEN);

	be_dump(DUMP_BE, irg, "code-selection");
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	optimize_graph_df(irg);

	be_dump(DUMP_BE, irg, "opt");
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}

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static void introduce_epilogue(ir_node *ret, bool omit_fp)
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{
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	ir_graph *irg      = get_irn_irg(ret);
	ir_node  *block    = get_nodes_block(ret);
	ir_node  *first_sp = get_irn_n(ret, n_amd64_ret_stack);
	ir_node  *curr_sp  = first_sp;
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	if (!omit_fp) {
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		int      const n_rbp    = determine_rbp_input(ret);
		ir_node       *curr_bp  = get_irn_n(ret, n_rbp);
		ir_node       *curr_mem = get_irn_n(ret, n_amd64_ret_mem);
		ir_node *const leave    = new_bd_amd64_leave(NULL, block, curr_bp, curr_mem);
		curr_mem = be_new_Proj(leave, pn_amd64_leave_M);
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		curr_bp = be_new_Proj_reg(leave, pn_amd64_leave_frame, &amd64_registers[REG_RBP]);
		curr_sp = be_new_Proj_reg(leave, pn_amd64_leave_stack, &amd64_registers[REG_RSP]);
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		sched_add_before(ret, leave);

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		set_irn_n(ret, n_amd64_ret_mem, curr_mem);
		set_irn_n(ret, n_rbp,           curr_bp);
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	} else {
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		ir_type *frame_type = get_irg_frame_type(irg);
		unsigned frame_size = get_type_size(frame_type);
		ir_node *incsp = amd64_new_IncSP(block, curr_sp, -(int)frame_size,
										 true);
		sched_add_before(ret, incsp);
		curr_sp = incsp;
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	}
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	set_irn_n(ret, n_amd64_ret_stack, curr_sp);
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	/* keep verifier happy... */
	if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
		kill_node(first_sp);
	}
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}

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static void introduce_prologue(ir_graph *const irg, bool omit_fp)
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{
	const arch_register_t *sp         = &amd64_registers[REG_RSP];
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	const arch_register_t *bp         = &amd64_registers[REG_RBP];
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	ir_node               *start      = get_irg_start(irg);
	ir_node               *block      = get_nodes_block(start);
	ir_type               *frame_type = get_irg_frame_type(irg);
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	unsigned               frame_size = get_type_size(frame_type);
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	ir_node               *initial_sp = be_get_Start_proj(irg, sp);
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	if (!omit_fp) {
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		/* push rbp */
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		ir_node *const mem        = get_irg_initial_mem(irg);
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		ir_node *const initial_bp = be_get_Start_proj(irg, bp);
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		ir_node *const push       = new_bd_amd64_push_reg(NULL, block, initial_sp, mem, initial_bp, INSN_SIZE_64);
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		sched_add_after(start, push);
		ir_node *const curr_mem   = be_new_Proj(push, pn_amd64_push_reg_M);
		edges_reroute_except(mem, curr_mem, push);
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		ir_node *const curr_sp    = be_new_Proj_reg(push, pn_amd64_push_reg_stack, sp);
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		/* move rsp to rbp */
		ir_node *const curr_bp = be_new_Copy(block, curr_sp);
		sched_add_after(push, curr_bp);
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		arch_copy_irn_out_info(curr_bp, 0, initial_bp);
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		edges_reroute_except(initial_bp, curr_bp, push);
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		ir_node *incsp = amd64_new_IncSP(block, curr_sp, frame_size, false);
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		sched_add_after(curr_bp, incsp);
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		edges_reroute_except(initial_sp, incsp, push);
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		/* make sure the initial IncSP is really used by someone */
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		be_keep_if_unused(incsp);
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	} else {
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		ir_node *const incsp = amd64_new_IncSP(block, initial_sp,
											   frame_size, false);
		sched_add_after(start, incsp);
		edges_reroute_except(initial_sp, incsp, incsp);
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	}
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}
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static void introduce_prologue_epilogue(ir_graph *irg, bool omit_fp)
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{
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	/* introduce epilogue for every return node */
	foreach_irn_in(get_irg_end_block(irg), i, ret) {
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		assert(is_amd64_ret(ret));
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		introduce_epilogue(ret, omit_fp);
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	}
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	introduce_prologue(irg, omit_fp);
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}

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static bool node_has_sp_base(ir_node const *const node,
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                             x86_addr_t const *const addr)
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{
	if (!x86_addr_variant_has_base(addr->variant))
		return false;
	arch_register_t const *const base_reg
		= arch_get_irn_register_in(node, addr->base_input);
	return base_reg == &amd64_registers[REG_RSP];
}

static void amd64_determine_frameoffset(ir_node *node, int sp_offset)
{
	if (!is_amd64_irn(node)
	 || !amd64_has_addr_attr(get_amd64_attr_const(node)->op_mode))
		return;

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	x86_addr_t *const addr = &get_amd64_addr_attr(node)->addr;
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	if (addr->immediate.kind == X86_IMM_FRAMEENT) {
		addr->immediate.offset += get_entity_offset(addr->immediate.entity);
		addr->immediate.entity  = NULL;
		addr->immediate.kind    = X86_IMM_FRAMEOFFSET;
	}

	if (addr->immediate.kind == X86_IMM_FRAMEOFFSET) {
		if (node_has_sp_base(node, addr))
			addr->immediate.offset += sp_offset;
		else {
			/* we calculate offsets relative to the SP value at function begin,
			 * but RBP points after the saved old frame pointer */
			addr->immediate.offset += AMD64_REGISTER_SIZE;
		}
		addr->immediate.kind = X86_IMM_VALUE;
	}
}

static void amd64_sp_sim(ir_node *const node, stack_pointer_state_t *state)
{
	/* Pop nodes modify the stack pointer before calculating destination
	 * address, so do this first */
	if (is_amd64_pop_am(node)) {
		const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node);
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		state->offset -= get_insn_size_bytes(attr->base.size);
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	}

	amd64_determine_frameoffset(node, state->offset);

	if (is_amd64_push_am(node)) {
		const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node);
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		state->offset       += get_insn_size_bytes(attr->base.size);
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	} else if (is_amd64_push_reg(node)) {
		/* 64-bit register size */
		state->offset       += AMD64_REGISTER_SIZE;
	} else if (is_amd64_leave(node)) {
		state->offset        = 0;
		state->align_padding = 0;
	} else if (is_amd64_sub_sp(node)) {
		state->align_padding = 0;
	}
}

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/**
 * Called immediatly before emit phase.
 */
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static void amd64_finish_and_emit(ir_graph *irg)
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{
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	bool omit_fp = amd64_get_irg_data(irg)->omit_fp;
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	/* create and coalesce frame entities */
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	be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
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	irg_walk_graph(irg, NULL, amd64_collect_frame_entity_nodes, fec_env);
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	be_assign_entities(fec_env, amd64_set_frame_entity, omit_fp);
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	be_free_frame_entity_coalescer(fec_env);
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	ir_type *const frame = get_irg_frame_type(irg);
	be_sort_frame_entities(frame, omit_fp);
	unsigned const misalign = AMD64_REGISTER_SIZE; /* return address on stack */
	int      const begin    = omit_fp ? 0 : -AMD64_REGISTER_SIZE;
	be_layout_frame_type(frame, begin, misalign);

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	irg_block_walk_graph(irg, NULL, amd64_after_ra_walker, NULL);
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	introduce_prologue_epilogue(irg, omit_fp);
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	/* fix stack entity offsets */
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	be_fix_stack_nodes(irg, &amd64_registers[REG_RSP]);
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	be_birg_from_irg(irg)->non_ssa_regs = NULL;
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	unsigned const p2align = AMD64_PO2_STACK_ALIGNMENT;
	be_sim_stack_pointer(irg, misalign, p2align, amd64_sp_sim);
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	/* Fix 2-address code constraints. */
	amd64_finish_irg(irg);
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	amd64_simulate_graph_x87(irg);

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	amd64_peephole_optimization(irg);

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	/* emit code */
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	be_timer_push(T_EMIT);
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	amd64_emit_function(irg);
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	be_timer_pop(T_EMIT);
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}
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static void amd64_finish(void)
{
	amd64_free_opcodes();
}

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static const regalloc_if_t amd64_regalloc_if = {
	.spill_cost  = 7,
	.reload_cost = 5,
	.new_spill   = amd64_new_spill,
	.new_reload  = amd64_new_reload,
};

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static void amd64_generate_code(FILE *output, const char *cup_name)
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{
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	amd64_constants = pmap_create();
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	be_begin(output, cup_name);
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	unsigned *const sp_is_non_ssa = rbitset_alloca(N_AMD64_REGISTERS);
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	rbitset_set(sp_is_non_ssa, REG_RSP);
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	foreach_irp_irg(i, irg) {
		if (!be_step_first(irg))
			continue;
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		struct obstack *obst = be_get_be_obst(irg);
		be_birg_from_irg(irg)->isa_link = OALLOCZ(obst, amd64_irg_data_t);

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		be_birg_from_irg(irg)->non_ssa_regs = sp_is_non_ssa;
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		amd64_select_instructions(irg);
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		be_step_schedule(irg);

		be_timer_push(T_RA_PREPARATION);
		be_sched_fix_flags(irg, &amd64_reg_classes[CLASS_amd64_flags], NULL,
						   NULL, NULL);
		be_timer_pop(T_RA_PREPARATION);

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		be_step_regalloc(irg, &amd64_regalloc_if);
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		amd64_finish_and_emit(irg);

		be_step_last(irg);
	}

	be_finish();
	pmap_destroy(amd64_constants);
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}

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static void amd64_lower_for_target(void)
{
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	/* lower compound param handling */
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	lower_calls_with_compounds(LF_RETURN_HIDDEN, NULL);
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	be_after_irp_transform("lower-calls");
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	foreach_irp_irg(i, irg) {
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		lower_switch(irg, 4, 256, mode_Iu);
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		be_after_transform(irg, "lower-switch");
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	}

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	foreach_irp_irg(i, irg) {
		/* lower for mode_b stuff */
		ir_lower_mode_b(irg, mode_Lu);
		be_after_transform(irg, "lower-modeb");
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		lower_alloc(irg, AMD64_PO2_STACK_ALIGNMENT);
		be_after_transform(irg, "lower-alloc");
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	}

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	foreach_irp_irg(i, irg) {
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		/* Turn all small CopyBs into loads/stores, and turn all bigger
		 * CopyBs into memcpy calls, because we cannot handle CopyB nodes
		 * during code generation yet.
		 * TODO:  Adapt this once custom CopyB handling is implemented. */
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		lower_CopyB(irg, 64, 65, true);
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		be_after_transform(irg, "lower-copyb");
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	}
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	ir_builtin_kind supported[6];
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	size_t  s = 0;
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	supported[s++] = ir_bk_ffs;
	supported[s++] = ir_bk_clz;
	supported[s++] = ir_bk_ctz;
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	supported[s++] = ir_bk_compare_swap;
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	supported[s++] = ir_bk_saturating_increment;
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	supported[s++] = ir_bk_va_start;
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	assert(s <= ARRAY_SIZE(supported));
	lower_builtins(s, supported);
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	be_after_irp_transform("lower-builtins");
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}

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static int amd64_is_mux_allowed(ir_node *sel, ir_node *mux_false,
                                ir_node *mux_true)
{
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	/* optimizable by middleend */
	if (ir_is_optimizable_mux(sel, mux_false, mux_true))
		return true;
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	return false;
}

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static const ir_settings_arch_dep_t amd64_arch_dep = {
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	.also_use_subs        = true,
	.maximum_shifts       = 4,
	.highest_shift_amount = 63,
	.evaluate             = NULL,
	.allow_mulhs          = true,
	.allow_mulhu          = true,
	.max_bits_for_mulh    = 32,
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};
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static backend_params amd64_backend_params = {
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	.experimental                  = "the amd64 backend is highly experimental and unfinished (consider the ia32 backend)",
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	.byte_order_big_endian         = false,
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	.pic_supported                 = true,
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	.unaligned_memaccess_supported = true,
	.modulo_shift                  = 32,
	.dep_param                     = &amd64_arch_dep,
	.allow_ifconv                  = amd64_is_mux_allowed,
	.machine_size                  = 64,
	.mode_float_arithmetic         = NULL,  /* will be set later */
	.type_long_long                = NULL,  /* will be set later */
	.type_unsigned_long_long       = NULL,  /* will be set later */
	.type_long_double              = NULL,  /* will be set later */
	.stack_param_align             = 8,
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	.float_int_overflow            = ir_overflow_indefinite,
	.vararg                        = {
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		.va_list_type = NULL,  /* Will be set later */
		.lower_va_arg = amd64_lower_va_arg,
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	},
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};

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static const backend_params *amd64_get_backend_params(void) {
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	return &amd64_backend_params;
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}

static int amd64_is_valid_clobber(const char *clobber)
{
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	return x86_parse_clobber(amd64_additional_clobber_names, clobber) != NULL;
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}

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static void amd64_init_types(void)
{
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	ir_mode *const ptr_mode = new_reference_mode("p64", irma_twos_complement, 64, 64);
	set_modeP(ptr_mode);

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	/* use an int128 mode for xmm registers for now, so that firm allows us to
	 * create constants with the xmm mode... */
	amd64_mode_xmm = new_int_mode("x86_xmm", irma_twos_complement, 128, 0, 0);

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	x86_init_x87_type();
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	amd64_backend_params.type_long_double = x86_type_E;

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	amd64_backend_params.vararg.va_list_type = amd64_build_va_list_type();
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}

static void amd64_init(void)
{
	amd64_init_types();
	amd64_register_init();
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	amd64_create_opcodes();
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	amd64_cconv_init();
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	x86_set_be_asm_constraint_support(&amd64_asm_constraints);
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}

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static unsigned amd64_get_op_estimated_cost(const ir_node *node)
{
	(void)node;/* TODO */
	return 1;
}

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static arch_isa_if_t const amd64_isa_if = {
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	.n_registers           = N_AMD64_REGISTERS,
	.registers             = amd64_registers,
	.n_register_classes    = N_AMD64_CLASSES,
	.register_classes      = amd64_reg_classes,
	.init                  = amd64_init,
	.finish                = amd64_finish,
	.get_params            = amd64_get_backend_params,
	.generate_code         = amd64_generate_code,
	.lower_for_target      = amd64_lower_for_target,
	.is_valid_clobber      = amd64_is_valid_clobber,
	.handle_intrinsics     = amd64_handle_intrinsics,
	.get_op_estimated_cost = amd64_get_op_estimated_cost,
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};

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BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64)
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void be_init_arch_amd64(void)
{
	be_register_isa_if("amd64", &amd64_isa_if);
	FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
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	static const lc_opt_table_entry_t options[] = {
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		LC_OPT_ENT_BOOL("x64abi",      "Use x64 ABI (otherwise system V)", &amd64_use_x64_abi),
		LC_OPT_ENT_BOOL("no-red-zone", "gcc compatibility",                &amd64_use_red_zone),
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		LC_OPT_LAST
	};
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	lc_opt_entry_t *be_grp    = lc_opt_get_grp(firm_opt_get_root(), "be");
	lc_opt_entry_t *amd64_grp = lc_opt_get_grp(be_grp, "amd64");
	lc_opt_add_table(amd64_grp, options);
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	amd64_init_transform();
}