amd64_transform.c 84.1 KB
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/*
 * This file is part of libFirm.
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 * Copyright (C) 2012 University of Karlsruhe.
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 */

/**
 * @file
 * @brief   code selection (transform FIRM into amd64 FIRM)
 */
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#include "debug.h"
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#include "panic.h"
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#include "heights.h"
#include "ircons.h"
#include "irgmod.h"
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#include "irgraph_t.h"
#include "irmode_t.h"
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#include "irnode_t.h"
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#include "iropt_t.h"
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#include "tv_t.h"
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#include "util.h"
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#include "benode.h"
#include "betranshlp.h"
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#include "bearch_amd64_t.h"
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#include "beirg.h"
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#include "besched.h"
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#include "amd64_new_nodes.h"
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#include "amd64_nodes_attr.h"
#include "amd64_transform.h"
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#include "../ia32/x86_address_mode.h"
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#include "../ia32/x86_cconv.h"
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#include "gen_amd64_regalloc_if.h"

DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

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static ir_mode         *mode_gp;
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static x86_cconv_t     *current_cconv = NULL;
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static pmap            *node_to_stack;
static be_stackorder_t *stackorder;
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/** we don't have a concept of aliasing registers, so enumerate them
 * manually for the asm nodes. */
const x86_clobber_name_t amd64_additional_clobber_names[] = {
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	{ "al", REG_RAX }, { "ah", REG_RAX }, { "ax", REG_RAX }, { "eax", REG_RAX },
	{ "bl", REG_RBX }, { "bh", REG_RBX }, { "bx", REG_RBX }, { "ebx", REG_RBX },
	{ "cl", REG_RCX }, { "ch", REG_RCX }, { "cx", REG_RCX }, { "ecx", REG_RCX },
	{ "dl", REG_RDX }, { "dh", REG_RDX }, { "dx", REG_RDX }, { "edx", REG_RDX },
	{ "sil",  REG_RSI }, { "si",   REG_RSI }, { "esi",  REG_RSI },
	{ "dil",  REG_RDI }, { "di",   REG_RDI }, { "edi",  REG_RDI },
	{ "bpl",  REG_RBP }, { "bp",   REG_RBP }, { "ebp",  REG_RBP },
	{ "spl",  REG_RSP }, { "sp",   REG_RSP }, { "esp",  REG_RSP },
	{ "r8b",  REG_R8  }, { "r8w",  REG_R8  }, { "r8d",  REG_R8  },
	{ "r9b",  REG_R9  }, { "r9w",  REG_R9  }, { "r9d",  REG_R9  },
	{ "r10b", REG_R10 }, { "r10w", REG_R10 }, { "r10d", REG_R10 },
	{ "r11b", REG_R11 }, { "r11w", REG_R11 }, { "r11d", REG_R11 },
	{ "r12b", REG_R12 }, { "r12w", REG_R12 }, { "r12d", REG_R12 },
	{ "r13b", REG_R13 }, { "r13w", REG_R13 }, { "r13d", REG_R13 },
	{ "r14b", REG_R14 }, { "r14w", REG_R14 }, { "r14d", REG_R14 },
	{ "r15b", REG_R15 }, { "r15w", REG_R15 }, { "r15d", REG_R15 },
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	{ NULL, ~0u }
};

#define GP &amd64_reg_classes[CLASS_amd64_gp]
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const x86_asm_constraint_list_t amd64_asm_constraints = {
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	['A'] = { MATCH_REG, GP, 1 << REG_GP_RAX | 1 << REG_GP_RDX },
	['D'] = { MATCH_REG, GP, 1 << REG_GP_RDI },
	['I'] = { MATCH_IMM, GP, 0 },
	['J'] = { MATCH_IMM, GP, 0 },
	['K'] = { MATCH_IMM, GP, 0 },
	['L'] = { MATCH_IMM, GP, 0 },
	['M'] = { MATCH_IMM, GP, 0 },
	['N'] = { MATCH_IMM, GP, 0 },
	['O'] = { MATCH_IMM, GP, 0 },
	['R'] = { MATCH_REG, GP, 1 << REG_GP_RAX | 1 << REG_GP_RBX
		| 1 << REG_GP_RCX | 1 << REG_GP_RDX | 1 << REG_GP_RSI
		| 1 << REG_GP_RDI | 1 << REG_GP_RBP | 1 << REG_GP_RSP },
	['S'] = { MATCH_REG, GP, 1 << REG_GP_RSI },
	['Q'] = { MATCH_REG, GP, 1 << REG_GP_RAX | 1 << REG_GP_RBX
		| 1 << REG_GP_RCX | 1 << REG_GP_RDX },
	['V'] = { MATCH_MEM, GP, 0 },
	['X'] = { MATCH_ANY, GP, 0 },
	['a'] = { MATCH_REG, GP, 1 << REG_GP_RAX },
	['b'] = { MATCH_REG, GP, 1 << REG_GP_RBX },
	['c'] = { MATCH_REG, GP, 1 << REG_GP_RCX },
	['d'] = { MATCH_REG, GP, 1 << REG_GP_RDX },
	['g'] = { MATCH_ANY, GP, 0 },
	['i'] = { MATCH_IMM, GP, 0 },
	['l'] = { MATCH_REG, GP, 1 << REG_GP_RAX | 1 << REG_GP_RBX
		| 1 << REG_GP_RCX | 1 << REG_GP_RDX | 1 << REG_GP_RSI
		| 1 << REG_GP_RDI | 1 << REG_GP_RBP },
	['m'] = { MATCH_MEM, GP, 0 },
	['n'] = { MATCH_IMM, GP, 0 },
	['o'] = { MATCH_MEM, GP, 0 },
	['p'] = { MATCH_REG, GP, 0 },
	['q'] = { MATCH_REG, GP, 0 },
	['r'] = { MATCH_REG, GP, 0 },
	['x'] = { MATCH_REG, &amd64_reg_classes[CLASS_amd64_xmm], 0 },

	// see comments in ia32_transform.c about unimplemented stuff.
};
#undef GP

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#define BIT(x)    (1u << x)

static const arch_register_req_t amd64_requirement_gp_same_0 = {
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	.cls               = &amd64_reg_classes[CLASS_amd64_gp],
	.should_be_same    = BIT(0),
	.width             = 1,
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};

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static const arch_register_req_t amd64_requirement_xmm_same_0 = {
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	.cls               = &amd64_reg_classes[CLASS_amd64_xmm],
	.should_be_same    = BIT(0),
	.width             = 1,
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};

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static const arch_register_req_t amd64_requirement_gp_same_0_not_1 = {
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	.cls               = &amd64_reg_classes[CLASS_amd64_gp],
	.should_be_same    = BIT(0),
	.must_be_different = BIT(1),
	.width             = 1,
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};

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static const arch_register_req_t amd64_requirement_xmm_same_0_not_1 = {
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	.cls               = &amd64_reg_classes[CLASS_amd64_xmm],
	.should_be_same    = BIT(0),
	.must_be_different = BIT(1),
	.width             = 1,
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};

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static const arch_register_req_t *mem_reqs[] = {
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	&arch_memory_requirement,
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};

static const arch_register_req_t *reg_mem_reqs[] = {
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	&amd64_class_reg_req_gp,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *rsp_mem_reqs[] = {
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	&amd64_single_reg_req_gp_rsp,
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	&arch_memory_requirement,
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};

static const arch_register_req_t *rsp_reg_mem_reqs[] = {
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	&amd64_single_reg_req_gp_rsp,
	&amd64_class_reg_req_gp,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *xmm_mem_reqs[] = {
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	&amd64_class_reg_req_xmm,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *reg_reg_mem_reqs[] = {
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	&amd64_class_reg_req_gp,
	&amd64_class_reg_req_gp,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *xmm_reg_mem_reqs[] = {
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	&amd64_class_reg_req_xmm,
	&amd64_class_reg_req_gp,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *reg_reg_reg_mem_reqs[] = {
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	&amd64_class_reg_req_gp,
	&amd64_class_reg_req_gp,
	&amd64_class_reg_req_gp,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *xmm_reg_reg_mem_reqs[] = {
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	&amd64_class_reg_req_xmm,
	&amd64_class_reg_req_gp,
	&amd64_class_reg_req_gp,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *reg_flags_reqs[] = {
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	&amd64_class_reg_req_gp,
	&amd64_class_reg_req_flags,
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};

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static const arch_register_req_t *reg_reg_reqs[] = {
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	&amd64_class_reg_req_gp,
	&amd64_class_reg_req_gp,
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};

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static const arch_register_req_t *rax_reg_reqs[] = {
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	&amd64_single_reg_req_gp_rax,
	&amd64_class_reg_req_gp,
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};

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static const arch_register_req_t *rax_reg_rdx_mem_reqs[] = {
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	&amd64_single_reg_req_gp_rax,
	&amd64_class_reg_req_gp,
	&amd64_single_reg_req_gp_rdx,
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	&arch_memory_requirement,
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};

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static const arch_register_req_t *reg_reqs[] = {
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	&amd64_class_reg_req_gp,
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};

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arch_register_req_t const *amd64_xmm_reqs[] = {
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	&amd64_class_reg_req_xmm,
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};

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static const arch_register_req_t *reg_rcx_reqs[] = {
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	&amd64_class_reg_req_gp,
	&amd64_single_reg_req_gp_rcx,
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};

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static const arch_register_req_t *no_reqs[] = {
};

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static const arch_register_req_t *xmm_xmm_reqs[] = {
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	&amd64_class_reg_req_xmm,
	&amd64_class_reg_req_xmm,
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};

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arch_register_req_t const **const gp_am_reqs[] = {
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	mem_reqs,
	reg_mem_reqs,
	reg_reg_mem_reqs,
	reg_reg_reg_mem_reqs,
};

static arch_register_req_t const **const xmm_am_reqs[] = {
	mem_reqs,
	xmm_mem_reqs,
	xmm_reg_mem_reqs,
	xmm_reg_reg_mem_reqs,
};

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static inline bool mode_needs_gp_reg(ir_mode *mode)
{
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	return get_mode_arithmetic(mode) == irma_twos_complement
	    && mode != amd64_mode_xmm; /* mode_xmm is 128bit int at the moment */
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}

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static ir_node *get_initial_sp(ir_graph *irg)
{
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	return be_get_Start_proj(irg, &amd64_registers[REG_RSP]);
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}

static ir_node *get_initial_fp(ir_graph *irg)
{
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	return be_get_Start_proj(irg, &amd64_registers[REG_RBP]);
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}

static ir_node *get_frame_base(ir_graph *irg)
{
	if (current_cconv->omit_fp) {
		return get_initial_sp(irg);
	} else {
		return get_initial_fp(irg);
	}
}
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static amd64_insn_mode_t get_insn_mode_from_mode(const ir_mode *mode)
{
	switch (get_mode_size_bits(mode)) {
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	case   8: return INSN_MODE_8;
	case  16: return INSN_MODE_16;
	case  32: return INSN_MODE_32;
	case  64: return INSN_MODE_64;
	case 128: return INSN_MODE_128;
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	}
	panic("unexpected mode");
}

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ir_entity *create_float_const_entity(ir_tarval *const tv)
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{
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	ir_entity *entity = pmap_get(ir_entity, amd64_constants, tv);
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	if (entity != NULL)
		return entity;

	ir_mode *mode = get_tarval_mode(tv);
	ir_type *type = get_type_for_mode(mode);
	ir_type *glob = get_glob_type();

	entity = new_entity(glob, id_unique("C%u"), type);
	set_entity_visibility(entity, ir_visibility_private);
	add_entity_linkage(entity, IR_LINKAGE_CONSTANT);

	ir_initializer_t *initializer = create_initializer_tarval(tv);
	set_entity_initializer(entity, initializer);

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	pmap_insert(amd64_constants, tv, entity);
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	return entity;
}

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void init_lconst_addr(amd64_addr_t *addr, ir_entity *entity)
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{
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	assert(entity_has_definition(entity));
	assert(get_entity_linkage(entity) == IR_LINKAGE_CONSTANT);
	assert(get_entity_visibility(entity) == ir_visibility_private);
	memset(addr, 0, sizeof(*addr));
	x86_immediate_kind_t kind = be_options.pic ? X86_IMM_PCREL : X86_IMM_ADDR;
	addr->immediate.entity = entity;
	addr->immediate.kind = kind;
	addr->index_input = NO_INPUT;
	addr->base_input = kind == X86_IMM_PCREL ? RIP_INPUT : NO_INPUT;
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}

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static ir_node *create_float_const(dbg_info *dbgi, ir_node *block,
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                                   ir_tarval *tv)
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{
	ir_graph  *irg     = get_irn_irg(block);
	ir_mode   *tv_mode = get_tarval_mode(tv);
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	ir_entity *entity  = create_float_const_entity(tv);
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	ir_node   *nomem   = get_irg_no_mem(irg);

	ir_node *in[] = { nomem };
	amd64_addr_t addr;
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	init_lconst_addr(&addr, entity);
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	ir_node *load;
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	unsigned pn_res;
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	amd64_insn_mode_t insn_mode = get_insn_mode_from_mode(tv_mode);
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	if (insn_mode == INSN_MODE_128) {
		load = new_bd_amd64_movdqa(dbgi, block, ARRAY_SIZE(in), in,
		                           AMD64_OP_ADDR, addr);
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		pn_res = pn_amd64_movdqa_res;
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	} else {
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		load = new_bd_amd64_movs_xmm(dbgi, block, ARRAY_SIZE(in), in,
		                             insn_mode, AMD64_OP_ADDR, addr);
		pn_res = pn_amd64_movs_xmm_res;
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	}
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	arch_set_irn_register_reqs_in(load, mem_reqs);
	set_irn_pinned(load, op_pin_state_floats);

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	return be_new_Proj(load, pn_res);
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}

ir_tarval *create_sign_tv(ir_mode *mode)
{
	unsigned size = get_mode_size_bits(mode);
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	assert(size == 32 || size == 64 || size == 128);
	ir_mode *intmode = size == 128 ? amd64_mode_xmm
	                 : size == 64  ? mode_Lu
	                               : mode_Iu;
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	ir_tarval *one  = get_mode_one(intmode);
	ir_tarval *sign = tarval_shl_unsigned(one, size-1);
	return tarval_bitcast(sign, mode);
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}

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static ir_node *gen_Const(ir_node *node)
{
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	ir_node  *block = be_transform_nodes_block(node);
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	dbg_info *dbgi  = get_irn_dbg_info(node);
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	ir_mode  *mode  = get_irn_mode(node);
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	ir_tarval *tv = get_Const_tarval(node);
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	if (!mode_needs_gp_reg(mode)) {
		if (tarval_is_null(tv)) {
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			return new_bd_amd64_xorpd_0(dbgi, block);
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		}

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		return create_float_const(dbgi, block, tv);
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	}

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	uint64_t val = get_tarval_uint64(tv);
	amd64_insn_mode_t imode = val > UINT32_MAX ? INSN_MODE_64 : INSN_MODE_32;
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	amd64_imm64_t const imm = {
		.kind   = X86_IMM_VALUE,
		.offset = val,
	};
	return new_bd_amd64_mov_imm(dbgi, block, imode, &imm);
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}

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static ir_node *gen_Address(ir_node *node)
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{
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	ir_node   *block  = be_transform_nodes_block(node);
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	dbg_info  *dbgi   = get_irn_dbg_info(node);
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	ir_entity *entity = get_Address_entity(node);
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	amd64_imm64_t const imm = {
		.kind   = X86_IMM_ADDR,
		.entity = entity,
	};
	return new_bd_amd64_mov_imm(dbgi, block, INSN_MODE_64, &imm);
}
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static ir_node *gen_be_Relocation(ir_node *node)
{
	ir_node             *const block  = be_transform_nodes_block(node);
	ir_entity           *const entity = be_get_Relocation_entity(node);
	x86_immediate_kind_t const kind
		= (x86_immediate_kind_t)be_get_Relocation_kind(node);
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	switch (kind) {
	case X86_IMM_ADDR: {
		amd64_imm64_t const imm = {
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			.kind   = X86_IMM_ADDR,
			.entity = entity,
		};
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		return new_bd_amd64_mov_imm(NULL, block, INSN_MODE_64, &imm);
	}
	case X86_IMM_PCREL:
	case X86_IMM_GOTPCREL: { /* can GOTPCREL happen here? */
		amd64_addr_t addr;
		memset(&addr, 0, sizeof(addr));
		addr.base_input  = RIP_INPUT;
		addr.index_input = NO_INPUT;
		addr.mem_input   = NO_INPUT;
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		addr.immediate = (x86_imm32_t) {
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			.kind   = kind,
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			.entity = entity,
		};
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		return new_bd_amd64_lea(NULL, block, 0, NULL, INSN_MODE_64, addr);
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	}
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	default:
		break;
	}
	panic("Unexpected relocation kind");
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}

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ir_node *amd64_new_IncSP(ir_node *block, ir_node *old_sp, int offset,
                         unsigned align)
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{
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	ir_node *incsp = be_new_IncSP(&amd64_registers[REG_RSP], block, old_sp,
	                              offset, align);
	arch_add_irn_flags(incsp, arch_irn_flag_modify_flags);
	return incsp;
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}

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typedef ir_node *(*construct_binop_func)(dbg_info *dbgi, ir_node *block, int arity, ir_node *const in[], amd64_binop_addr_attr_t const *attr_init);
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typedef ir_node *(*construct_rax_binop_func)(dbg_info *dbgi, ir_node *block, int arity, ir_node *const in[], amd64_insn_mode_t insn_mode, amd64_op_mode_t op_mode, amd64_addr_t addr);
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typedef enum match_flags_t {
	match_am           = 1 << 0,
	match_mode_neutral = 1 << 1,
	match_immediate    = 1 << 2,
	match_commutative  = 1 << 3,
} match_flags_t;

typedef struct amd64_args_t {
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	amd64_binop_addr_attr_t     attr;
	ir_node                    *mem_proj;
	ir_node                    *in[4];
	int                         arity;
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	const arch_register_req_t **reqs;
} amd64_args_t;

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static bool match_immediate_32(x86_imm32_t *imm, const ir_node *op,
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                               bool can_match_ip_relative,
                               bool upper32_dont_care)
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{
	assert(mode_needs_gp_reg(get_irn_mode(op)));
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	assert(imm->offset == 0 && imm->entity == NULL
	       && imm->kind == X86_IMM_VALUE);
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	ir_tarval *tv;
	ir_entity *entity;
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	unsigned   reloc_kind;
	if (!be_match_immediate(op, &tv, &entity, &reloc_kind))
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		return false;

	int32_t val;
	if (tv) {
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		if (!tarval_is_long(tv))
			return false;
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		long lval = get_tarval_long(tv);
		val = (int32_t)lval;
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		if ((long)val != lval)
			return false;
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		/** the immediate value is signed extended to 64bit, sometimes
		 * this is not what we want. */
		if (!upper32_dont_care && val < 0
		    && !mode_is_signed(get_tarval_mode(tv)))
		    return false;
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	} else {
		val = 0;
	}

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	x86_immediate_kind_t kind = (x86_immediate_kind_t)reloc_kind;
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	if (entity != NULL) {
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		if (!can_match_ip_relative)
			return false;
		if (kind == X86_IMM_VALUE || kind == X86_IMM_ADDR) {
			kind = X86_IMM_PCREL;
		} else if (kind != X86_IMM_PCREL)
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			return false;
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	}
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	imm->entity = entity;
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	imm->offset = val;
	imm->kind   = kind;
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	return true;
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}

static ir_heights_t *heights;

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static bool input_depends_on_load(ir_node *load, ir_node *input)
{
	ir_node *block = get_nodes_block(load);
	/* if the dependency is in another block, then we ignore it for now
	   as we only match address mode loads in the same block. */
	return get_nodes_block(input) == block
	    && heights_reachable_in_block(heights, input, load);
}

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static void fix_node_mem_proj(ir_node *node, ir_node *mem_proj)
{
	if (mem_proj == NULL)
		return;

	ir_node *load = get_Proj_pred(mem_proj);
	be_set_transformed_node(load, node);
}

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static ir_node *source_am_possible(ir_node *block, ir_node *node)
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{
	if (!is_Proj(node))
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		return NULL;
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	ir_node *load = get_Proj_pred(node);
	if (!is_Load(load))
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		return NULL;
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	assert(get_Proj_num(node) == pn_Load_res);
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	if (get_nodes_block(load) != block)
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		return NULL;
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	/* make sure we are the only user */
	if (get_irn_n_edges(node) != 1)
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		return NULL;
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	/* From ia32_transform.c:751:
	 * in some edge cases with address mode we might reach the load normally
	 * and through some AM sequence, if it is already materialized then we
	 * can't create an AM node from it */
	if (be_is_transformed(node))
		return NULL;
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	return load;
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}

static bool needs_extension(ir_node *op)
{
	ir_mode *mode = get_irn_mode(op);
	if (get_mode_size_bits(mode) >= 32)
		return false;
	return !be_upper_bits_clean(op, mode);
}

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static ir_node *create_sext(ir_node *new_block, ir_node *const node, ir_mode *mode)
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{
	amd64_insn_mode_t insn_mode = get_insn_mode_from_mode(mode);
	dbg_info *const   dbgi      = get_irn_dbg_info(node);
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	ir_node  *const   new_node  = be_transform_node(node);
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	amd64_shift_attr_t attr;
	memset(&attr, 0, sizeof(attr));
	attr.base.op_mode = AMD64_OP_SHIFT_IMM;
	attr.insn_mode    = insn_mode;
	attr.immediate    = get_mode_size_bits(mode) - 1;
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	ir_node *in[1]    = { new_node };
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	ir_node *sar      = new_bd_amd64_sar(dbgi, new_block, ARRAY_SIZE(in),
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	                                     in, &attr);
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	arch_set_irn_register_reqs_in(sar, reg_reqs);
	arch_set_irn_register_req_out(sar, 0, &amd64_requirement_gp_same_0);
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	return be_new_Proj(sar, pn_amd64_sar_res);
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}

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static ir_node *create_zext(ir_node *new_block, ir_node *const node)
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{
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	dbg_info *const dbgi      = get_irn_dbg_info(node);
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	ir_node  *const xor0      = new_bd_amd64_xor_0(dbgi, new_block);
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	arch_set_irn_register_reqs_in(xor0, reg_reqs);
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	return be_new_Proj(xor0, pn_amd64_xor_0_res);
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}

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static bool use_address_matching(ir_mode *mode, match_flags_t flags,
                                 ir_node *block,
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                                 ir_node *op1, ir_node *op2,
                                 ir_node **out_load, ir_node **out_op)
{
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	if (! (flags & match_am))
		return false;
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	unsigned mode_bits = get_mode_size_bits(mode);
	if (mode_bits == 8 || mode_bits == 16)
		return false;

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	ir_node *load2 = source_am_possible(block, op2);
	if (load2 != NULL && !input_depends_on_load(load2, op1)) {
		(*out_load) = load2;
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		(*out_op)   = op1;
		return true;
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	}

	if (flags & match_commutative) {
		ir_node *load1 = source_am_possible(block, op1);
		if (load1 != NULL && !input_depends_on_load(load1, op2)) {
			(*out_load) = load1;
			(*out_op)   = op2;
			return true;
		}
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	}
	return false;
}

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static void perform_address_matching(ir_node *ptr, int *arity,
                                     ir_node **in, amd64_addr_t *addr)
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{
	x86_address_t maddr;
	memset(&maddr, 0, sizeof(maddr));
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	x86_create_address_mode(&maddr, ptr, x86_create_am_normal);
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	if (maddr.base != NULL) {
		int base_input   = (*arity)++;
		addr->base_input = base_input;
		in[base_input]   = be_transform_node(maddr.base);
	} else {
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		addr->base_input = maddr.ip_base ? RIP_INPUT : NO_INPUT;
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	}
	if (maddr.index != NULL) {
		int index_input = (*arity)++;
		addr->index_input = index_input;
		in[index_input]  = be_transform_node(maddr.index);
	} else {
		addr->index_input = NO_INPUT;
	}
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	ir_entity *entity = maddr.imm.entity;
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	if (entity != NULL && is_parameter_entity(entity) &&
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		get_entity_parameter_number(entity) == IR_VA_START_PARAMETER_NUMBER)
		panic("VA_START not supported yet");

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	addr->immediate = maddr.imm;
	addr->log_scale = maddr.scale;
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}

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static void match_binop(amd64_args_t *args, ir_node *block,
                        ir_mode *mode, ir_node *op1, ir_node *op2,
                        match_flags_t flags)
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{
	memset(args, 0, sizeof(*args));

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	bool use_am;
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	bool use_xmm       = mode_is_float(mode);
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	bool use_immediate = flags & match_immediate;
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	bool mode_neutral  = flags & match_mode_neutral;
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	args->attr.base.insn_mode = get_insn_mode_from_mode(mode);
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	/* TODO: legalize phase */
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	if (mode_neutral) {
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		op1 = be_skip_downconv(op1, true);
		op2 = be_skip_downconv(op2, true);
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	} else {
		/* TODO: extend inputs? */
		(void)needs_extension;
	}

	ir_node *load;
	ir_node *op;
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	use_am = use_address_matching(mode, flags, block, op1, op2, &load, &op);
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	if (use_immediate
	    && match_immediate_32(&args->attr.u.immediate, op2, false, mode_neutral)) {
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		assert(!use_xmm && "Can't (yet) match binop with xmm immediate");
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		/* fine, we found an immediate */
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		args->attr.base.base.op_mode = AMD64_OP_REG_IMM;
		args->in[args->arity++]      = be_transform_node(op1);
		args->reqs                   = reg_reqs;
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	} else if (use_am) {
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		ir_node *new_op        = be_transform_node(op);
		int      reg_input     = args->arity++;
		args->attr.u.reg_input = reg_input;
		args->in[reg_input]    = new_op;
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		amd64_addr_t *addr     = &args->attr.base.addr;
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		ir_node *ptr = get_Load_ptr(load);
		perform_address_matching(ptr, &(args->arity), args->in, addr);

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		args->reqs = (use_xmm ? xmm_am_reqs : gp_am_reqs)[args->arity];

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		ir_node *new_mem    = be_transform_node(get_Load_mem(load));
		int mem_input       = args->arity++;
		args->in[mem_input] = new_mem;
		addr->mem_input     = mem_input;
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		args->mem_proj      = get_Proj_for_pn(load, pn_Load_M);
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		args->attr.base.base.op_mode = AMD64_OP_REG_ADDR;
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	} else {
		/* simply transform the arguments */
		args->in[args->arity++] = be_transform_node(op1);
		args->in[args->arity++] = be_transform_node(op2);
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		args->attr.base.base.op_mode = AMD64_OP_REG_REG;
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		args->reqs = use_xmm ? xmm_xmm_reqs : reg_reg_reqs;
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	}
}

static ir_node *gen_binop_am(ir_node *node, ir_node *op1, ir_node *op2,
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                             construct_binop_func func, unsigned pn_res,
                             match_flags_t flags)
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{
	ir_node *block = get_nodes_block(node);
	ir_mode *mode  = get_irn_mode(node);
	amd64_args_t args;
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	match_binop(&args, block, mode, op1, op2, flags);
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	dbg_info *const dbgi      = get_irn_dbg_info(node);
	ir_node  *const new_block = be_transform_node(block);

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	ir_node *new_node = func(dbgi, new_block, args.arity, args.in, &args.attr);
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	arch_set_irn_register_reqs_in(new_node, args.reqs);
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	fix_node_mem_proj(new_node, args.mem_proj);
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	if (mode_is_float(mode)) {
		arch_set_irn_register_req_out(new_node, 0,
		                              &amd64_requirement_xmm_same_0);
	} else {
		arch_set_irn_register_req_out(new_node, 0,
		                              &amd64_requirement_gp_same_0);
	}
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	return be_new_Proj(new_node, pn_res);
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}

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static ir_node *gen_binop_rax(ir_node *node, ir_node *op1, ir_node *op2,
                              construct_rax_binop_func make_node,
                              match_flags_t flags)
{
	bool use_am;
	bool mode_neutral  = flags & match_mode_neutral;
	assert(! (flags & match_immediate));

	ir_mode *mode = get_irn_mode(op1);
	amd64_insn_mode_t insn_mode = get_insn_mode_from_mode(mode);

	/* TODO: legalize phase */
	if (mode_neutral) {
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		op1 = be_skip_downconv(op1, true);
		op2 = be_skip_downconv(op2, true);
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	} else {
		/* TODO: extend inputs? */
		(void)needs_extension;
	}

	ir_node *load;
	ir_node *op;
	ir_node *block = get_nodes_block(node);
	ir_node *in[4];
	int      arity = 0;
	const arch_register_req_t **reqs;
	amd64_op_mode_t op_mode;
	amd64_addr_t    addr;
	memset(&addr, 0, sizeof(addr));

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	use_am = use_address_matching(mode, flags, block, op1, op2, &load, &op);
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	ir_node *mem_proj = NULL;
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	if (use_am) {
		ir_node *new_op    = be_transform_node(op);
		int      reg_input = arity++;
		in[reg_input]      = new_op;

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		ir_node *ptr = get_Load_ptr(load);
		perform_address_matching(ptr, &arity, in, &addr);

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		reqs = gp_am_reqs[arity];
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		ir_node *new_mem = be_transform_node(get_Load_mem(load));
		int mem_input    = arity++;
		in[mem_input]    = new_mem;
		addr.mem_input   = mem_input;
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		mem_proj                = get_Proj_for_pn(load, pn_Load_M);
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		op_mode                 = AMD64_OP_RAX_ADDR;
	} else {
		/* simply transform the arguments */
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		in[arity++] = be_transform_node(op1);
		in[arity++] = be_transform_node(op2);
		reqs        = rax_reg_reqs;
		op_mode     = AMD64_OP_RAX_REG;
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	}

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	assert((size_t)arity <= ARRAY_SIZE(in));
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	dbg_info *dbgi      = get_irn_dbg_info(node);
	ir_node  *new_block = be_transform_node(block);
	ir_node  *new_node  = make_node(dbgi, new_block, arity, in, insn_mode,
	                                op_mode, addr);
	arch_set_irn_register_reqs_in(new_node, reqs);
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	if (mem_proj != NULL) {
		be_set_transformed_node(load, new_node);
	}
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	return new_node;
}

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static ir_node *gen_binop_xmm(ir_node *node, ir_node *op0, ir_node *op1,
                              construct_binop_func make_node,
                              match_flags_t flags)
{
	ir_node *block = get_nodes_block(node);
	ir_mode *mode  = get_irn_mode(op0);
	amd64_args_t args;
	memset(&args, 0, sizeof(args));

	ir_node *load;
	ir_node *op;
	bool use_am = use_address_matching(mode, flags, block, op0, op1, &load,
	                                   &op);

	if (use_am) {
		int reg_input = args.arity++;
		args.attr.u.reg_input = reg_input;
		args.in[reg_input]    = be_transform_node(op);

		amd64_addr_t *addr = &args.attr.base.addr;
		ir_node      *ptr  = get_Load_ptr(load);
		perform_address_matching(ptr, &args.arity, args.in, addr);

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		args.reqs = xmm_am_reqs[args.arity];
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		ir_node *new_mem   = be_transform_node(get_Load_mem(load));
		int mem_input      = args.arity++;
		args.in[mem_input] = new_mem;
		addr->mem_input    = mem_input;

		args.mem_proj      = get_Proj_for_pn(load, pn_Load_M);
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		args.attr.base.base.op_mode = AMD64_OP_REG_ADDR;
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	} else {
		args.in[args.arity++] = be_transform_node(op0);
		args.in[args.arity++] = be_transform_node(op1);
		args.attr.base.base.op_mode = AMD64_OP_REG_REG;
		args.reqs = xmm_xmm_reqs;
	}

	dbg_info *const dbgi      = get_irn_dbg_info(node);
	ir_node  *const new_block = be_transform_node(block);
	ir_node *new_node = make_node(dbgi, new_block, args.arity, args.in,
	                              &args.attr);
	arch_set_irn_register_reqs_in(new_node, args.reqs);

	fix_node_mem_proj(new_node, args.mem_proj);

	arch_set_irn_register_req_out(new_node, 0,
								  &amd64_requirement_xmm_same_0);
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	return be_new_Proj(new_node, pn_amd64_subs_res);
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}

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typedef ir_node *(*construct_shift_func)(dbg_info *dbgi, ir_node *block, int arity, ir_node *const in[], amd64_shift_attr_t const *attr_init);
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static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
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                                construct_shift_func func, unsigned pn_res,
                                match_flags_t flags)
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{
	ir_mode *mode = get_irn_mode(node);
	assert(!mode_is_float(mode));

	if (get_mode_modulo_shift(mode) != 32 && get_mode_size_bits(mode) != 64)
		panic("insupported modulo shift used");

	ir_node *in[3];
	int      arity = 0;
	if (flags & match_mode_neutral) {
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		op1 = be_skip_downconv(op1, true);
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		in[arity++] = be_transform_node(op1);
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		mode = get_mode_size_bits(mode) > 32 ? mode_gp : mode_Iu;
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	} else {
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		op1 = be_skip_sameconv(op1);
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		/* Use 8/16bit operations instead of doing zext/upconv */
		in[arity++] = be_transform_node(op1);
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	}

	/* we can skip any convs for the shift count, as it only uses the lowest
	 * 5/6 bits anyway */
	while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
		ir_node *const op = get_Conv_op(op2);
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		if (get_mode_arithmetic(get_irn_mode(op)) != irma_twos_complement)
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			break;
		op2 = op;
	}

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	amd64_shift_attr_t attr;
	memset(&attr, 0, sizeof(attr));
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	const arch_register_req_t **reqs;
	const arch_register_req_t  *out_req0;
	if (is_Const(op2)) {
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		attr.base.op_mode = AMD64_OP_SHIFT_IMM;
		reqs              = reg_reqs;
		out_req0          = &amd64_requirement_gp_same_0;
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		attr.immediate    = get_Const_long(op2);
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	} else {
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		attr.base.op_mode = AMD64_OP_SHIFT_REG;
		in[arity++]       = be_transform_node(op2);
		reqs              = reg_rcx_reqs;
		out_req0          = &amd64_requirement_gp_same_0_not_1;
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	}
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	attr.insn_mode = get_insn_mode_from_mode(mode);
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	dbg_info *const dbgi      = get_irn_dbg_info(node);
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	ir_node  *const new_block = be_transform_nodes_block(node);
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	ir_node  *const new_node  = func(dbgi, new_block, arity, in, &attr);
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	arch_set_irn_register_reqs_in(new_node, reqs);
	arch_set_irn_register_req_out(new_node, 0, out_req0);
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	return be_new_Proj(new_node, pn_res);
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}

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static ir_node *create_lea_as_add(ir_node *node, ir_node *op1, ir_node *op2)
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{
	dbg_info *const dbgi = get_irn_dbg_info(node);
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	ir_node  *new_block  = be_transform_nodes_block(node);
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	ir_mode *mode        = get_irn_mode(node);

	amd64_insn_mode_t insn_mode;
	if (get_mode_size_bits(mode) <= 32)
		insn_mode = INSN_MODE_32;
	else
		insn_mode = INSN_MODE_64;

	const arch_register_req_t **reqs;
	amd64_addr_t addr;
	memset(&addr, 0, sizeof(addr));

	ir_node *in[2];
	int arity = 0;

	if (match_immediate_32(&addr.immediate, op2, false, true)) {
		in[arity++]      = be_transform_node(op1);
		reqs             = reg_reqs;
		addr.index_input = NO_INPUT;
	} else {
		in[arity++]      = be_transform_node(op1);
		in[arity++]      = be_transform_node(op2);
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		addr.base_input  = 0;
		addr.index_input = 1;
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		reqs             = reg_reg_reqs;
	}

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	ir_node *res = new_bd_amd64_lea(dbgi, new_block, arity, in, insn_mode, addr);
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	arch_set_irn_register_reqs_in(res, reqs);
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	return res;
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}

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static ir_node *gen_Add(ir_node *const node)
{
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	match_flags_t flags = match_immediate | match_am | match_mode_neutral
	                      | match_commutative;

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	ir_node *op1 = get_Add_left(node);
	ir_node *op2 = get_Add_right(node);
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	ir_mode *mode  = get_irn_mode(node);
	ir_node *block = get_nodes_block(node);
	ir_node *load, *op;

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	if (mode_is_float(mode)) {
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		return gen_binop_am(node, op1, op2, new_bd_amd64_adds,
							pn_amd64_adds_res, match_commutative | match_am);
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	}

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	bool use_am = use_address_matching(mode, flags, block, op1, op2, &load, &op);

	ir_node *res;
	if (use_am)
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		res = gen_binop_am(node, op1, op2, new_bd_amd64_add, pn_amd64_add_res,
		                   flags);
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	else
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		res = create_lea_as_add(node, op1, op2);
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	x86_mark_non_am(node);
	return res;
}
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static ir_node *gen_Sub(ir_node *const node)
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{
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	ir_node  *const op1     = get_Sub_left(node);
	ir_node  *const op2     = get_Sub_right(node);
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	ir_mode  *const mode    = get_irn_mode(node);
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	if (mode_is_float(mode)) {
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		return gen_binop_am(node, op1, op2, new_bd_amd64_subs,
		                    pn_amd64_subs_res, match_am);
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	} else {
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		/* TODO: do not match AM yet until we have a sub->neg+add rule
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		 * in amd64_finish */
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		return gen_binop_am(node, op1, op2, new_bd_amd64_sub, pn_amd64_sub_res,
		                    match_immediate);
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	}
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}

static ir_node *gen_And(ir_node *const node)
{
	ir_node *op1 = get_And_left(node);
	ir_node *op2 = get_And_right(node);
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	return gen_binop_am(node, op1, op2, new_bd_amd64_and, pn_amd64_and_res,
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	                    match_immediate | match_am | match_mode_neutral
	                    | match_commutative);
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}

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static ir_node *gen_Eor(ir_node *const node)
{
	ir_node *op1 = get_Eor_left(node);
	ir_node *op2 = get_Eor_right(node);
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	return gen_binop_am(node, op1, op2, new_bd_amd64_xor, pn_amd64_xor_res,
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	                    match_immediate | match_am | match_mode_neutral
	                    | match_commutative);
}

static ir_node *gen_Or(ir_node *const node)
{
	ir_node *op1 = get_Or_left(node);
	ir_node *op2 = get_Or_right(node);
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	return gen_binop_am(node, op1, op2, new_bd_amd64_or, pn_amd64_or_res,
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	                    match_immediate | match_am |