ia32_optimize.c 49.8 KB
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/**
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 * Project:     libFIRM
 * File name:   ir/be/ia32/ia32_optimize.c
 * Purpose:     Implements several optimizations for IA32
 * Author:      Christian Wuerdig
 * CVS-ID:      $Id$
 * Copyright:   (c) 2006 Universitt Karlsruhe
 * Licence:     This file protected by GPL -  GNU GENERAL PUBLIC LICENSE.
 */

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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "irnode.h"
#include "irprog_t.h"
#include "ircons.h"
#include "firm_types.h"
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#include "iredges.h"
#include "tv.h"
#include "irgmod.h"
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#include "irgwalk.h"
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#include "height.h"
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#include "irbitset.h"
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#include "../be_t.h"
#include "../beabi.h"
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#include "../benode_t.h"
#include "../besched_t.h"
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#include "ia32_new_nodes.h"
#include "bearch_ia32_t.h"
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#include "gen_ia32_regalloc_if.h"     /* the generated interface (register type and class defenitions) */
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#include "ia32_transform.h"
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#include "ia32_dbg_stat.h"
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#include "ia32_util.h"
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#define AGGRESSIVE_AM

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typedef enum {
	IA32_AM_CAND_NONE  = 0,
	IA32_AM_CAND_LEFT  = 1,
	IA32_AM_CAND_RIGHT = 2,
	IA32_AM_CAND_BOTH  = 3
} ia32_am_cand_t;

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#undef is_NoMem
#define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)

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typedef int is_op_func_t(const ir_node *n);
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typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
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/**
 * checks if a node represents the NOREG value
 */
static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
  be_abi_irg_t *babi = cg->birg->abi;
	const arch_register_t *fp_noreg = USE_SSE2(cg) ?
		&ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
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	return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
	       (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
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}

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/*************************************************
 *   _____                _              _
 *  / ____|              | |            | |
 * | |     ___  _ __  ___| |_ __ _ _ __ | |_ ___
 * | |    / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
 *  \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
 *
 *************************************************/

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/**
 * creates a unique ident by adding a number to a tag
 *
 * @param tag   the tag string, must contain a %d if a number
 *              should be added
 */
static ident *unique_id(const char *tag)
{
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	static unsigned id = 0;
	char str[256];
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	snprintf(str, sizeof(str), tag, ++id);
	return new_id_from_str(str);
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}

/**
 * Transforms a SymConst.
 *
 * @param mod     the debug module
 * @param block   the block the new node should belong to
 * @param node    the ir SymConst node
 * @param mode    mode of the SymConst
 * @return the created ia32 Const node
 */
static ir_node *gen_SymConst(ia32_transform_env_t *env) {
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	dbg_info *dbg   = env->dbg;
	ir_mode  *mode  = env->mode;
	ir_graph *irg   = env->irg;
	ir_node  *block = env->block;
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	ir_node  *cnst;
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	if (mode_is_float(mode)) {
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		FP_USED(env->cg);
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		if (USE_SSE2(env->cg))
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			cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
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		else
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			cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
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	}
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	else
		cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
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	set_ia32_Const_attr(cnst, env->irn);
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	return cnst;
}
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/**
 * Get a primitive type for a mode.
 */
static ir_type *get_prim_type(pmap *types, ir_mode *mode)
{
	pmap_entry *e = pmap_find(types, mode);
	ir_type *res;

	if (! e) {
		char buf[64];
		snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
		res = new_type_primitive(new_id_from_str(buf), mode);
		pmap_insert(types, mode, res);
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	}
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	else
		res = e->value;
	return res;
}
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/**
 * Get an entity that is initialized with a tarval
 */
static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
{
	tarval *tv    = get_Const_tarval(cnst);
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	pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
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	entity *res;
	ir_graph *rem;

	if (! e) {
		ir_mode *mode = get_irn_mode(cnst);
		ir_type *tp = get_Const_type(cnst);
		if (tp == firm_unknown_type)
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			tp = get_prim_type(cg->isa->types, mode);
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		res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
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		set_entity_ld_ident(res, get_entity_ident(res));
		set_entity_visibility(res, visibility_local);
		set_entity_variability(res, variability_constant);
		set_entity_allocation(res, allocation_static);

		 /* we create a new entity here: It's initialization must resist on the
		    const code irg */
		rem = current_ir_graph;
		current_ir_graph = get_const_code_irg();
		set_atomic_ent_value(res, new_Const_type(tv, tp));
		current_ir_graph = rem;
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		pmap_insert(cg->isa->tv_ent, tv, res);
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	}
	else
		res = e->value;
	return res;
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}

/**
 * Transforms a Const.
 *
 * @param mod     the debug module
 * @param block   the block the new node should belong to
 * @param node    the ir Const node
 * @param mode    mode of the Const
 * @return the created ia32 Const node
 */
static ir_node *gen_Const(ia32_transform_env_t *env) {
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	ir_node *cnst, *load;
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	symconst_symbol sym;
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	ir_graph *irg   = env->irg;
	ir_node  *block = env->block;
	ir_node  *node  = env->irn;
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	dbg_info *dbg   = env->dbg;
	ir_mode  *mode  = env->mode;
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	if (mode_is_float(mode)) {
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		FP_USED(env->cg);
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		if (! USE_SSE2(env->cg)) {
			cnst_classify_t clss = classify_Const(node);

			if (clss == CNST_NULL)
				return new_rd_ia32_vfldz(dbg, irg, block, mode);
			else if (clss == CNST_ONE)
				return new_rd_ia32_vfld1(dbg, irg, block, mode);
		}
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		sym.entity_p = get_entity_for_tv(env->cg, node);
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		cnst      = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
		load      = new_r_Load(irg, block, get_irg_no_mem(irg), cnst, mode);
		load      = new_r_Proj(irg, block, load, mode, pn_Load_res);
		env->irn  = cnst;
		env->mode = mode_P;
		cnst      = gen_SymConst(env);
		set_Load_ptr(get_Proj_pred(load), cnst);
		cnst      = load;
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	}
	else {
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		cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
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		set_ia32_Const_attr(cnst, node);
	}
	return cnst;
}

/**
 * Transforms (all) Const's into ia32_Const and places them in the
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 * block where they are used (or in the cfg-pred Block in case of Phi's).
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 * Additionally all reference nodes are changed into mode_Is nodes.
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 * NOTE: irn must be a firm constant!
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 */
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static void ia32_transform_const(ir_node *irn, void *env) {
	ia32_code_gen_t      *cg   = env;
	ir_node              *cnst = NULL;
	ia32_transform_env_t tenv;

	tenv.cg   = cg;
	tenv.irg  = cg->irg;
	tenv.mode = get_irn_mode(irn);
	tenv.dbg  = get_irn_dbg_info(irn);
	tenv.irn  = irn;
	DEBUG_ONLY(tenv.mod = cg->mod;)
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#if 1
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	/* place const either in the smallest dominator of all its users or the original block */
	if (cg->opt & IA32_OPT_PLACECNST)
		tenv.block = node_users_smallest_common_dominator(irn, 1);
	else
		tenv.block = get_nodes_block(irn);
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#else
	{
		ir_node *afterstart = NULL;
		ir_node *startblock = get_irg_start_block(tenv.irg);
		const ir_edge_t *edge;

		foreach_block_succ(startblock, edge) {
			ir_node *block = get_edge_src_irn(edge);
			if (block != startblock) {
				afterstart = block;
				break;
			}
		}
		assert(afterstart != NULL);
		tenv.block = afterstart;
	}
#endif
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	switch (get_irn_opcode(irn)) {
		case iro_Const:
			cnst = gen_Const(&tenv);
			break;
		case iro_SymConst:
			cnst = gen_SymConst(&tenv);
			break;
		default:
			assert(0 && "Wrong usage of ia32_transform_const!");
	}

	assert(cnst && "Could not create ia32 Const");

	/* set the new ia32 const */
	exchange(irn, cnst);
}

/**
 * Transform all firm consts and assure, we visit each const only once.
 */
static void ia32_place_consts_walker(ir_node *irn, void *env) {
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	ia32_code_gen_t *cg = env;
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	if(!is_Const(irn) && !is_SymConst(irn))
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		return;

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	ia32_transform_const(irn, cg);
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}

/**
 * Replace reference modes with mode_Iu and preserve store value modes.
 */
static void ia32_set_modes(ir_node *irn, void *env) {
	if (is_Block(irn))
		return;

	/* transform all reference nodes into mode_Iu nodes */
	if (mode_is_reference(get_irn_mode(irn))) {
		set_irn_mode(irn, mode_Iu);
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	}
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}
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/**
 * Walks over the graph, transforms all firm consts into ia32 consts
 * and places them into the "best" block.
 * @param cg  The ia32 codegenerator object
 */
static void ia32_transform_all_firm_consts(ia32_code_gen_t *cg) {
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	irg_walk_graph(cg->irg, NULL, ia32_place_consts_walker, cg);
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}
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/* Place all consts and change pointer arithmetics into unsigned integer arithmetics. */
void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
	/*
		We need to transform the consts twice:
		- the psi condition tree transformer needs existing constants to be ia32 constants
		- the psi condition tree transformer inserts new firm constants which need to be transformed
	*/
	ia32_transform_all_firm_consts(cg);
	irg_walk_graph(cg->irg, ia32_set_modes, ia32_transform_psi_cond_tree, cg);
	ia32_transform_all_firm_consts(cg);
}
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/********************************************************************************************************
 *  _____                _           _         ____        _   _           _          _   _
 * |  __ \              | |         | |       / __ \      | | (_)         (_)        | | (_)
 * | |__) |__  ___ _ __ | |__   ___ | | ___  | |  | |_ __ | |_ _ _ __ ___  _ ______ _| |_ _  ___  _ __
 * |  ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | |  | | '_ \| __| | '_ ` _ \| |_  / _` | __| |/ _ \| '_ \
 * | |  |  __/  __/ |_) | | | | (_) | |  __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
 * |_|   \___|\___| .__/|_| |_|\___/|_|\___|  \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
 *                | |                               | |
 *                |_|                               |_|
 ********************************************************************************************************/

/**
 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
 */

static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
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	return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
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}

/**
 * Checks for potential CJmp/CJmpAM optimization candidates.
 */
static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
	ir_node *cand = NULL;
	ir_node *prev = sched_prev(irn);

	if (is_Block(prev)) {
		if (get_Block_n_cfgpreds(prev) == 1)
			prev = get_Block_cfgpred(prev, 0);
		else
			prev = NULL;
	}

	/* The predecessor must be a ProjX. */
	if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
		prev = get_Proj_pred(prev);

		if (is_op_func(prev))
			cand = prev;
	}

	return cand;
}

static int is_TestJmp_cand(const ir_node *irn) {
	return is_ia32_TestJmp(irn) || is_ia32_And(irn);
}

/**
 * Checks if two consecutive arguments of cand matches
 * the two arguments of irn (TestJmp).
 */
static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
	ir_node *in1       = get_irn_n(irn, 0);
	ir_node *in2       = get_irn_n(irn, 1);
	int      i, n      = get_irn_arity(cand);
	int      same_args = 0;

	for (i = 0; i < n - 1; i++) {
		if (get_irn_n(cand, i)     == in1 &&
			get_irn_n(cand, i + 1) == in2)
		{
			same_args = 1;
			break;
		}
	}

	if (same_args)
		return ia32_cnst_compare(cand, irn);

	return 0;
}

/**
 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
 */
static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
	ir_node *cand    = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
	int      replace = 0;

	/* we found a possible candidate */
	replace = cand ? is_TestJmp_replacement(cand, irn) : 0;

	if (replace) {
		DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));

		if (is_ia32_And(cand))
			set_irn_op(irn, op_ia32_CJmpAM);
		else
			set_irn_op(irn, op_ia32_CJmp);

		DB((cg->mod, LEVEL_1, "%+F\n", irn));
	}
}

static int is_CondJmp_cand(const ir_node *irn) {
	return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
}

/**
 * Checks if the arguments of cand are the same of irn.
 */
static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
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	int i, n      = get_irn_arity(cand);
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	int same_args = 1;
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	for (i = 0; i < n; i++) {
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		if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
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			same_args = 0;
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			break;
		}
	}

	if (same_args)
		return ia32_cnst_compare(cand, irn);

	return 0;
}

/**
 * Tries to replace a CondJmp by a CJmpAM
 */
static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
	ir_node *cand    = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
	int      replace = 0;

	/* we found a possible candidate */
	replace = cand ? is_CondJmp_replacement(cand, irn) : 0;

	if (replace) {
		DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
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		DBG_OPT_CJMP(irn);
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		set_irn_op(irn, op_ia32_CJmpAM);
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		DB((cg->mod, LEVEL_1, "%+F\n", irn));
	}
}

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// only optimize up to 48 stores behind IncSPs
#define MAXPUSH_OPTIMIZE	48
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/**
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 * Tries to create pushs from IncSP,Store combinations
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 */
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static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
	int i;
	int offset;
	ir_node *node;
	ir_node *stores[MAXPUSH_OPTIMIZE];
	ir_node *block = get_nodes_block(irn);
	ir_graph *irg = cg->irg;
	ir_node *curr_sp;
	ir_mode *spmode = get_irn_mode(irn);

	memset(stores, 0, sizeof(stores));

	assert(be_is_IncSP(irn));

	offset = be_get_IncSP_offset(irn);
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	if(offset < 4)
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		return;

	/*
	 * We first walk the schedule after the IncSP node as long as we find
	 * suitable stores that could be transformed to a push.
	 * We save them into the stores array which is sorted by the frame offset/4
	 * attached to the node
	 */
	for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
		const char *am_offs;
		ir_node *mem;
		int offset = -1;
		int n;
		int storeslot;

		// it has to be a store
		if(!is_ia32_Store(node))
			break;

		// it has to use our sp value
		if(get_irn_n(node, 0) != irn)
			continue;
		// store has to be attached to NoMem
		mem = get_irn_n(node, 3);
		if(!is_NoMem(mem)) {
			continue;
		}

		if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
			break;

		am_offs = get_ia32_am_offs(node);
		if(am_offs == NULL) {
			offset = 0;
		} else {
			// the am_offs has to be of the form "+NUMBER"
			if(sscanf(am_offs, "+%d%n", &offset, &n) != 1 || am_offs[n] != '\0') {
				// we shouldn't have any cases in the compiler at the moment
				// that produce something different from esp+XX
				assert(0);
				break;
			}
		}

		storeslot = offset / 4;
		if(storeslot >= MAXPUSH_OPTIMIZE)
			continue;

		// storing into the same slot twice is bad (and shouldn't happen...)
		if(stores[storeslot] != NULL)
			break;

		// storing at half-slots is bad
		if(offset % 4 != 0)
			break;

		stores[storeslot] = node;
	}

	curr_sp = get_irn_n(irn, 0);

	// walk the stores in inverse order and create pushs for them
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	i = (offset / 4) - 1;
	if(i >= MAXPUSH_OPTIMIZE) {
		i = MAXPUSH_OPTIMIZE - 1;
	}

	for( ; i >= 0; --i) {
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		const ir_edge_t *edge, *next;
		const arch_register_t *spreg;
		ir_node *push;
		ir_node *val, *mem;
		ir_node *store = stores[i];

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		if(store == NULL || is_Bad(store))
			break;

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		val = get_irn_n(store, 2);
		mem = get_irn_n(store, 3);
		spreg = arch_get_irn_register(cg->arch_env, curr_sp);

		// create a push
		push = new_rd_ia32_Push(NULL, irg, block, curr_sp, val, mem);
		if(get_ia32_immop_type(store) != ia32_ImmNone) {
			copy_ia32_Immop_attr(push, store);
		}
		sched_add_before(irn, push);

		// create stackpointer proj
		curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
		arch_set_irn_register(cg->arch_env, curr_sp, spreg);
		sched_add_before(irn, curr_sp);

		// rewire memprojs of the store
		foreach_out_edge_safe(store, edge, next) {
			ir_node *succ = get_edge_src_irn(edge);

			assert(is_Proj(succ) && get_Proj_proj(succ) == pn_ia32_Store_M);
			set_irn_n(succ, 0, push);
		}

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		// we can remove the store now
		set_irn_n(store, 0, new_Bad());
		set_irn_n(store, 1, new_Bad());
		set_irn_n(store, 2, new_Bad());
		set_irn_n(store, 3, new_Bad());
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		sched_remove(store);
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		offset -= 4;
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	}

	be_set_IncSP_offset(irn, offset);

	// can we remove the IncSP now?
	if(offset == 0) {
		const ir_edge_t *edge, *next;

		foreach_out_edge_safe(irn, edge, next) {
			ir_node *arg = get_edge_src_irn(edge);
			int pos = get_edge_src_pos(edge);

			set_irn_n(arg, pos, curr_sp);
		}

		set_irn_n(irn, 0, new_Bad());
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		sched_remove(irn);
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	} else {
		set_irn_n(irn, 0, curr_sp);
	}
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}

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 * Tries to optimize two following IncSP.
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 */
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static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
	ir_node *prev = be_get_IncSP_pred(irn);
	int real_uses = get_irn_n_edges(prev);

	if (be_is_IncSP(prev) && real_uses == 1) {
		/* first IncSP has only one IncSP user, kill the first one */
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		int prev_offs = be_get_IncSP_offset(prev);
		int curr_offs = be_get_IncSP_offset(irn);
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		be_set_IncSP_offset(prev, prev_offs + curr_offs);
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		/* Omit the optimized IncSP */
		be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
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		set_irn_n(prev, 0, new_Bad());
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		sched_remove(prev);
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	}
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}

/**
 * Performs Peephole Optimizations.
 */
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static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
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	ia32_code_gen_t *cg = env;

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	/* AMD CPUs want explicit compare before conditional jump  */
	if (! ARCH_AMD(cg->opt_arch)) {
		if (is_ia32_TestJmp(irn))
			ia32_optimize_TestJmp(irn, cg);
		else if (is_ia32_CondJmp(irn))
			ia32_optimize_CondJmp(irn, cg);
	}
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	if (be_is_IncSP(irn)) {
		// optimize_IncSP doesn't respect dependency edges yet...
		//ia32_optimize_IncSP(irn, cg);
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		(void) ia32_optimize_IncSP;
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		ia32_create_Pushs(irn, cg);
	}
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}

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void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
	irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
}
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/******************************************************************
 *              _     _                   __  __           _
 *     /\      | |   | |                 |  \/  |         | |
 *    /  \   __| | __| |_ __ ___  ___ ___| \  / | ___   __| | ___
 *   / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
 *  / ____ \ (_| | (_| | | |  __/\__ \__ \ |  | | (_) | (_| |  __/
 * /_/    \_\__,_|\__,_|_|  \___||___/___/_|  |_|\___/ \__,_|\___|
 *
 ******************************************************************/

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typedef struct {
	ia32_code_gen_t *cg;
	heights_t       *h;
} ia32_am_opt_env_t;

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static int node_is_ia32_comm(const ir_node *irn) {
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	return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
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}

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static int ia32_get_irn_n_edges(const ir_node *irn) {
	const ir_edge_t *edge;
	int cnt = 0;

	foreach_out_edge(irn, edge) {
		cnt++;
	}

	return cnt;
}

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/**
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 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
 *
 * @param pred       The node to be checked
 * @param is_op_func The check-function
 * @return 1 if conditions are fulfilled, 0 otherwise
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 */
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static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
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	if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
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		return 1;
	}

	return 0;
}

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/**
 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
 * and if the predecessor is in block bl.
 *
 * @param bl         The block
 * @param pred       The node to be checked
 * @param is_op_func The check-function
 * @return 1 if conditions are fulfilled, 0 otherwise
 */
static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
	int (*is_op_func)(const ir_node *n))
{
	if (is_Proj(pred)) {
		pred = get_Proj_pred(pred);
		if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
			return 1;
		}
	}

	return 0;
}

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/**
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 * Checks if irn is a candidate for address calculation.
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 *
 * - none of the operand must be a Load  within the same block OR
 * - all Loads must have more than one user                    OR
 * - the irn has a frame entity (it's a former FrameAddr)
 *
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 * @param block   The block the Loads must/mustnot be in
 * @param irn     The irn to check
 * return 1 if irn is a candidate, 0 otherwise
 */
static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
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	ir_node *in, *left, *right;
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	int      n, is_cand = 1;

	left  = get_irn_n(irn, 2);
	right = get_irn_n(irn, 3);

	in = left;

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#ifndef AGGRESSIVE_AM
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	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
		n         = ia32_get_irn_n_edges(in);
		is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
	}

	in = right;

	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
		n         = ia32_get_irn_n_edges(in);
		is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
	}
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#endif
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	is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;

	return is_cand;
}

/**
 * Checks if irn is a candidate for address mode.
 *
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 * address mode (AM):
 * - at least one operand has to be a Load within the same block AND
 * - the load must not have other users than the irn             AND
 * - the irn must not have a frame entity set
 *
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 * @param h           The height information of the irg
 * @param block       The block the Loads must/mustnot be in
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 * @param irn         The irn to check
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 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
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 */
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static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
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	ir_node *in, *load, *other, *left, *right;
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	int      n, is_cand = 0, cand;
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	if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
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		is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
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		return 0;

	left  = get_irn_n(irn, 2);
	right = get_irn_n(irn, 3);

	in = left;
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	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
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#ifndef AGGRESSIVE_AM
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		n         = ia32_get_irn_n_edges(in);
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		is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
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#endif
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		load  = get_Proj_pred(in);
		other = right;

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		/* 8bit Loads are not supported, they cannot be used with every register */
		if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
			is_cand = 0;

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		/* If there is a data dependency of other irn from load: cannot use AM */
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		if (is_cand && get_nodes_block(other) == block) {
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			other   = skip_Proj(other);
			is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
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			/* this could happen in loops */
			is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
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		}
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	}

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	cand    = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
	in      = right;
	is_cand = 0;
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	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
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#ifndef AGGRESSIVE_AM
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		n         = ia32_get_irn_n_edges(in);
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		is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
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#endif
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		load  = get_Proj_pred(in);
		other = left;

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		/* 8bit Loads are not supported, they cannot be used with every register */
		if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
			is_cand = 0;

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		/* If there is a data dependency of other irn from load: cannot use load */
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		if (is_cand && get_nodes_block(other) == block) {
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			other   = skip_Proj(other);
			is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
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			/* this could happen in loops */
			is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
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		}
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	}

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	cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
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	/* check some special cases */
	if (USE_SSE2(cg) && is_ia32_Conv_I2FP(irn)) {
		/* SSE Conv I -> FP cvtsi2s(s|d) can only load 32 bit values */
		if (get_mode_size_bits(get_ia32_tgt_mode(irn)) != 32)
			cand = IA32_AM_CAND_NONE;
	}
	else if (is_ia32_Conv_I2I(irn)) {
		/* we cannot load an N bit value and implicitly convert it into an M bit value if N > M */
		if (get_mode_size_bits(get_ia32_src_mode(irn)) > get_mode_size_bits(get_ia32_tgt_mode(irn)))
			cand = IA32_AM_CAND_NONE;
	}

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	/* if the irn has a frame entity: we do not use address mode */
	return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
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}

/**
 * Compares the base and index addr and the load/store entities
 * and returns 1 if they are equal.
 */
static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
									const ir_node *addr_b, const ir_node *addr_i)
{
	int     is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
	entity *lent     = get_ia32_frame_ent(load);
	entity *sent     = get_ia32_frame_ent(store);
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	ident  *lid      = get_ia32_am_sc(load);
	ident  *sid      = get_ia32_am_sc(store);
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	char   *loffs    = get_ia32_am_offs(load);
	char   *soffs    = get_ia32_am_offs(store);
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	/* are both entities set and equal? */
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	if (is_equal && (lent || sent))
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		is_equal = lent && sent && (lent == sent);
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	/* are address mode idents set and equal? */
	if (is_equal && (lid || sid))
		is_equal = lid && sid && (lid == sid);
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	/* are offsets set and equal */
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	if (is_equal && (loffs || soffs))
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		is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;

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	/* are the load and the store of the same mode? */
	is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;

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	return is_equal;
}

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typedef enum _ia32_take_lea_attr {
	IA32_LEA_ATTR_NONE  = 0,
	IA32_LEA_ATTR_BASE  = (1 << 0),
	IA32_LEA_ATTR_INDEX = (1 << 1),
	IA32_LEA_ATTR_OFFS  = (1 << 2),
	IA32_LEA_ATTR_SCALE = (1 << 3),
	IA32_LEA_ATTR_AMSC  = (1 << 4),
	IA32_LEA_ATTR_FENT  = (1 << 5)
} ia32_take_lea_attr;

/**
 * Decides if we have to keep the LEA operand or if we can assimilate it.
 */
static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
		int have_am_sc, ia32_code_gen_t *cg)
{
	entity  *irn_ent  = get_ia32_frame_ent(irn);
	entity  *lea_ent  = get_ia32_frame_ent(lea);
	int      ret_val  = 0;
	int      is_noreg_base  = be_is_NoReg(cg, base);
	int      is_noreg_index = be_is_NoReg(cg, index);
	ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);

	/* If the Add and the LEA both have a different frame entity set: keep */
	if (irn_ent && lea_ent && (irn_ent != lea_ent))
		return IA32_LEA_ATTR_NONE;
	else if (! irn_ent && lea_ent)
		ret_val |= IA32_LEA_ATTR_FENT;

	/* If the Add and the LEA both have already an address mode symconst: keep */
	if (have_am_sc && get_ia32_am_sc(lea))
		return IA32_LEA_ATTR_NONE;
	else if (get_ia32_am_sc(lea))
		ret_val |= IA32_LEA_ATTR_AMSC;

	/* Check the different base-index combinations */

	if (! is_noreg_base && ! is_noreg_index) {
		/* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
		if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
			if (am_flav & ia32_O)
				ret_val |= IA32_LEA_ATTR_OFFS;

			ret_val |= IA32_LEA_ATTR_BASE;
		}
		else
			return IA32_LEA_ATTR_NONE;
	}
	else if (! is_noreg_base && is_noreg_index) {
		/* Base is set but index not */
		if (base == lea) {
			/* Base points to LEA: assimilate everything */
			if (am_flav & ia32_O)
				ret_val |= IA32_LEA_ATTR_OFFS;
			if (am_flav & ia32_S)
				ret_val |= IA32_LEA_ATTR_SCALE;
			if (am_flav & ia32_I)
				ret_val |= IA32_LEA_ATTR_INDEX;

			ret_val |= IA32_LEA_ATTR_BASE;
		}
		else if (am_flav & ia32_B ? 0 : 1) {
			/* Base is not the LEA but the LEA is an index only calculation: assimilate */
			if (am_flav & ia32_O)
				ret_val |= IA32_LEA_ATTR_OFFS;
			if (am_flav & ia32_S)
				ret_val |= IA32_LEA_ATTR_SCALE;

			ret_val |= IA32_LEA_ATTR_INDEX;
		}
		else
			return IA32_LEA_ATTR_NONE;
	}
	else if (is_noreg_base && ! is_noreg_index) {
		/* Index is set but not base */
		if (index == lea) {
			/* Index points to LEA: assimilate everything */
			if (am_flav & ia32_O)
				ret_val |= IA32_LEA_ATTR_OFFS;
			if (am_flav & ia32_S)
				ret_val |= IA32_LEA_ATTR_SCALE;
			if (am_flav & ia32_B)
				ret_val |= IA32_LEA_ATTR_BASE;

			ret_val |= IA32_LEA_ATTR_INDEX;
		}
		else if (am_flav & ia32_I ? 0 : 1) {
			/* Index is not the LEA but the LEA is a base only calculation: assimilate */
			if (am_flav & ia32_O)
				ret_val |= IA32_LEA_ATTR_OFFS;
			if (am_flav & ia32_S)
				ret_val |= IA32_LEA_ATTR_SCALE;

			ret_val |= IA32_LEA_ATTR_BASE;
		}
		else
			return IA32_LEA_ATTR_NONE;
	}
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