ia32_emitter.c 67.6 KB
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/**
 * This file implements the node emitter.
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 * @author Christian Wuerdig
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 * $Id$
 */

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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

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#include <limits.h>

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#include "xmalloc.h"
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#include "tv.h"
#include "iredges.h"
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#include "debug.h"
#include "irgwalk.h"
#include "irprintf.h"
#include "irop_t.h"
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#include "irargs_t.h"
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#include "irprog_t.h"
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#include "iredges_t.h"
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#include "execfreq.h"
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#include "../besched_t.h"
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#include "../benode_t.h"
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#include "../beabi.h"
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#include "../be_dbgout.h"
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#include "ia32_emitter.h"
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#include "gen_ia32_emitter.h"
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#include "gen_ia32_regalloc_if.h"
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#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
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#include "ia32_map_regs.h"
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#include "bearch_ia32_t.h"
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#define BLOCK_PREFIX(x) ".L" x
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#define SNPRINTF_BUF_LEN 128

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/* global arch_env for lc_printf functions */
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static const arch_env_t *arch_env = NULL;
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/** by default, we generate assembler code for the Linux gas */
asm_flavour_t asm_flavour = ASM_LINUX_GAS;

/**
 * Switch to a new section
 */
void ia32_switch_section(FILE *F, section_t sec) {
	static section_t curr_sec = NO_SECTION;
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	static const char *text[ASM_MAX][SECTION_MAX] = {
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		{
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			".section\t.text",
			".section\t.data",
			".section\t.rodata",
			".section\t.text",
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			".section\t.tbss,\"awT\",@nobits",
			".section\t.ctors,\"aw\",@progbits"
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		},
		{
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			".section\t.text",
			".section\t.data",
			".section .rdata,\"dr\"",
			".section\t.text",
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			".section\t.tbss,\"awT\",@nobits",
			".section\t.ctors,\"aw\",@progbits"
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		}
	};

	if (curr_sec == sec)
		return;

	curr_sec = sec;
	switch (sec) {

	case NO_SECTION:
		break;

	case SECTION_TEXT:
	case SECTION_DATA:
	case SECTION_RODATA:
	case SECTION_COMMON:
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	case SECTION_TLS:
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	case SECTION_CTOR:
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		fprintf(F, "\t%s\n", text[asm_flavour][sec]);
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		break;

	default:
		break;
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	}
}

static void ia32_dump_function_object(FILE *F, const char *name)
{
	switch (asm_flavour) {
	case ASM_LINUX_GAS:
		fprintf(F, "\t.type\t%s, @function\n", name);
		break;
	case ASM_MINGW_GAS:
		fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
		break;
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	default:
		break;
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	}
}

static void ia32_dump_function_size(FILE *F, const char *name)
{
	switch (asm_flavour) {
	case ASM_LINUX_GAS:
		fprintf(F, "\t.size\t%s, .-%s\n", name, name);
		break;
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	default:
		break;
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	}
}

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/*************************************************************
 *             _       _    __   _          _
 *            (_)     | |  / _| | |        | |
 *  _ __  _ __ _ _ __ | |_| |_  | |__   ___| |_ __   ___ _ __
 * | '_ \| '__| | '_ \| __|  _| | '_ \ / _ \ | '_ \ / _ \ '__|
 * | |_) | |  | | | | | |_| |   | | | |  __/ | |_) |  __/ |
 * | .__/|_|  |_|_| |_|\__|_|   |_| |_|\___|_| .__/ \___|_|
 * | |                                       | |
 * |_|                                       |_|
 *************************************************************/

/* We always pass the ir_node which is a pointer. */
static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
	return lc_arg_type_ptr;
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}

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/**
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 * Returns the register at in position pos.
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 */
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static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
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	ir_node                *op;
	const arch_register_t  *reg = NULL;

	assert(get_irn_arity(irn) > pos && "Invalid IN position");

	/* The out register of the operator at position pos is the
	   in register we need. */
	op = get_irn_n(irn, pos);

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	reg = arch_get_irn_register(arch_env, op);
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	assert(reg && "no in register found");
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	/* in case of a joker register: just return a valid register */
	if (arch_register_type_is(reg, joker)) {
		arch_register_req_t       req;
		const arch_register_req_t *p_req;

		/* ask for the requirements */
		p_req = arch_get_register_req(arch_env, &req, irn, pos);

		if (arch_register_req_is(p_req, limited)) {
			/* in case of limited requirements: get the first allowed register */

			bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
			int      idx;

			p_req->limited(p_req->limited_env, bs);
			idx = bitset_next_set(bs, 0);
			reg = arch_register_for_index(p_req->cls, idx);
		}
		else {
			/* otherwise get first register in class */
			reg = arch_register_for_index(p_req->cls, 0);
		}
	}
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	return reg;
}

/**
 * Returns the register at out position pos.
 */
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static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
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	ir_node                *proj;
	const arch_register_t  *reg = NULL;

	/* 1st case: irn is not of mode_T, so it has only                 */
	/*           one OUT register -> good                             */
	/* 2nd case: irn is of mode_T -> collect all Projs and ask the    */
	/*           Proj with the corresponding projnum for the register */

	if (get_irn_mode(irn) != mode_T) {
		reg = arch_get_irn_register(arch_env, irn);
	}
	else if (is_ia32_irn(irn)) {
		reg = get_ia32_out_reg(irn, pos);
	}
	else {
		const ir_edge_t *edge;

		foreach_out_edge(irn, edge) {
			proj = get_edge_src_irn(edge);
			assert(is_Proj(proj) && "non-Proj from mode_T node");
			if (get_Proj_proj(proj) == pos) {
				reg = arch_get_irn_register(arch_env, proj);
				break;
			}
		}
	}

	assert(reg && "no out register found");
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	return reg;
}

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enum io_direction {
  IN_REG,
  OUT_REG
};

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/**
 * Returns the name of the in register at position pos.
 */
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static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
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	const arch_register_t *reg;

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	if (in_out == IN_REG) {
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		reg = get_in_reg(irn, pos);
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		if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
			/* FIXME: works for binop only */
			assert(2 <= pos && pos <= 3);
			reg = get_ia32_attr(irn)->x87[pos - 2];
		}
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	}
	else {
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		/* destination address mode nodes don't have outputs */
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		if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
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			return "MEM";
		}

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		reg = get_out_reg(irn, pos);
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		if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
			reg = get_ia32_attr(irn)->x87[pos + 2];
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	}
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	return arch_register_get_name(reg);
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}

/**
 * Get the register name for a node.
 */
static int ia32_get_reg_name(lc_appendable_t *app,
    const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
	const char *buf;
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	ir_node    *irn = arg->v_ptr;
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	int         nr = occ->width - 1;

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	if (! irn)
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		return lc_appendable_snadd(app, "(null)", 6);
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	buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
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	/* append the stupid % to register names */
	lc_appendable_chadd(app, '%');
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	return lc_appendable_snadd(app, buf, strlen(buf));
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}

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/**
 * Get the x87 register name for a node.
 */
static int ia32_get_x87_name(lc_appendable_t *app,
    const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
	const char *buf;
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	ir_node     *irn = arg->v_ptr;
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	int         nr = occ->width - 1;
	ia32_attr_t *attr;

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	if (! irn)
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		return lc_appendable_snadd(app, "(null)", 6);

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	attr = get_ia32_attr(irn);
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	buf = attr->x87[nr]->name;
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	lc_appendable_chadd(app, '%');
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	return lc_appendable_snadd(app, buf, strlen(buf));
}

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/**
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 * Returns the tarval, offset or scale of an ia32 as a string.
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 */
static int ia32_const_to_str(lc_appendable_t *app,
    const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
	const char *buf;
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	ir_node    *irn = arg->v_ptr;
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	if (! irn)
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		return lc_arg_append(app, occ, "(null)", 6);

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	if (occ->conversion == 'C') {
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		buf = get_ia32_cnst(irn);
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	}
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	else { /* 'O' */
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		buf = get_ia32_am_offs(irn);
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	}

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	return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
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}

/**
 * Determines the SSE suffix depending on the mode.
 */
static int ia32_get_mode_suffix(lc_appendable_t *app,
    const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
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	ir_node *irn  = arg->v_ptr;
	ir_mode *mode = get_irn_mode(irn);
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	if (mode == mode_T) {
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		mode = get_ia32_res_mode(irn);
		if (! mode)
			mode = get_ia32_ls_mode(irn);
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	}
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	if (! irn)
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		return lc_arg_append(app, occ, "(null)", 6);

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	if (mode_is_float(mode)) {
		return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
	}
	else {
		return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
	}
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}

/**
 * Return the ia32 printf arg environment.
 * We use the firm environment with some additional handlers.
 */
const lc_arg_env_t *ia32_get_arg_env(void) {
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	static lc_arg_env_t *env = NULL;
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	static const lc_arg_handler_t ia32_reg_handler   = { ia32_get_arg_type, ia32_get_reg_name };
	static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
	static const lc_arg_handler_t ia32_mode_handler  = { ia32_get_arg_type, ia32_get_mode_suffix };
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	static const lc_arg_handler_t ia32_x87_handler   = { ia32_get_arg_type, ia32_get_x87_name };
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	if(env == NULL) {
		/* extend the firm printer */
		env = firm_get_arg_env();
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		lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
		lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
		lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
		lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
		lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
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		lc_arg_register(env, "ia32:x87",  'X', &ia32_x87_handler);
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	}
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	return env;
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}

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static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
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	switch(get_mode_size_bits(mode)) {
		case 8:
			return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
		case 16:
			return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
		default:
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			return (char *)arch_register_get_name(reg);
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	}
}

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/**
 * Emits registers and/or address mode of a binary operation.
 */
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const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
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	static char *buf = NULL;
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	/* verify that this function is never called on non-AM supporting operations */
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	//assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
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#define PRODUCES_RESULT(n)   \
	(!(is_ia32_St(n)      || \
	is_ia32_Store8Bit(n)  || \
	is_ia32_CondJmp(n)    || \
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	is_ia32_xCondJmp(n)   || \
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	is_ia32_CmpSet(n)     || \
	is_ia32_xCmpSet(n)    || \
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	is_ia32_SwitchJmp(n)))
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	if (! buf) {
		buf = xcalloc(1, SNPRINTF_BUF_LEN);
	}
	else {
		memset(buf, 0, SNPRINTF_BUF_LEN);
	}

	switch(get_ia32_op_type(n)) {
		case ia32_Normal:
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			if (is_ia32_ImmConst(n)) {
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				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
			}
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			else if (is_ia32_ImmSymConst(n)) {
				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
			}
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			else {
				const arch_register_t *in1 = get_in_reg(n, 2);
				const arch_register_t *in2 = get_in_reg(n, 3);
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				const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
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				const arch_register_t *in;
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				const char            *in_name;
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				in      = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
				out     = out ? out : in1;
				in_name = arch_register_get_name(in);
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				if (is_ia32_emit_cl(n)) {
					assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
					in_name = "cl";
				}

				snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
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			}
			break;
		case ia32_AddrModeS:
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			if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
				assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
				snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
			}
			else {
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				if (PRODUCES_RESULT(n)) {
					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
				}
				else {
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					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
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				}
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			}
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			break;
		case ia32_AddrModeD:
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			if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
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				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
					ia32_emit_am(n, env),
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					is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ",  /* In case of a symconst we must add OFFSET to */
					get_ia32_cnst(n));                               /* tell the assembler to store it's address.   */
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			}
			else {
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				const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
				ir_mode               *mode = get_ia32_res_mode(n);
				const char            *in_name;
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				mode    = mode ? mode : get_ia32_ls_mode(n);
				in_name = ia32_get_reg_name_for_mode(env, mode, in1);

				if (is_ia32_emit_cl(n)) {
					assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
					in_name = "cl";
				}
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				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
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			}
			break;
		default:
			assert(0 && "unsupported op type");
	}

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#undef PRODUCES_RESULT

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	return buf;
}

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/**
 * Returns the xxx PTR string for a given mode
 *
 * @param mode      the mode
 * @param x87_insn  if non-zero returns the string for a x87 instruction
 *                  else for a SSE instruction
 */
static const char *pointer_size(ir_mode *mode, int x87_insn)
{
	if (mode) {
		switch (get_mode_size_bits(mode)) {
		case 8:  return "BYTE PTR";
		case 16: return "WORD PTR";
		case 32: return "DWORD PTR";
		case 64:
			if (x87_insn)
				return "QWORD PTR";
			return NULL;
		case 80:
		case 96: return "XWORD PTR";
		default: return NULL;
		}
	}
	return NULL;
}

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/**
 * Emits registers and/or address mode of a binary operation.
 */
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const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
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	static char *buf = NULL;

	/* verify that this function is never called on non-AM supporting operations */
	//assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");

	if (! buf) {
		buf = xcalloc(1, SNPRINTF_BUF_LEN);
	}
	else {
		memset(buf, 0, SNPRINTF_BUF_LEN);
	}

	switch(get_ia32_op_type(n)) {
		case ia32_Normal:
			if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
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				ir_mode *mode = get_ia32_ls_mode(n);
				const char *p = pointer_size(mode, 1);
				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
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			}
			else {
				ia32_attr_t *attr = get_ia32_attr(n);
				const arch_register_t *in1 = attr->x87[0];
				const arch_register_t *in2 = attr->x87[1];
				const arch_register_t *out = attr->x87[2];
				const arch_register_t *in;
				const char            *in_name;

				in      = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
				out     = out ? out : in1;
				in_name = arch_register_get_name(in);

				snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
			}
			break;
		case ia32_AddrModeS:
		case ia32_AddrModeD:
			lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
			break;
		default:
			assert(0 && "unsupported op type");
	}

	return buf;
}

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/**
 * Emits registers and/or address mode of a unary operation.
 */
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const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
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	static char *buf = NULL;

	if (! buf) {
		buf = xcalloc(1, SNPRINTF_BUF_LEN);
	}
	else {
		memset(buf, 0, SNPRINTF_BUF_LEN);
	}

	switch(get_ia32_op_type(n)) {
		case ia32_Normal:
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			if (is_ia32_ImmConst(n)) {
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				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
			}
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			else if (is_ia32_ImmSymConst(n)) {
				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
			}
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			else {
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				if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
					/* MulS and Mulh implicitly multiply by EAX */
					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
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				} else if(is_ia32_Push(n)) {
					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
				} else {
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					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
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				}
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			}
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			break;
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		case ia32_AddrModeD:
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			assert(!is_ia32_Push(n));
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			snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
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			break;
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		case ia32_AddrModeS:
			/*
				Mulh is emitted via emit_unop
				imul [MEM]  means EDX:EAX <- EAX * [MEM]
			*/
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			assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
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			lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
			break;
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		default:
			assert(0 && "unsupported op type");
	}

	return buf;
}

/**
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 * Emits address mode.
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 */
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const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
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	ia32_am_flavour_t am_flav    = get_ia32_am_flavour(n);
	int               had_output = 0;
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	char              *s;
	const char        *p;
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	static struct obstack *obst  = NULL;
	ir_mode *mode = get_ia32_ls_mode(n);

	if (! is_ia32_Lea(n))
		assert(mode && "AM node must have ls_mode attribute set.");

	if (! obst) {
		obst = xcalloc(1, sizeof(*obst));
	}
	else {
		obstack_free(obst, NULL);
	}

	/* obstack_free with NULL results in an uninitialized obstack */
	obstack_init(obst);

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	p = pointer_size(mode, ia32_has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
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	if (p)
		obstack_printf(obst, "%s ", p);
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	/* emit address mode symconst */
	if (get_ia32_am_sc(n)) {
		if (is_ia32_am_sc_sign(n))
			obstack_printf(obst, "-");
		obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
	}
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	if (am_flav & ia32_B) {
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		obstack_printf(obst, "[");
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		lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
		had_output = 1;
	}

	if (am_flav & ia32_I) {
		if (had_output) {
			obstack_printf(obst, "+");
		}
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		else {
			obstack_printf(obst, "[");
		}
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		lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);

		if (am_flav & ia32_S) {
			obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
		}

		had_output = 1;
	}

	if (am_flav & ia32_O) {
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		int offs = get_ia32_am_offs_int(n);
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		if (offs != 0) {
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			/* omit explicit + if there was no base or index */
			if (! had_output) {
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				obstack_printf(obst, "[%d", offs);
			} else {
				obstack_printf(obst, "%+d", offs);
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			}
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			had_output = 1;
		}
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	}

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	if (had_output)
		obstack_printf(obst, "] ");
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	obstack_1grow(obst, '\0');
	s = obstack_finish(obst);
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	return s;
}

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/**
 * emit an address
 */
const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
{
	static char buf[SNPRINTF_BUF_LEN];
	ir_mode    *mode = get_ia32_ls_mode(irn);
	const char *adr  = get_ia32_cnst(irn);
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	const char *pref = pointer_size(mode, ia32_has_x87_register(irn));
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	snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
	return buf;
}
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/**
 * Formated print of commands and comments.
 */
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static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
	unsigned lineno;
	const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;

	if (name)
		fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
	else
		fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
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}



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/**
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 * Add a number to a prefix. This number will not be used a second time.
 */
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static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
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	static unsigned long id = 0;
	snprintf(buf, buflen, "%s%lu", prefix, ++id);
	return buf;
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}

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/*************************************************
 *                 _ _                         _
 *                (_) |                       | |
 *   ___ _ __ ___  _| |_    ___ ___  _ __   __| |
 *  / _ \ '_ ` _ \| | __|  / __/ _ \| '_ \ / _` |
 * |  __/ | | | | | | |_  | (_| (_) | | | | (_| |
 *  \___|_| |_| |_|_|\__|  \___\___/|_| |_|\__,_|
 *
 *************************************************/

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#undef IA32_DO_EMIT
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#define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
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/*
 * coding of conditions
 */
struct cmp2conditon_t {
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	const char *name;
	pn_Cmp      num;
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};

/*
 * positive conditions for signed compares
 */
static const struct cmp2conditon_t cmp2condition_s[] = {
  { NULL,              pn_Cmp_False },  /* always false */
  { "e",               pn_Cmp_Eq },     /* == */
  { "l",               pn_Cmp_Lt },     /* < */
  { "le",              pn_Cmp_Le },     /* <= */
  { "g",               pn_Cmp_Gt },     /* > */
  { "ge",              pn_Cmp_Ge },     /* >= */
  { "ne",              pn_Cmp_Lg },     /* != */
  { "ordered",         pn_Cmp_Leg },    /* Floating point: ordered */
  { "unordered",       pn_Cmp_Uo },     /* FLoting point: unordered */
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  { "e",               pn_Cmp_Ue },     /* Floating point: unordered or == */
  { "b",               pn_Cmp_Ul },     /* Floating point: unordered or < */
  { "be",              pn_Cmp_Ule },    /* Floating point: unordered or <= */
  { "a",               pn_Cmp_Ug },     /* Floating point: unordered or > */
  { "ae",              pn_Cmp_Uge },    /* Floating point: unordered or >= */
  { "ne",              pn_Cmp_Ne },     /* Floating point: unordered or != */
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  { NULL,              pn_Cmp_True },   /* always true */
};

/*
 * positive conditions for unsigned compares
 */
static const struct cmp2conditon_t cmp2condition_u[] = {
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	{ NULL,              pn_Cmp_False },  /* always false */
	{ "e",               pn_Cmp_Eq },     /* == */
	{ "b",               pn_Cmp_Lt },     /* < */
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	{ "be",              pn_Cmp_Le },     /* <= */
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	{ "a",               pn_Cmp_Gt },     /* > */
	{ "ae",              pn_Cmp_Ge },     /* >= */
	{ "ne",              pn_Cmp_Lg },     /* != */
	{ "ordered",         pn_Cmp_Leg },    /* Floating point: ordered */
	{ "unordered",       pn_Cmp_Uo },     /* FLoting point: unordered */
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	{ "e",               pn_Cmp_Ue },     /* Floating point: unordered or == */
	{ "b",               pn_Cmp_Ul },     /* Floating point: unordered or < */
	{ "be",              pn_Cmp_Ule },    /* Floating point: unordered or <= */
	{ "a",               pn_Cmp_Ug },     /* Floating point: unordered or > */
	{ "ae",              pn_Cmp_Uge },    /* Floating point: unordered or >= */
	{ "ne",              pn_Cmp_Ne },     /* Floating point: unordered or != */
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	{ NULL,              pn_Cmp_True },   /* always true */
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};

/*
 * returns the condition code
 */
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static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
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{
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	assert(cmp2condition_s[cmp_code].num == cmp_code);
	assert(cmp2condition_u[cmp_code].num == cmp_code);
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	return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
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}

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/**
 * Returns the target block for a control flow node.
 */
static ir_node *get_cfop_target_block(const ir_node *irn) {
	return get_irn_link(irn);
}

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/**
 * Returns the target label for a control flow node.
 */
static char *get_cfop_target(const ir_node *irn, char *buf) {
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	ir_node *bl = get_cfop_target_block(irn);
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	snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
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	return buf;
}
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/** Return the next block in Block schedule */
static ir_node *next_blk_sched(const ir_node *block) {
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	return get_irn_link(block);
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}

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/**
 * Returns the Proj with projection number proj and NOT mode_M
 */
static ir_node *get_proj(const ir_node *irn, long proj) {
	const ir_edge_t *edge;
	ir_node         *src;

	assert(get_irn_mode(irn) == mode_T && "expected mode_T node");

	foreach_out_edge(irn, edge) {
		src = get_edge_src_irn(edge);

		assert(is_Proj(src) && "Proj expected");
		if (get_irn_mode(src) == mode_M)
			continue;

		if (get_Proj_proj(src) == proj)
			return src;
	}
	return NULL;
}

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/**
 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
 */
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static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
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	const ir_node *proj_true;
	const ir_node *proj_false;
	const ir_node *block;
	const ir_node *next_block;
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	char buf[SNPRINTF_BUF_LEN];
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	char cmd_buf[SNPRINTF_BUF_LEN];
	char cmnt_buf[SNPRINTF_BUF_LEN];
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	int is_unsigned;
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	int pnc;
	int flipped = 0;
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	/* get both Proj's */
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	proj_true = get_proj(irn, pn_Cond_true);
	assert(proj_true && "CondJmp without true Proj");
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	proj_false = get_proj(irn, pn_Cond_false);
	assert(proj_false && "CondJmp without false Proj");

	pnc = get_ia32_pncode(irn);
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	/* for now, the code works for scheduled and non-schedules blocks */
	block = get_nodes_block(irn);
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	/* we have a block schedule */
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	next_block = next_blk_sched(block);
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	if (get_cfop_target_block(proj_true) == next_block) {
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		/* exchange both proj's so the second one can be omitted */
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		const ir_node *t = proj_true;
		proj_true = proj_false;
		proj_false = t;

		flipped = 1;
		pnc = get_negated_pnc(pnc, mode);
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	}

	/* the first Proj must always be created */
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	is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
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	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
	         get_cmp_suffix(pnc, is_unsigned),
	         get_cfop_target(proj_true, buf));
	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
	         get_pnc_string(pnc), flipped ? "(was flipped)" : "");
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	IA32_DO_EMIT(irn);
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	/* the second Proj might be a fallthrough */
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	if (get_cfop_target_block(proj_false) != next_block) {
		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
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		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
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	}
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	else {
		cmd_buf[0] = '\0';
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		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
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	}
	IA32_DO_EMIT(irn);
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}

/**
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 * Emits code for conditional jump.
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 */
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static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
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	FILE *F = env->out;
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	char cmd_buf[SNPRINTF_BUF_LEN];
	char cmnt_buf[SNPRINTF_BUF_LEN];
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	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
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	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
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	IA32_DO_EMIT(irn);
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	finish_CondJmp(F, irn, get_ia32_res_mode(irn));
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}

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/**
 * Emits code for conditional jump with two variables.
 */
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static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
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	CondJmp_emitter(irn, env);
}

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/**
 * Emits code for conditional test and jump.
 */
static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
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#define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))

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	FILE       *F   = env->out;
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	const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
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	const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
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	char        cmd_buf[SNPRINTF_BUF_LEN];
	char        cmnt_buf[SNPRINTF_BUF_LEN];
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	if (! op2)
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		op2 = arch_register_get_name(get_in_reg(irn, 1));
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	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
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	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
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	IA32_DO_EMIT(irn);
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	finish_CondJmp(F, irn, get_ia32_res_mode(irn));
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#undef IA32_IS_IMMOP
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}

/**
 * Emits code for conditional test and jump with two variables.
 */
static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
	TestJmp_emitter(irn, env);
}

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static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
	FILE *F = env->out;
	char cmd_buf[SNPRINTF_BUF_LEN];
	char cmnt_buf[SNPRINTF_BUF_LEN];

	snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
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	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
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	IA32_DO_EMIT(irn);
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	finish_CondJmp(F, irn, get_ia32_res_mode(irn));
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}
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static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
	FILE *F = env->out;
	char cmd_buf[SNPRINTF_BUF_LEN];
	char cmnt_buf[SNPRINTF_BUF_LEN];

	snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
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	IA32_DO_EMIT(irn);
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	finish_CondJmp(F, irn, get_ia32_res_mode(irn));
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}
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/**
 * Emits code for conditional SSE floating point jump with two variables.
 */
static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
	FILE *F = env->out;
	char cmd_buf[SNPRINTF_BUF_LEN];
	char cmnt_buf[SNPRINTF_BUF_LEN];

	lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
	IA32_DO_EMIT(irn);
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	finish_CondJmp(F, irn, mode_F);
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}

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/**
 * Emits code for conditional x87 floating point jump with two variables.
 */
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static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
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	FILE *F = env->out;
	char cmd_buf[SNPRINTF_BUF_LEN];
	char cmnt_buf[SNPRINTF_BUF_LEN];
	ia32_attr_t *attr = get_ia32_attr(irn);
	const char *reg = attr->x87[1]->name;
	const char *instr = "fcom";
	int reverse = 0;

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	switch (get_ia32_irn_opcode(irn)) {
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	case iro_ia32_fcomrJmp:
		reverse = 1;
	case iro_ia32_fcomJmp:
	default:
		instr = "fucom";
		break;
	case iro_ia32_fcomrpJmp:
		reverse = 1;
	case iro_ia32_fcompJmp:
		instr = "fucomp";
		break;
	case iro_ia32_fcomrppJmp:
		reverse = 1;
	case iro_ia32_fcomppJmp:
		instr = "fucompp";
		reg = "";
		break;
	}

	if (reverse)
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		set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
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	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
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	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
	IA32_DO_EMIT(irn);
	lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
	IA32_DO_EMIT(irn);
	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
	IA32_DO_EMIT(irn);

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	/* the compare flags must be evaluated using carry , ie unsigned */
	finish_CondJmp(F, irn, mode_Iu);
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}

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static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
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	FILE               *F       = env->out;
	const lc_arg_env_t *arg_env = ia32_get_arg_env();
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	ir_mode    *mode       = get_irn_mode(get_irn_n(irn, 0));
	int        is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
	const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
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	int is_PsiCondCMov     = is_ia32_PsiCondCMov(irn);
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	int idx_left  = 2 - is_PsiCondCMov;
	int idx_right = 3 - is_PsiCondCMov;
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	char cmd_buf[SNPRINTF_BUF_LEN];
	char cmnt_buf[SNPRINTF_BUF_LEN];
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	const arch_register_t *in1, *in2, *out;

	out = arch_get_irn_register(env->arch_env, irn);
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	in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
	in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
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	/* we have to emit the cmp first, because the destination register */
	/* could be one of the compare registers                           */
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	if (is_ia32_CmpCMov(irn)) {
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		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
	}
	else if (is_ia32_xCmpCMov(irn)) {
		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
	}
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	else if (is_PsiCondCMov) {
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		/* omit compare because flags are already set by And/Or */
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		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
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	}
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	else {
		assert(0 && "unsupported CMov");
	}
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	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
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	IA32_DO_EMIT(irn);

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	if (REGS_ARE_EQUAL(out, in2)) {
		/* best case: default in == out -> do nothing */
	}
	else if (REGS_ARE_EQUAL(out, in1)) {
		/* true in == out -> need complement compare and exchange true and default in */
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		ir_node *t = get_irn_n(irn, idx_left);
		set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
		set_irn_n(irn, idx_right, t);
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		cmp_suffix  = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
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	}
	else {
		/* out is different from in: need copy default -> out */
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		if (is_PsiCondCMov)
			lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
		else
			lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);

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		lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
		IA32_DO_EMIT(irn);
	}
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	if (is_PsiCondCMov)
		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
	else
		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);

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	lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
	IA32_DO_EMIT(irn);
}