ia32_emitter.c 52.5 KB
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/*
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 * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
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 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

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/**
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 * @file
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 * @brief       This file implements the ia32 node emitter.
 * @author      Christian Wuerdig, Matthias Braun
 * @version     $Id$
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 */
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif

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#include <limits.h>

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#include "xmalloc.h"
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#include "tv.h"
#include "iredges.h"
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#include "debug.h"
#include "irgwalk.h"
#include "irprintf.h"
#include "irop_t.h"
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#include "irargs_t.h"
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#include "irprog_t.h"
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#include "iredges_t.h"
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#include "execfreq.h"
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#include "error.h"
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#include "raw_bitset.h"
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#include "dbginfo.h"
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#include "../besched_t.h"
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#include "../benode_t.h"
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#include "../beabi.h"
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#include "../be_dbgout.h"
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#include "../beemitter.h"
#include "../begnuas.h"
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#include "../beirg_t.h"
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#include "../be_dbgout.h"
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#include "ia32_emitter.h"
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#include "gen_ia32_emitter.h"
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#include "gen_ia32_regalloc_if.h"
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#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
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#include "ia32_map_regs.h"
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#include "ia32_architecture.h"
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#include "bearch_ia32_t.h"
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DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

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#define BLOCK_PREFIX ".L"
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#define SNPRINTF_BUF_LEN 128

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static const arch_env_t *arch_env;
static const ia32_isa_t *isa;
static ia32_code_gen_t  *cg;
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static int               do_pic;
static char              pic_base_label[128];
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static ir_label_t        exc_label_id;
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static int               mark_spill_reload = 0;
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/** Return the next block in Block schedule */
static ir_node *get_prev_block_sched(const ir_node *block)
{
	return get_irn_link(block);
}

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static int is_fallthrough(const ir_node *cfgpred)
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{
	ir_node *pred;

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	if (!is_Proj(cfgpred))
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		return 1;
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	pred = get_Proj_pred(cfgpred);
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	if (is_ia32_SwitchJmp(pred))
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		return 0;
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	return 1;
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}

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static int block_needs_label(const ir_node *block)
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{
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	int need_label = 1;
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	int  n_cfgpreds = get_Block_n_cfgpreds(block);

	if (n_cfgpreds == 0) {
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		need_label = 0;
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	} else if (n_cfgpreds == 1) {
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		ir_node *cfgpred       = get_Block_cfgpred(block, 0);
		ir_node *cfgpred_block = get_nodes_block(cfgpred);
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		if (get_prev_block_sched(block) == cfgpred_block
				&& is_fallthrough(cfgpred)) {
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			need_label = 0;
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		}
	}

	return need_label;
}

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/**
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 * Returns the register at in position pos.
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 */
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static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
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{
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	ir_node               *op;
	const arch_register_t *reg = NULL;
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	assert(get_irn_arity(irn) > pos && "Invalid IN position");

	/* The out register of the operator at position pos is the
	   in register we need. */
	op = get_irn_n(irn, pos);

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	reg = arch_get_irn_register(arch_env, op);
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	assert(reg && "no in register found");
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	if (reg == &ia32_gp_regs[REG_GP_NOREG])
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		panic("trying to emit noreg for %+F input %d", irn, pos);
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	/* in case of unknown register: just return a valid register */
	if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
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		const arch_register_req_t *req;
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		/* ask for the requirements */
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		req = arch_get_register_req(arch_env, irn, pos);
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		if (arch_register_req_is(req, limited)) {
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			/* in case of limited requirements: get the first allowed register */
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			unsigned idx = rbitset_next(req->limited, 0, 1);
			reg = arch_register_for_index(req->cls, idx);
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		} else {
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			/* otherwise get first register in class */
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			reg = arch_register_for_index(req->cls, 0);
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		}
	}
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	return reg;
}

/**
 * Returns the register at out position pos.
 */
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static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
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{
	ir_node               *proj;
	const arch_register_t *reg = NULL;
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	/* 1st case: irn is not of mode_T, so it has only                 */
	/*           one OUT register -> good                             */
	/* 2nd case: irn is of mode_T -> collect all Projs and ask the    */
	/*           Proj with the corresponding projnum for the register */

	if (get_irn_mode(irn) != mode_T) {
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		assert(pos == 0);
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		reg = arch_get_irn_register(arch_env, irn);
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	} else if (is_ia32_irn(irn)) {
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		reg = get_ia32_out_reg(irn, pos);
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	} else {
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		const ir_edge_t *edge;

		foreach_out_edge(irn, edge) {
			proj = get_edge_src_irn(edge);
			assert(is_Proj(proj) && "non-Proj from mode_T node");
			if (get_Proj_proj(proj) == pos) {
				reg = arch_get_irn_register(arch_env, proj);
				break;
			}
		}
	}

	assert(reg && "no out register found");
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	return reg;
}

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/**
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 * Add a number to a prefix. This number will not be used a second time.
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 */
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static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
{
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	static unsigned long id = 0;
	snprintf(buf, buflen, "%s%lu", prefix, ++id);
	return buf;
}

/*************************************************************
 *             _       _    __   _          _
 *            (_)     | |  / _| | |        | |
 *  _ __  _ __ _ _ __ | |_| |_  | |__   ___| |_ __   ___ _ __
 * | '_ \| '__| | '_ \| __|  _| | '_ \ / _ \ | '_ \ / _ \ '__|
 * | |_) | |  | | | | | |_| |   | | | |  __/ | |_) |  __/ |
 * | .__/|_|  |_|_| |_|\__|_|   |_| |_|\___|_| .__/ \___|_|
 * | |                                       | |
 * |_|                                       |_|
 *************************************************************/

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static void emit_8bit_register(const arch_register_t *reg)
{
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	const char *reg_name = arch_register_get_name(reg);
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	be_emit_char('%');
	be_emit_char(reg_name[1]);
	be_emit_char('l');
}

static void emit_16bit_register(const arch_register_t *reg)
{
	const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
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	be_emit_char('%');
	be_emit_string(reg_name);
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}

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static void emit_register(const arch_register_t *reg, const ir_mode *mode)
{
	const char *reg_name;

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	if (mode != NULL) {
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		int size = get_mode_size_bits(mode);
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		switch (size) {
			case  8: emit_8bit_register(reg);  return;
			case 16: emit_16bit_register(reg); return;
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		}
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		assert(mode_is_float(mode) || size == 32);
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	}

	reg_name = arch_register_get_name(reg);
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	be_emit_char('%');
	be_emit_string(reg_name);
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}

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void ia32_emit_source_register(const ir_node *node, int pos)
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{
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	const arch_register_t *reg = get_in_reg(node, pos);
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	emit_register(reg, NULL);
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}

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static void emit_ia32_Immediate(const ir_node *node);

void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
{
	const arch_register_t *reg;
	ir_node               *in = get_irn_n(node, pos);
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	if (is_ia32_Immediate(in)) {
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		emit_ia32_Immediate(in);
		return;
	}

	reg = get_in_reg(node, pos);
	emit_8bit_register(reg);
}

void ia32_emit_dest_register(const ir_node *node, int pos)
{
	const arch_register_t *reg  = get_out_reg(node, pos);

	emit_register(reg, NULL);
}

void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
{
	const arch_register_t *reg  = get_out_reg(node, pos);

	emit_register(reg, mode_Bu);
}

void ia32_emit_x87_register(const ir_node *node, int pos)
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{
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	const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
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	assert(pos < 3);
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	be_emit_char('%');
	be_emit_string(attr->x87[pos]->name);
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}
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static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
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{
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	assert(mode_is_int(mode) || mode_is_reference(mode));
	switch (get_mode_size_bits(mode)) {
		case 8:  be_emit_char('b');     return;
		case 16: be_emit_char('w');     return;
		case 32: be_emit_char('l');     return;
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		/* gas docu says q is the suffix but gcc, objdump and icc use ll
		 * apparently */
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		case 64: be_emit_cstring("ll"); return;
	}
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	panic("Can't output mode_suffix for %+F", mode);
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}

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void ia32_emit_mode_suffix(const ir_node *node)
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{
	ir_mode *mode = get_ia32_ls_mode(node);
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	if (mode == NULL)
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		mode = mode_Iu;

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	ia32_emit_mode_suffix_mode(mode);
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}

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void ia32_emit_x87_mode_suffix(const ir_node *node)
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{
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	ir_mode *mode;

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	/* we only need to emit the mode on address mode */
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	if (get_ia32_op_type(node) == ia32_Normal)
		return;

	mode = get_ia32_ls_mode(node);
	assert(mode != NULL);

	if (mode_is_float(mode)) {
		switch (get_mode_size_bits(mode)) {
			case 32: be_emit_char('s'); return;
			case 64: be_emit_char('l'); return;
			case 80:
			case 96: be_emit_char('t'); return;
		}
	} else {
		assert(mode_is_int(mode));
		switch (get_mode_size_bits(mode)) {
			case 16: be_emit_char('s');     return;
			case 32: be_emit_char('l');     return;
			/* gas docu says q is the suffix but gcc, objdump and icc use ll
			 * apparently */
			case 64: be_emit_cstring("ll"); return;
		}
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	}
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	panic("Can't output mode_suffix for %+F", mode);
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}

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static char get_xmm_mode_suffix(ir_mode *mode)
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{
	assert(mode_is_float(mode));
	switch(get_mode_size_bits(mode)) {
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	case 32: return 's';
	case 64: return 'd';
	default: panic("Invalid XMM mode");
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	}
}

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void ia32_emit_xmm_mode_suffix(const ir_node *node)
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{
	ir_mode *mode = get_ia32_ls_mode(node);
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	assert(mode != NULL);
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	be_emit_char('s');
	be_emit_char(get_xmm_mode_suffix(mode));
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}

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void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
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{
	ir_mode *mode = get_ia32_ls_mode(node);
	assert(mode != NULL);
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	be_emit_char(get_xmm_mode_suffix(mode));
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}

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void ia32_emit_extend_suffix(const ir_mode *mode)
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{
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	if (get_mode_size_bits(mode) == 32)
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		return;
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	be_emit_char(mode_is_signed(mode) ? 's' : 'z');
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}

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void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
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{
	ir_node *in = get_irn_n(node, pos);
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	if (is_ia32_Immediate(in)) {
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		emit_ia32_Immediate(in);
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	} else {
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		const ir_mode         *mode = get_ia32_ls_mode(node);
		const arch_register_t *reg  = get_in_reg(node, pos);
		emit_register(reg, mode);
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	}
}

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/**
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 * Returns the target block for a control flow node.
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 */
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static ir_node *get_cfop_target_block(const ir_node *irn)
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{
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	assert(get_irn_mode(irn) == mode_X);
	return get_irn_link(irn);
}
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/**
 * Emits a block label for the given block.
 */
static void ia32_emit_block_name(const ir_node *block)
{
	if (has_Block_label(block)) {
		be_emit_string(be_gas_block_label_prefix());
		be_emit_irprintf("%lu", get_Block_label(block));
	} else {
		be_emit_cstring(BLOCK_PREFIX);
		be_emit_irprintf("%ld", get_irn_node_nr(block));
	}
}

/**
 * Emits the target label for a control flow node.
 */
static void ia32_emit_cfop_target(const ir_node *node)
{
	ir_node *block = get_cfop_target_block(node);
	ia32_emit_block_name(block);
}

/*
 * coding of conditions
 */
struct cmp2conditon_t {
	const char *name;
	int         num;
};

/*
 * positive conditions for signed compares
 */
static const struct cmp2conditon_t cmp2condition_s[] = {
	{ NULL,              pn_Cmp_False },  /* always false */
	{ "e",               pn_Cmp_Eq },     /* == */
	{ "l",               pn_Cmp_Lt },     /* < */
	{ "le",              pn_Cmp_Le },     /* <= */
	{ "g",               pn_Cmp_Gt },     /* > */
	{ "ge",              pn_Cmp_Ge },     /* >= */
	{ "ne",              pn_Cmp_Lg },     /* != */
	{ NULL,              pn_Cmp_Leg},     /* always true */
};

/*
 * positive conditions for unsigned compares
 */
static const struct cmp2conditon_t cmp2condition_u[] = {
	{ NULL,              pn_Cmp_False },  /* always false */
	{ "e",               pn_Cmp_Eq },     /* == */
	{ "b",               pn_Cmp_Lt },     /* < */
	{ "be",              pn_Cmp_Le },     /* <= */
	{ "a",               pn_Cmp_Gt },     /* > */
	{ "ae",              pn_Cmp_Ge },     /* >= */
	{ "ne",              pn_Cmp_Lg },     /* != */
	{ NULL,              pn_Cmp_Leg },   /* always true  */
};

static void ia32_emit_cmp_suffix(int pnc)
{
	const char *str;

	if ((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
		pnc = pnc & 7;
		assert(cmp2condition_u[pnc].num == pnc);
		str = cmp2condition_u[pnc].name;
	} else {
		pnc = pnc & 7;
		assert(cmp2condition_s[pnc].num == pnc);
		str = cmp2condition_s[pnc].name;
	}

	be_emit_string(str);
}

/**
 * fmt  parameter               output
 * ---- ----------------------  ---------------------------------------------
 * %%                           %
 * %AM  <node>                  address mode of the node
 * %AR  const arch_register_t*  address mode of the node or register
 * %ASx <node>                  address mode of the node or source register x
 * %Dx  <node>                  destination register x
 * %I   <node>                  immediate of the node
 * %L   <node>                  control flow target of the node
 * %M   <node>                  mode suffix of the node
 * %P   int                     condition code
 * %R   const arch_register_t*  register
 * %Sx  <node>                  source register x
 * %s   const char*             string
 * %u   unsigned int            unsigned int
 *
 * x starts at 0
 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
 */
static void ia32_emitf(const ir_node *node, const char *fmt, ...)
{
	va_list ap;
	va_start(ap, fmt);

	for (;;) {
		const char    *start = fmt;
		const ir_mode *mode  = NULL;

		while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
			++fmt;
		if (fmt != start) {
			be_emit_string_len(start, fmt - start);
		}

		if (*fmt == '\n') {
			be_emit_finish_line_gas(node);
			++fmt;
			if (*fmt == '\0')
				break;
			continue;
		}

		if (*fmt == '\0')
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			break;
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		++fmt;
		if (*fmt == '#') {
			mode = get_ia32_ls_mode(node);
			++fmt;
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		}
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		switch (*fmt++) {
			case '%':
				be_emit_char('%');
				break;

			case 'A': {
				switch (*fmt++) {
					case 'M':
						ia32_emit_am(node);
						break;

					case 'R': {
						const arch_register_t *reg = va_arg(ap, const arch_register_t*);
						if (get_ia32_op_type(node) == ia32_AddrModeS) {
							ia32_emit_am(node);
						} else {
							emit_register(reg, NULL);
						}
						break;
					}

					case 'S':
						if (get_ia32_op_type(node) == ia32_AddrModeS) {
							ia32_emit_am(node);
							++fmt;
						} else {
							assert(get_ia32_op_type(node) == ia32_Normal);
							goto emit_S;
						}
						break;

					default: goto unknown;
				}
				break;
			}

			case 'D': {
				unsigned               pos;
				const arch_register_t *reg;

				if (*fmt < '0' || '9' <= *fmt)
					goto unknown;

				pos = *fmt++ - '0';
				reg = get_out_reg(node, pos);
				emit_register(reg, mode);
				break;
			}

			case 'I':
				emit_ia32_Immediate(node);
				break;

			case 'L':
				ia32_emit_cfop_target(node);
				break;

			case 'M': {
				ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
				break;
			}

			case 'P': {
				int pnc = va_arg(ap, int);
				ia32_emit_cmp_suffix(pnc);
				break;
			}

			case 'R': {
				const arch_register_t *reg = va_arg(ap, const arch_register_t*);
				emit_register(reg, NULL);
				break;
			}

emit_S:
			case 'S': {
				unsigned       pos;
				const ir_node *in;

				if (*fmt < '0' || '9' <= *fmt)
					goto unknown;

				pos = *fmt++ - '0';
				in  = get_irn_n(node, pos);
				if (is_ia32_Immediate(in)) {
					emit_ia32_Immediate(in);
				} else {
					const arch_register_t *reg = get_in_reg(node, pos);
					emit_register(reg, mode);
				}
				break;
			}

			case 's': {
				const char *str = va_arg(ap, const char*);
				be_emit_string(str);
				break;
			}

			case 'u': {
				unsigned num = va_arg(ap, unsigned);
				be_emit_irprintf("%u", num);
				break;
			}

			default:
unknown:
				panic("unknown conversion");
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		}
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	}

	va_end(ap);
}

/**
 * Emits registers and/or address mode of a binary operation.
 */
void ia32_emit_binop(const ir_node *node)
{
	if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
		ia32_emitf(node, "%#S4, %#AS3");
	} else {
		ia32_emitf(node, "%#AS4, %#S3");
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	}
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}

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/**
 * Emits registers and/or address mode of a binary operation.
 */
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void ia32_emit_x87_binop(const ir_node *node)
{
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	switch(get_ia32_op_type(node)) {
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		case ia32_Normal:
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			{
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				const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
				const arch_register_t *in1      = x87_attr->x87[0];
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				const arch_register_t *in       = x87_attr->x87[1];
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				const arch_register_t *out      = x87_attr->x87[2];
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				if (out == NULL) {
					out = in1;
				} else if (out == in) {
					in = in1;
				}
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				be_emit_char('%');
				be_emit_string(arch_register_get_name(in));
				be_emit_cstring(", %");
				be_emit_string(arch_register_get_name(out));
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			}
			break;
		case ia32_AddrModeS:
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			ia32_emit_am(node);
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			break;
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		case ia32_AddrModeD:
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		default:
			assert(0 && "unsupported op type");
	}
}

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/**
 * Emits registers and/or address mode of a unary operation.
 */
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void ia32_emit_unop(const ir_node *node, int pos)
{
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	char fmt[] = "%ASx";
	fmt[3] = '0' + pos;
	ia32_emitf(node, fmt);
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}

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static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
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{
	ident *id;

	set_entity_backend_marked(entity, 1);
	id = get_entity_ld_ident(entity);
	be_emit_ident(id);

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	if (get_entity_owner(entity) == get_tls_type()) {
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		if (get_entity_visibility(entity) == visibility_external_allocated) {
			be_emit_cstring("@INDNTPOFF");
		} else {
			be_emit_cstring("@NTPOFF");
		}
	}
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	if (!no_pic_adjust && do_pic) {
		/* TODO: only do this when necessary */
		be_emit_char('-');
		be_emit_string(pic_base_label);
	}
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}

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/**
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 * Emits address mode.
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 */
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void ia32_emit_am(const ir_node *node)
{
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	ir_entity *ent       = get_ia32_am_sc(node);
	int        offs      = get_ia32_am_offs_int(node);
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	ir_node   *base      = get_irn_n(node, n_ia32_base);
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	int        has_base  = !is_ia32_NoReg_GP(base);
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	ir_node   *index     = get_irn_n(node, n_ia32_index);
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	int        has_index = !is_ia32_NoReg_GP(index);
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	/* just to be sure... */
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	assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
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	/* emit offset */
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	if (ent != NULL) {
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		if (is_ia32_am_sc_sign(node))
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			be_emit_char('-');
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		ia32_emit_entity(ent, 0);
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	}

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	/* also handle special case if nothing is set */
	if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
		if (ent != NULL) {
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			be_emit_irprintf("%+d", offs);
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		} else {
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			be_emit_irprintf("%d", offs);
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		}
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	}
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	if (has_base || has_index) {
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		be_emit_char('(');
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		/* emit base */
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		if (has_base) {
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			const arch_register_t *reg = get_in_reg(node, n_ia32_base);
			emit_register(reg, NULL);
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		}

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		/* emit index + scale */
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		if (has_index) {
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			const arch_register_t *reg = get_in_reg(node, n_ia32_index);
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			int scale;
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			be_emit_char(',');
			emit_register(reg, NULL);
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			scale = get_ia32_am_scale(node);
			if (scale > 0) {
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				be_emit_irprintf(",%d", 1 << scale);
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			}
		}
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		be_emit_char(')');
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	}
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}
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static void emit_ia32_IMul(const ir_node *node)
{
	ir_node               *left    = get_irn_n(node, n_ia32_IMul_left);
	const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);

	/* do we need the 3-address form? */
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	if (is_ia32_NoReg_GP(left) ||
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			get_in_reg(node, n_ia32_IMul_left) != out_reg) {
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		ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
	} else {
		ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
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	}
}

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/**
 * walks up a tree of copies/perms/spills/reloads to find the original value
 * that is moved around
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 */
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static ir_node *find_original_value(ir_node *node)
{
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	if (irn_visited(node))
		return NULL;

	mark_irn_visited(node);
	if (be_is_Copy(node)) {
		return find_original_value(be_get_Copy_op(node));
	} else if (be_is_CopyKeep(node)) {
		return find_original_value(be_get_CopyKeep_op(node));
	} else if (is_Proj(node)) {
		ir_node *pred = get_Proj_pred(node);
		if (be_is_Perm(pred)) {
			return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
		} else if (be_is_MemPerm(pred)) {
			return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
		} else if (is_ia32_Load(pred)) {
			return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
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		} else {
			return node;
		}
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	} else if (is_ia32_Store(node)) {
		return find_original_value(get_irn_n(node, n_ia32_Store_val));
	} else if (is_Phi(node)) {
		int i, arity;
		arity = get_irn_arity(node);
		for (i = 0; i < arity; ++i) {
			ir_node *in  = get_irn_n(node, i);
			ir_node *res = find_original_value(in);

			if (res != NULL)
				return res;
		}
		return NULL;
	} else {
		return node;
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	}
}

static int determine_final_pnc(const ir_node *node, int flags_pos,
                               int pnc)
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{
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	ir_node           *flags = get_irn_n(node, flags_pos);
	const ia32_attr_t *flags_attr;
	flags = skip_Proj(flags);

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	if (is_ia32_Sahf(flags)) {
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		ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
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		if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
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				|| is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
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			inc_irg_visited(current_ir_graph);
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			cmp = find_original_value(cmp);
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			assert(cmp != NULL);
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			assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
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			       || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
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		}
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		flags_attr = get_ia32_attr_const(cmp);
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		if (flags_attr->data.ins_permuted)
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			pnc = get_mirrored_pnc(pnc);
		pnc |= ia32_pn_Cmp_float;
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	} else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
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			|| is_ia32_Fucompi(flags)) {
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		flags_attr = get_ia32_attr_const(flags);

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		if (flags_attr->data.ins_permuted)
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			pnc = get_mirrored_pnc(pnc);
		pnc |= ia32_pn_Cmp_float;
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	} else {
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		flags_attr = get_ia32_attr_const(flags);

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		if (flags_attr->data.ins_permuted)
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			pnc = get_mirrored_pnc(pnc);
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		if (flags_attr->data.cmp_unsigned)
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			pnc |= ia32_pn_Cmp_unsigned;
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	}
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	return pnc;
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}

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void ia32_emit_cmp_suffix_node(const ir_node *node,
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                               int flags_pos)
{
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	const ia32_attr_t *attr = get_ia32_attr_const(node);

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	pn_Cmp pnc = get_ia32_condcode(node);
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	pnc = determine_final_pnc(node, flags_pos, pnc);
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	if (attr->data.ins_permuted) {
		if (pnc & ia32_pn_Cmp_float) {
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			pnc = get_negated_pnc(pnc, mode_F);
		} else {
			pnc = get_negated_pnc(pnc, mode_Iu);
		}
	}

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	ia32_emit_cmp_suffix(pnc);
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}
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/**
 * Emits an exception label for a given node.
 */
static void ia32_emit_exc_label(const ir_node *node)
{
	be_emit_string(be_gas_insn_label_prefix());
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	be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
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}

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/**
 * Returns the Proj with projection number proj and NOT mode_M
 */
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static ir_node *get_proj(const ir_node *node, long proj)
{
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	const ir_edge_t *edge;
	ir_node         *src;

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	assert(get_irn_mode(node) == mode_T && "expected mode_T node");
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	foreach_out_edge(node, edge) {
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		src = get_edge_src_irn(edge);

		assert(is_Proj(src) && "Proj expected");
		if (get_irn_mode(src) == mode_M)
			continue;

		if (get_Proj_proj(src) == proj)
			return src;
	}
	return NULL;
}

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static int can_be_fallthrough(const ir_node *node)
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{
	ir_node *target_block = get_cfop_target_block(node);
	ir_node *block        = get_nodes_block(node);
	return get_prev_block_sched(target_block) == block;
}

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/**
 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
 */
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static void emit_ia32_Jcc(const ir_node *node)
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{
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	int            need_parity_label = 0;
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	const ir_node *proj_true;
	const ir_node *proj_false;
	const ir_node *block;
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	pn_Cmp         pnc = get_ia32_condcode(node);
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	pnc = determine_final_pnc(node, 0, pnc);
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	/* get both Projs */
	proj_true = get_proj(node, pn_ia32_Jcc_true);
	assert(proj_true && "Jcc without true Proj");
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	proj_false = get_proj(node, pn_ia32_Jcc_false);
	assert(proj_false && "Jcc without false Proj");
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	block      = get_nodes_block(node);
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	if (can_be_fallthrough(proj_true)) {
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		/* exchange both proj's so the second one can be omitted */
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		const ir_node *t = proj_true;

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		proj_true  = proj_false;
		proj_false = t;
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		if (pnc & ia32_pn_Cmp_float) {
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			pnc = get_negated_pnc(pnc, mode_F);
		} else {
			pnc = get_negated_pnc(pnc, mode_Iu);
		}
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	}

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	if (pnc & ia32_pn_Cmp_float) {
		/* Some floating point comparisons require a test of the parity flag,
		 * which indicates that the result is unordered */
		switch (pnc & 15) {
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			case pn_Cmp_Uo: {
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				ia32_emitf(proj_true, "\tjp %L\n");
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				break;
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			}
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			case pn_Cmp_Leg:
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				ia32_emitf(proj_true, "\tjnp %L\n");
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				break;

			case pn_Cmp_Eq:
			case pn_Cmp_Lt:
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			case pn_Cmp_Le:
				/* we need a local label if the false proj is a fallthrough
				 * as the falseblock might have no label emitted then */
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				if (can_be_fallthrough(proj_false)) {
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					need_parity_label = 1;
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					ia32_emitf(proj_false, "\tjp 1f\n");
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				} else {
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					ia32_emitf(proj_false, "\tjp %L\n");
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				}
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				goto emit_jcc;
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			case pn_Cmp_Ug:
			case pn_Cmp_Uge:
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			case pn_Cmp_Ne:
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				ia32_emitf(proj_true, "\tjp %L\n");
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				goto emit_jcc;
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			default:
				goto emit_jcc;
		}
	} else {
emit_jcc:
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		ia32_emitf(proj_true, "\tj%P %L\n", pnc);
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	}

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	if (need_parity_label) {
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		ia32_emitf(NULL, "1:\n");
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	}

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	/* the second Proj might be a fallthrough */
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	if (can_be_fallthrough(proj_false)) {
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		ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
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	} else {
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		ia32_emitf(proj_false, "\tjmp %L\n");
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	}
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}

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static void emit_ia32_CMov(const ir_node *node)
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{
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	const ia32_attr_t     *attr         = get_ia32_attr_const(node);
	int                    ins_permuted = attr->data.ins_permuted;
	const arch_register_t *out          = arch_get_irn_register(arch_env, node);
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	pn_Cmp                 pnc          = get_ia32_condcode(node);
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	const arch_register_t *in_true;
	const arch_register_t *in_false;

	pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);

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	in_true  = arch_get_irn_register(arch_env,
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	                                 get_irn_n(node, n_ia32_CMov_val_true));
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	in_false = arch_get_irn_register(arch_env,
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	                                 get_irn_n(node, n_ia32_CMov_val_false));

	/* should be same constraint fullfilled? */
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	if (out == in_false) {
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		/* yes -> nothing to do */
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	} else if (out == in_true) {
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		const arch_register_t *tmp;

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		assert(get_ia32_op_type(node) == ia32_Normal);

		ins_permuted = !ins_permuted;
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		tmp      = in_true;
		in_true  = in_false;
		in_false = tmp;
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	} else {
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		/* we need a mov */
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		ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
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	}
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	if (ins_permuted) {
		if (pnc & ia32_pn_Cmp_float) {
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			pnc = get_negated_pnc(pnc, mode_F);
		} else {
			pnc = get_negated_pnc(pnc, mode_Iu);
		}
	}

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	/* TODO: handling of Nans isn't correct yet */

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	ia32_emitf(node, "\tcmov%P %AR, %#R\n", pnc, in_true, out);
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}