ia32_transform.c

/*
 * Copyright (C) 1995-2011 University of Karlsruhe.  All right reserved.
 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

/**
 * @file
 * @brief       This file implements the IR transformation from firm into
 *              ia32-Firm.
 * @author      Christian Wuerdig, Matthias Braun
 * @version     $Id$
 */
#include "config.h"

#include <limits.h>
#include <stdbool.h>

#include "irargs_t.h"
#include "irnode_t.h"
#include "irgraph_t.h"
#include "irmode_t.h"
#include "iropt_t.h"
#include "irop_t.h"
#include "irprog_t.h"
#include "iredges_t.h"
#include "irgmod.h"
#include "ircons.h"
#include "irgwalk.h"
#include "irprintf.h"
#include "debug.h"
#include "irdom.h"
#include "error.h"
#include "array_t.h"
#include "heights.h"

#include "../benode.h"
#include "../besched.h"
#include "../beabi.h"
#include "../beutil.h"
#include "../beirg.h"
#include "../betranshlp.h"
#include "../be_t.h"

#include "bearch_ia32_t.h"
#include "ia32_common_transform.h"
#include "ia32_nodes_attr.h"
#include "ia32_transform.h"
#include "ia32_new_nodes.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
#include "ia32_util.h"
#include "ia32_address_mode.h"
#include "ia32_architecture.h"

#include "gen_ia32_regalloc_if.h"

/* define this to construct SSE constants instead of load them */
#undef CONSTRUCT_SSE_CONST


#define SFP_SIGN   "0x80000000"
#define DFP_SIGN   "0x8000000000000000"
#define SFP_ABS    "0x7FFFFFFF"
#define DFP_ABS    "0x7FFFFFFFFFFFFFFF"
#define DFP_INTMAX "9223372036854775807"
#define ULL_BIAS   "18446744073709551616"

#define ENT_SFP_SIGN "C_ia32_sfp_sign"
#define ENT_DFP_SIGN "C_ia32_dfp_sign"
#define ENT_SFP_ABS  "C_ia32_sfp_abs"
#define ENT_DFP_ABS  "C_ia32_dfp_abs"
#define ENT_ULL_BIAS "C_ia32_ull_bias"

#define mode_vfp    (ia32_reg_classes[CLASS_ia32_vfp].mode)
#define mode_xmm    (ia32_reg_classes[CLASS_ia32_xmm].mode)

DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

static ir_node         *initial_fpcw = NULL;
int                     ia32_no_pic_adjust;

typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
        ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
        ir_node *op2);

typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
        ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
        ir_node *flags);

typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
        ir_node *op1, ir_node *op2);

typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
        ir_node *base, ir_node *index, ir_node *mem, ir_node *op);

typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
        ir_node *base, ir_node *index, ir_node *mem);

typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
        ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
        ir_node *fpcw);

typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);

static ir_node *create_immediate_or_transform(ir_node *node,
                                              char immediate_constraint_type);

static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
                                dbg_info *dbgi, ir_node *block,
                                ir_node *op, ir_node *orig_node);

/* its enough to have those once */
static ir_node *nomem, *noreg_GP;

/** a list to postprocess all calls */
static ir_node **call_list;
static ir_type **call_types;

/** Return non-zero is a node represents the 0 constant. */
static bool is_Const_0(ir_node *node)
{
	return is_Const(node) && is_Const_null(node);
}

/** Return non-zero is a node represents the 1 constant. */
static bool is_Const_1(ir_node *node)
{
	return is_Const(node) && is_Const_one(node);
}

/** Return non-zero is a node represents the -1 constant. */
static bool is_Const_Minus_1(ir_node *node)
{
	return is_Const(node) && is_Const_all_one(node);
}

/**
 * returns true if constant can be created with a simple float command
 */
static bool is_simple_x87_Const(ir_node *node)
{
	ir_tarval *tv = get_Const_tarval(node);
	if (tarval_is_null(tv) || tarval_is_one(tv))
		return true;

	/* TODO: match all the other float constants */
	return false;
}

/**
 * returns true if constant can be created with a simple float command
 */
static bool is_simple_sse_Const(ir_node *node)
{
	ir_tarval *tv   = get_Const_tarval(node);
	ir_mode   *mode = get_tarval_mode(tv);

	if (mode == mode_F)
		return true;

	if (tarval_is_null(tv)
#ifdef CONSTRUCT_SSE_CONST
	    || tarval_is_one(tv)
#endif
	   )
		return true;
#ifdef CONSTRUCT_SSE_CONST
	if (mode == mode_D) {
		unsigned val = get_tarval_sub_bits(tv, 0) |
			(get_tarval_sub_bits(tv, 1) << 8) |
			(get_tarval_sub_bits(tv, 2) << 16) |
			(get_tarval_sub_bits(tv, 3) << 24);
		if (val == 0)
			/* lower 32bit are zero, really a 32bit constant */
			return true;
	}
#endif /* CONSTRUCT_SSE_CONST */
	/* TODO: match all the other float constants */
	return false;
}

/**
 * return NoREG or pic_base in case of PIC.
 * This is necessary as base address for newly created symbols
 */
static ir_node *get_symconst_base(void)
{
	ir_graph *irg = current_ir_graph;

	if (be_get_irg_options(irg)->pic) {
		const arch_env_t *arch_env = be_get_irg_arch_env(irg);
		return arch_env->impl->get_pic_base(irg);
	}

	return noreg_GP;
}

/**
 * Transforms a Const.
 */
static ir_node *gen_Const(ir_node *node)
{
	ir_node  *old_block = get_nodes_block(node);
	ir_node  *block     = be_transform_node(old_block);
	dbg_info *dbgi      = get_irn_dbg_info(node);
	ir_mode  *mode      = get_irn_mode(node);

	assert(is_Const(node));

	if (mode_is_float(mode)) {
		ir_node   *res   = NULL;
		ir_node   *load;
		ir_node   *base;
		ir_entity *floatent;

		if (ia32_cg_config.use_sse2) {
			ir_tarval *tv = get_Const_tarval(node);
			if (tarval_is_null(tv)) {
				load = new_bd_ia32_xZero(dbgi, block);
				set_ia32_ls_mode(load, mode);
				res  = load;
#ifdef CONSTRUCT_SSE_CONST
			} else if (tarval_is_one(tv)) {
				int     cnst  = mode == mode_F ? 26 : 55;
				ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
				ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
				ir_node *pslld, *psrld;

				load = new_bd_ia32_xAllOnes(dbgi, block);
				set_ia32_ls_mode(load, mode);
				pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
				set_ia32_ls_mode(pslld, mode);
				psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
				set_ia32_ls_mode(psrld, mode);
				res = psrld;
#endif /* CONSTRUCT_SSE_CONST */
			} else if (mode == mode_F) {
				/* we can place any 32bit constant by using a movd gp, sse */
				unsigned val = get_tarval_sub_bits(tv, 0) |
				               (get_tarval_sub_bits(tv, 1) << 8) |
				               (get_tarval_sub_bits(tv, 2) << 16) |
				               (get_tarval_sub_bits(tv, 3) << 24);
				ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
				load = new_bd_ia32_xMovd(dbgi, block, cnst);
				set_ia32_ls_mode(load, mode);
				res = load;
			} else {
#ifdef CONSTRUCT_SSE_CONST
				if (mode == mode_D) {
					unsigned val = get_tarval_sub_bits(tv, 0) |
						(get_tarval_sub_bits(tv, 1) << 8) |
						(get_tarval_sub_bits(tv, 2) << 16) |
						(get_tarval_sub_bits(tv, 3) << 24);
					if (val == 0) {
						ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
						ir_node *cnst, *psllq;

						/* fine, lower 32bit are zero, produce 32bit value */
						val = get_tarval_sub_bits(tv, 4) |
							(get_tarval_sub_bits(tv, 5) << 8) |
							(get_tarval_sub_bits(tv, 6) << 16) |
							(get_tarval_sub_bits(tv, 7) << 24);
						cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
						load = new_bd_ia32_xMovd(dbgi, block, cnst);
						set_ia32_ls_mode(load, mode);
						psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
						set_ia32_ls_mode(psllq, mode);
						res = psllq;
						goto end;
					}
				}
#endif /* CONSTRUCT_SSE_CONST */
				floatent = ia32_create_float_const_entity(node);

				base     = get_symconst_base();
				load     = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
				                             mode);
				set_ia32_op_type(load, ia32_AddrModeS);
				set_ia32_am_sc(load, floatent);
				arch_irn_add_flags(load, arch_irn_flags_rematerializable);
				res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res);
			}
		} else {
			if (is_Const_null(node)) {
				load = new_bd_ia32_vfldz(dbgi, block);
				res  = load;
				set_ia32_ls_mode(load, mode);
			} else if (is_Const_one(node)) {
				load = new_bd_ia32_vfld1(dbgi, block);
				res  = load;
				set_ia32_ls_mode(load, mode);
			} else {
				ir_mode *ls_mode;
				ir_node *base;

				floatent = ia32_create_float_const_entity(node);
				/* create_float_const_ent is smart and sometimes creates
				   smaller entities */
				ls_mode  = get_type_mode(get_entity_type(floatent));
				base     = get_symconst_base();
				load     = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
				                            ls_mode);
				set_ia32_op_type(load, ia32_AddrModeS);
				set_ia32_am_sc(load, floatent);
				arch_irn_add_flags(load, arch_irn_flags_rematerializable);
				res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
			}
		}
#ifdef CONSTRUCT_SSE_CONST
end:
#endif /* CONSTRUCT_SSE_CONST */
		SET_IA32_ORIG_NODE(load, node);
		return res;
	} else { /* non-float mode */
		ir_node   *cnst;
		ir_tarval *tv = get_Const_tarval(node);
		long       val;

		tv = tarval_convert_to(tv, mode_Iu);

		if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
		    tv == NULL) {
			panic("couldn't convert constant tarval (%+F)", node);
		}
		val = get_tarval_long(tv);

		cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
		SET_IA32_ORIG_NODE(cnst, node);

		return cnst;
	}
}

/**
 * Transforms a SymConst.
 */
static ir_node *gen_SymConst(ir_node *node)
{
	ir_node  *old_block = get_nodes_block(node);
	ir_node  *block = be_transform_node(old_block);
	dbg_info *dbgi  = get_irn_dbg_info(node);
	ir_mode  *mode  = get_irn_mode(node);
	ir_node  *cnst;

	if (mode_is_float(mode)) {
		if (ia32_cg_config.use_sse2)
			cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
		else
			cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
		set_ia32_am_sc(cnst, get_SymConst_entity(node));
		set_ia32_use_frame(cnst);
	} else {
		ir_entity *entity;

		if (get_SymConst_kind(node) != symconst_addr_ent) {
			panic("backend only support symconst_addr_ent (at %+F)", node);
		}
		entity = get_SymConst_entity(node);
		if (get_entity_owner(entity) == get_tls_type()) {
			ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
			ir_node *lea     = new_bd_ia32_Lea(dbgi, block, tls_base, noreg_GP);
			set_ia32_am_sc(lea, entity);
			cnst = lea;
		} else {
			cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
		}
	}

	SET_IA32_ORIG_NODE(cnst, node);

	return cnst;
}

/**
 * Create a float type for the given mode and cache it.
 *
 * @param mode   the mode for the float type (might be integer mode for SSE2 types)
 * @param align  alignment
 */
static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align)
{
	ir_type *tp;

	assert(align <= 16);

	if (mode == mode_Iu) {
		static ir_type *int_Iu[16] = {NULL, };

		if (int_Iu[align] == NULL) {
			int_Iu[align] = tp = new_type_primitive(mode);
			/* set the specified alignment */
			set_type_alignment_bytes(tp, align);
		}
		return int_Iu[align];
	} else if (mode == mode_Lu) {
		static ir_type *int_Lu[16] = {NULL, };

		if (int_Lu[align] == NULL) {
			int_Lu[align] = tp = new_type_primitive(mode);
			/* set the specified alignment */
			set_type_alignment_bytes(tp, align);
		}
		return int_Lu[align];
	} else if (mode == mode_F) {
		static ir_type *float_F[16] = {NULL, };

		if (float_F[align] == NULL) {
			float_F[align] = tp = new_type_primitive(mode);
			/* set the specified alignment */
			set_type_alignment_bytes(tp, align);
		}
		return float_F[align];
	} else if (mode == mode_D) {
		static ir_type *float_D[16] = {NULL, };

		if (float_D[align] == NULL) {
			float_D[align] = tp = new_type_primitive(mode);
			/* set the specified alignment */
			set_type_alignment_bytes(tp, align);
		}
		return float_D[align];
	} else {
		static ir_type *float_E[16] = {NULL, };

		if (float_E[align] == NULL) {
			float_E[align] = tp = new_type_primitive(mode);
			/* set the specified alignment */
			set_type_alignment_bytes(tp, align);
		}
		return float_E[align];
	}
}

/**
 * Create a float[2] array type for the given atomic type.
 *
 * @param tp  the atomic type
 */
static ir_type *ia32_create_float_array(ir_type *tp)
{
	ir_mode  *mode = get_type_mode(tp);
	unsigned align = get_type_alignment_bytes(tp);
	ir_type  *arr;

	assert(align <= 16);

	if (mode == mode_F) {
		static ir_type *float_F[16] = {NULL, };

		if (float_F[align] != NULL)
			return float_F[align];
		arr = float_F[align] = new_type_array(1, tp);
	} else if (mode == mode_D) {
		static ir_type *float_D[16] = {NULL, };

		if (float_D[align] != NULL)
			return float_D[align];
		arr = float_D[align] = new_type_array(1, tp);
	} else {
		static ir_type *float_E[16] = {NULL, };

		if (float_E[align] != NULL)
			return float_E[align];
		arr = float_E[align] = new_type_array(1, tp);
	}
	set_type_alignment_bytes(arr, align);
	set_type_size_bytes(arr, 2 * get_type_size_bytes(tp));
	set_type_state(arr, layout_fixed);
	return arr;
}

/* Generates an entity for a known FP const (used for FP Neg + Abs) */
ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
{
	static const struct {
		const char *ent_name;
		const char *cnst_str;
		char mode;
		unsigned char align;
	} names [ia32_known_const_max] = {
		{ ENT_SFP_SIGN, SFP_SIGN,   0, 16 }, /* ia32_SSIGN */
		{ ENT_DFP_SIGN, DFP_SIGN,   1, 16 }, /* ia32_DSIGN */
		{ ENT_SFP_ABS,  SFP_ABS,    0, 16 }, /* ia32_SABS */
		{ ENT_DFP_ABS,  DFP_ABS,    1, 16 }, /* ia32_DABS */
		{ ENT_ULL_BIAS, ULL_BIAS,   2, 4 }   /* ia32_ULLBIAS */
	};
	static ir_entity *ent_cache[ia32_known_const_max];

	const char *ent_name, *cnst_str;
	ir_type    *tp;
	ir_entity  *ent;
	ir_tarval  *tv;
	ir_mode    *mode;

	ent_name = names[kct].ent_name;
	if (! ent_cache[kct]) {
		cnst_str = names[kct].cnst_str;

		switch (names[kct].mode) {
		case 0:  mode = mode_Iu; break;
		case 1:  mode = mode_Lu; break;
		default: mode = mode_F;  break;
		}
		tv  = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
		tp  = ia32_create_float_type(mode, names[kct].align);

		if (kct == ia32_ULLBIAS)
			tp = ia32_create_float_array(tp);
		ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);

		set_entity_ld_ident(ent, get_entity_ident(ent));
		add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
		set_entity_visibility(ent, ir_visibility_private);

		if (kct == ia32_ULLBIAS) {
			ir_initializer_t *initializer = create_initializer_compound(2);

			set_initializer_compound_value(initializer, 0,
				create_initializer_tarval(get_mode_null(mode)));
			set_initializer_compound_value(initializer, 1,
				create_initializer_tarval(tv));

			set_entity_initializer(ent, initializer);
		} else {
			set_entity_initializer(ent, create_initializer_tarval(tv));
		}

		/* cache the entry */
		ent_cache[kct] = ent;
	}

	return ent_cache[kct];
}

/**
 * return true if the node is a Proj(Load) and could be used in source address
 * mode for another node. Will return only true if the @p other node is not
 * dependent on the memory of the Load (for binary operations use the other
 * input here, for unary operations use NULL).
 */
static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
                                        ir_node *other, ir_node *other2, match_flags_t flags)
{
	ir_node *load;
	long     pn;

	/* float constants are always available */
	if (is_Const(node)) {
		ir_mode *mode = get_irn_mode(node);
		if (mode_is_float(mode)) {
			if (ia32_cg_config.use_sse2) {
				if (is_simple_sse_Const(node))
					return 0;
			} else {
				if (is_simple_x87_Const(node))
					return 0;
			}
			if (get_irn_n_edges(node) > 1)
				return 0;
			return 1;
		}
	}

	if (!is_Proj(node))
		return 0;
	load = get_Proj_pred(node);
	pn   = get_Proj_proj(node);
	if (!is_Load(load) || pn != pn_Load_res)
		return 0;
	if (get_nodes_block(load) != block)
		return 0;
	/* we only use address mode if we're the only user of the load */
	if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
		return 0;
	/* in some edge cases with address mode we might reach the load normally
	 * and through some AM sequence, if it is already materialized then we
	 * can't create an AM node from it */
	if (be_is_transformed(node))
		return 0;

	/* don't do AM if other node inputs depend on the load (via mem-proj) */
	if (other != NULL && ia32_prevents_AM(block, load, other))
		return 0;

	if (other2 != NULL && ia32_prevents_AM(block, load, other2))
		return 0;

	return 1;
}

typedef struct ia32_address_mode_t ia32_address_mode_t;
struct ia32_address_mode_t {
	ia32_address_t  addr;
	ir_mode        *ls_mode;
	ir_node        *mem_proj;
	ir_node        *am_node;
	ia32_op_type_t  op_type;
	ir_node        *new_op1;
	ir_node        *new_op2;
	op_pin_state    pinned;
	unsigned        commutative  : 1;
	unsigned        ins_permuted : 1;
};

static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
{
	/* construct load address */
	memset(addr, 0, sizeof(addr[0]));
	ia32_create_address_mode(addr, ptr, ia32_create_am_normal);

	addr->base  = addr->base  ? be_transform_node(addr->base)  : noreg_GP;
	addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
	addr->mem   = be_transform_node(mem);
}

static void build_address(ia32_address_mode_t *am, ir_node *node,
                          ia32_create_am_flags_t flags)
{
	ia32_address_t *addr = &am->addr;
	ir_node        *load;
	ir_node        *ptr;
	ir_node        *mem;
	ir_node        *new_mem;

	/* floating point immediates */
	if (is_Const(node)) {
		ir_entity *entity  = ia32_create_float_const_entity(node);
		addr->base         = get_symconst_base();
		addr->index        = noreg_GP;
		addr->mem          = nomem;
		addr->symconst_ent = entity;
		addr->tls_segment  = false;
		addr->use_frame    = 1;
		am->ls_mode        = get_type_mode(get_entity_type(entity));
		am->pinned         = op_pin_state_floats;
		return;
	}

	load         = get_Proj_pred(node);
	ptr          = get_Load_ptr(load);
	mem          = get_Load_mem(load);
	new_mem      = be_transform_node(mem);
	am->pinned   = get_irn_pinned(load);
	am->ls_mode  = get_Load_mode(load);
	am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
	am->am_node  = node;

	/* construct load address */
	ia32_create_address_mode(addr, ptr, flags);

	addr->base  = addr->base  ? be_transform_node(addr->base)  : noreg_GP;
	addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
	addr->mem   = new_mem;
}

static void set_address(ir_node *node, const ia32_address_t *addr)
{
	set_ia32_am_scale(node, addr->scale);
	set_ia32_am_sc(node, addr->symconst_ent);
	set_ia32_am_offs_int(node, addr->offset);
	set_ia32_am_tls_segment(node, addr->tls_segment);
	if (addr->symconst_sign)
		set_ia32_am_sc_sign(node);
	if (addr->use_frame)
		set_ia32_use_frame(node);
	set_ia32_frame_ent(node, addr->frame_entity);
}

/**
 * Apply attributes of a given address mode to a node.
 */
static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
{
	set_address(node, &am->addr);

	set_ia32_op_type(node, am->op_type);
	set_ia32_ls_mode(node, am->ls_mode);
	if (am->pinned == op_pin_state_pinned) {
		/* beware: some nodes are already pinned and did not allow to change the state */
		if (get_irn_pinned(node) != op_pin_state_pinned)
			set_irn_pinned(node, op_pin_state_pinned);
	}
	if (am->commutative)
		set_ia32_commutative(node);
}

/**
 * Check, if a given node is a Down-Conv, ie. a integer Conv
 * from a mode with a mode with more bits to a mode with lesser bits.
 * Moreover, we return only true if the node has not more than 1 user.
 *
 * @param node   the node
 * @return non-zero if node is a Down-Conv
 */
static int is_downconv(const ir_node *node)
{
	ir_mode *src_mode;
	ir_mode *dest_mode;

	if (!is_Conv(node))
		return 0;

	/* we only want to skip the conv when we're the only user
	 * (because this test is used in the context of address-mode selection
	 *  and we don't want to use address mode for multiple users) */
	if (get_irn_n_edges(node) > 1)
		return 0;

	src_mode  = get_irn_mode(get_Conv_op(node));
	dest_mode = get_irn_mode(node);
	return
		ia32_mode_needs_gp_reg(src_mode)  &&
		ia32_mode_needs_gp_reg(dest_mode) &&
		get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
}

/** Skip all Down-Conv's on a given node and return the resulting node. */
ir_node *ia32_skip_downconv(ir_node *node)
{
	while (is_downconv(node))
		node = get_Conv_op(node);

	return node;
}

static bool is_sameconv(ir_node *node)
{
	ir_mode *src_mode;
	ir_mode *dest_mode;

	if (!is_Conv(node))
		return 0;

	/* we only want to skip the conv when we're the only user
	 * (because this test is used in the context of address-mode selection
	 *  and we don't want to use address mode for multiple users) */
	if (get_irn_n_edges(node) > 1)
		return 0;

	src_mode  = get_irn_mode(get_Conv_op(node));
	dest_mode = get_irn_mode(node);
	return
		ia32_mode_needs_gp_reg(src_mode)  &&
		ia32_mode_needs_gp_reg(dest_mode) &&
		get_mode_size_bits(dest_mode) == get_mode_size_bits(src_mode);
}

/** Skip all signedness convs */
static ir_node *ia32_skip_sameconv(ir_node *node)
{
	while (is_sameconv(node))
		node = get_Conv_op(node);

	return node;
}

static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
{
	ir_mode  *mode = get_irn_mode(node);
	ir_node  *block;
	ir_mode  *tgt_mode;
	dbg_info *dbgi;

	if (mode_is_signed(mode)) {
		tgt_mode = mode_Is;
	} else {
		tgt_mode = mode_Iu;
	}
	block = get_nodes_block(node);
	dbgi  = get_irn_dbg_info(node);

	return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
}

/**
 * matches operands of a node into ia32 addressing/operand modes. This covers
 * usage of source address mode, immediates, operations with non 32-bit modes,
 * ...
 * The resulting data is filled into the @p am struct. block is the block
 * of the node whose arguments are matched. op1, op2 are the first and second
 * input that are matched (op1 may be NULL). other_op is another unrelated
 * input that is not matched! but which is needed sometimes to check if AM
 * for op1/op2 is legal.
 * @p flags describes the supported modes of the operation in detail.
 */
static void match_arguments(ia32_address_mode_t *am, ir_node *block,
                            ir_node *op1, ir_node *op2, ir_node *other_op,
                            match_flags_t flags)
{
	ia32_address_t *addr      = &am->addr;
	ir_mode        *mode      = get_irn_mode(op2);
	int             mode_bits = get_mode_size_bits(mode);
	ir_node        *new_op1, *new_op2;
	int             use_am;
	unsigned        commutative;
	int             use_am_and_immediates;
	int             use_immediate;

	memset(am, 0, sizeof(am[0]));

	commutative           = (flags & match_commutative) != 0;
	use_am_and_immediates = (flags & match_am_and_immediates) != 0;
	use_am                = (flags & match_am) != 0;
	use_immediate         = (flags & match_immediate) != 0;
	assert(!use_am_and_immediates || use_immediate);

	assert(op2 != NULL);
	assert(!commutative || op1 != NULL);
	assert(use_am || !(flags & match_8bit_am));
	assert(use_am || !(flags & match_16bit_am));

	if ((mode_bits ==  8 && !(flags & match_8bit_am)) ||
	    (mode_bits == 16 && !(flags & match_16bit_am))) {
		use_am = 0;
	}

	/* we can simply skip downconvs for mode neutral nodes: the upper bits
	 * can be random for these operations */
	if (flags & match_mode_neutral) {
		op2 = ia32_skip_downconv(op2);
		if (op1 != NULL) {
			op1 = ia32_skip_downconv(op1);
		}
	} else {
		op2 = ia32_skip_sameconv(op2);
		if (op1 != NULL) {
			op1 = ia32_skip_sameconv(op1);
		}
	}

	/* match immediates. firm nodes are normalized: constants are always on the
	 * op2 input */
	new_op2 = NULL;
	if (!(flags & match_try_am) && use_immediate) {
		new_op2 = ia32_try_create_Immediate(op2, 0);
	}

	if (new_op2 == NULL &&
	    use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
		build_address(am, op2, ia32_create_am_normal);
		new_op1     = (op1 == NULL ? NULL : be_transform_node(op1));
		if (mode_is_float(mode)) {
			new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
		} else {
			new_op2 = noreg_GP;
		}
		am->op_type = ia32_AddrModeS;
	} else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
		       use_am &&
		       ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
		ir_node *noreg;
		build_address(am, op1, ia32_create_am_normal);

		if (mode_is_float(mode)) {
			noreg = ia32_new_NoReg_vfp(current_ir_graph);
		} else {
			noreg = noreg_GP;
		}

		if (new_op2 != NULL) {
			new_op1 = noreg;
		} else {
			new_op1 = be_transform_node(op2);
			new_op2 = noreg;
			am->ins_permuted = true;
		}
		am->op_type = ia32_AddrModeS;
	} else {
		ir_mode *mode;
		am->op_type = ia32_Normal;

		if (flags & match_try_am) {
			am->new_op1 = NULL;
			am->new_op2 = NULL;
			return;
		}