bearch_ia32.c 68.4 KB
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/*
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 * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
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 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

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/**
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 * @file
 * @brief       This is the main ia32 firm backend driver.
 * @author      Christian Wuerdig
 * @version     $Id$
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 */
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#include "config.h"
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#include "lc_opts.h"
#include "lc_opts_enum.h"
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#include <math.h>

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#include "pseudo_irg.h"
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#include "irarch.h"
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#include "irgwalk.h"
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#include "irprog.h"
#include "irprintf.h"
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#include "iredges_t.h"
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#include "ircons.h"
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#include "irflag.h"
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#include "irgmod.h"
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#include "irgopt.h"
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#include "irbitset.h"
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#include "irgopt.h"
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#include "pdeq.h"
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#include "pset.h"
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#include "debug.h"
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#include "error.h"
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#include "xmalloc.h"
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#include "irtools.h"
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#include "iroptimize.h"
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#include "instrument.h"
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#include "../beabi.h"
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#include "../beirg.h"
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#include "../benode.h"
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#include "../belower.h"
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#include "../besched.h"
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#include "be.h"
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#include "../be_t.h"
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#include "../beirgmod.h"
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#include "../be_dbgout.h"
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#include "../beblocksched.h"
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#include "../bemachine.h"
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#include "../beilpsched.h"
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#include "../bespillslots.h"
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#include "../bemodule.h"
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#include "../begnuas.h"
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#include "../bestate.h"
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#include "../beflags.h"
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#include "../betranshlp.h"
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#include "../belistsched.h"
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#include "bearch_ia32_t.h"
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#include "ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
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#include "gen_ia32_machine.h"
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#include "ia32_common_transform.h"
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#include "ia32_transform.h"
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#include "ia32_emitter.h"
#include "ia32_map_regs.h"
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#include "ia32_optimize.h"
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#include "ia32_x87.h"
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#include "ia32_dbg_stat.h"
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#include "ia32_finish.h"
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#include "ia32_util.h"
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#include "ia32_fpu.h"
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#include "ia32_architecture.h"
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#ifdef FIRM_GRGEN_BE
#include "ia32_pbqp_transform.h"
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transformer_t be_transformer = TRANSFORMER_DEFAULT;
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#endif

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DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
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/* TODO: ugly */
static set *cur_reg_set = NULL;
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ir_mode         *mode_fpcw       = NULL;
ia32_code_gen_t *ia32_current_cg = NULL;
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/** The current omit-fp state */
static unsigned ia32_curr_fp_ommitted  = 0;
static ir_type *omit_fp_between_type   = NULL;
static ir_type *between_type           = NULL;
static ir_entity *old_bp_ent           = NULL;
static ir_entity *ret_addr_ent         = NULL;
static ir_entity *omit_fp_ret_addr_ent = NULL;

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/**
 * The environment for the intrinsic mapping.
 */
static ia32_intrinsic_env_t intrinsic_env = {
	NULL,    /* the isa */
	NULL,    /* the irg, these entities belong to */
	NULL,    /* entity for __divdi3 library call */
	NULL,    /* entity for __moddi3 library call */
	NULL,    /* entity for __udivdi3 library call */
	NULL,    /* entity for __umoddi3 library call */
};


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typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
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/**
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 * Used to create per-graph unique pseudo nodes.
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 */
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static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
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                                    create_const_node_func func,
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                                    const arch_register_t* reg)
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{
	ir_node *block, *res;

	if(*place != NULL)
		return *place;

	block = get_irg_start_block(cg->irg);
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	res = func(NULL, block);
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	arch_set_irn_register(res, reg);
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	*place = res;

	return res;
}

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/* Creates the unique per irg GP NoReg node. */
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ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
{
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	return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
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	                    &ia32_gp_regs[REG_GP_NOREG]);
}

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ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
{
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	return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
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	                    &ia32_vfp_regs[REG_VFP_NOREG]);
}

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ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
{
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	return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
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	                    &ia32_xmm_regs[REG_XMM_NOREG]);
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}

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ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg)
{
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	return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
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	                    &ia32_gp_regs[REG_GP_UKNWN]);
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}
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ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg)
{
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	return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
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	                    &ia32_vfp_regs[REG_VFP_UKNWN]);
}

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ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg)
{
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	return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
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	                    &ia32_xmm_regs[REG_XMM_UKNWN]);
}

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ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
{
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	return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
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                        &ia32_fp_cw_regs[REG_FPCW]);
}

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/**
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 * Returns the admissible noreg register node for input register pos of node irn.
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 */
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static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
{
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	const arch_register_req_t *req = arch_get_register_req(irn, pos);
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	assert(req != NULL && "Missing register requirements");
	if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
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		return ia32_new_NoReg_gp(cg);
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	if (ia32_cg_config.use_sse2) {
		return ia32_new_NoReg_xmm(cg);
	} else {
		return ia32_new_NoReg_vfp(cg);
	}
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}

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/**************************************************
 *                         _ _              _  __
 *                        | | |            (_)/ _|
 *  _ __ ___  __ _    __ _| | | ___   ___   _| |_
 * | '__/ _ \/ _` |  / _` | | |/ _ \ / __| | |  _|
 * | | |  __/ (_| | | (_| | | | (_) | (__  | | |
 * |_|  \___|\__, |  \__,_|_|_|\___/ \___| |_|_|
 *            __/ |
 *           |___/
 **************************************************/

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static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
		const ir_node *node, int pos)
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{
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	(void) node;
	(void) pos;
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	return arch_no_register_req;
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}
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static arch_irn_class_t ia32_classify(const ir_node *irn)
{
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	arch_irn_class_t classification = 0;
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	assert(is_ia32_irn(irn));
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	if (is_ia32_is_reload(irn))
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		classification |= arch_irn_class_reload;

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	if (is_ia32_is_spill(irn))
		classification |= arch_irn_class_spill;

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	if (is_ia32_is_remat(irn))
		classification |= arch_irn_class_remat;

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	return classification;
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}
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/**
 * The IA32 ABI callback object.
 */
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typedef struct {
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	be_abi_call_flags_bits_t flags;  /**< The call flags. */
	const arch_env_t *aenv;          /**< The architecture environment. */
	ir_graph *irg;                   /**< The associated graph. */
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} ia32_abi_env_t;

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static ir_entity *ia32_get_frame_entity(const ir_node *irn)
{
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	return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
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}

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static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent)
{
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	set_ia32_frame_ent(irn, ent);
}

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static void ia32_set_frame_offset(ir_node *irn, int bias)
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{
	if (get_ia32_frame_ent(irn) == NULL)
		return;
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	if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
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		ia32_code_gen_t *cg = ia32_current_cg;
		int omit_fp = be_abi_omit_fp(cg->birg->abi);
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		if (omit_fp) {
			/* Pop nodes modify the stack pointer before calculating the
			 * destination address, so fix this here
			 */
			bias -= 4;
		}
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	}
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	add_ia32_am_offs_int(irn, bias);
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}

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static int ia32_get_sp_bias(const ir_node *node)
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{
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	if (is_ia32_Call(node))
		return -(int)get_ia32_call_attr_const(node)->pop;

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	if (is_ia32_Push(node))
		return 4;

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	if (is_ia32_Pop(node) || is_ia32_PopMem(node))
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		return -4;
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	return 0;
}

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/**
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 * Generate the routine prologue.
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 *
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 * @param self       The callback object.
 * @param mem        A pointer to the mem node. Update this if you define new memory.
 * @param reg_map    A map mapping all callee_save/ignore/parameter registers to their defining nodes.
 * @param stack_bias Points to the current stack bias, can be modified if needed.
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 *
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 * @return           The register which shall be used as a stack frame base.
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 *
 * All nodes which define registers in @p reg_map must keep @p reg_map current.
 */
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static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
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{
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	ia32_abi_env_t   *env      = self;
	ia32_code_gen_t  *cg       = ia32_current_cg;
	const arch_env_t *arch_env = env->aenv;
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	ia32_curr_fp_ommitted = env->flags.try_omit_fp;
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	if (! env->flags.try_omit_fp) {
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		ir_node  *bl      = get_irg_start_block(env->irg);
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		ir_node  *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
		ir_node  *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
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		ir_node  *noreg   = ia32_new_NoReg_gp(cg);
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		ir_node  *push;
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		/* mark bp register as ignore */
		be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
				get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
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		/* push ebp */
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		push    = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
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		curr_sp = new_r_Proj(bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
		*mem    = new_r_Proj(bl, push, mode_M, pn_ia32_Push_M);
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		/* the push must have SP out register */
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		arch_set_irn_register(curr_sp, arch_env->sp);
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		/* this modifies the stack bias, because we pushed 32bit */
		*stack_bias -= 4;

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		/* move esp to ebp */
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		curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
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		be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
		                             arch_register_req_type_ignore);
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		/* beware: the copy must be done before any other sp use */
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		curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
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		be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
				                     arch_register_req_type_produces_sp);
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		be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
		be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
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		return arch_env->bp;
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	}

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	return arch_env->sp;
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}

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/**
 * Generate the routine epilogue.
 * @param self    The callback object.
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 * @param bl      The block for the epilog
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 * @param mem     A pointer to the mem node. Update this if you define new memory.
 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
 * @return        The register which shall be used as a stack frame base.
 *
 * All nodes which define registers in @p reg_map must keep @p reg_map current.
 */
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static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
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	ia32_abi_env_t   *env      = self;
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	const arch_env_t *arch_env = env->aenv;
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	ir_node          *curr_sp  = be_abi_reg_map_get(reg_map, arch_env->sp);
	ir_node          *curr_bp  = be_abi_reg_map_get(reg_map, arch_env->bp);
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	if (env->flags.try_omit_fp) {
		/* simply remove the stack frame here */
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		curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
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	} else {
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		ir_mode *mode_bp = arch_env->bp->reg_class->mode;
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		if (ia32_cg_config.use_leave) {
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			ir_node *leave;
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			/* leave */
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			leave   = new_bd_ia32_Leave(NULL, bl, curr_bp);
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			curr_bp = new_r_Proj(bl, leave, mode_bp, pn_ia32_Leave_frame);
			curr_sp = new_r_Proj(bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
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		} else {
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			ir_node *pop;

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			/* the old SP is not needed anymore (kill the proj) */
			assert(is_Proj(curr_sp));
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			kill_node(curr_sp);
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			/* copy ebp to esp */
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			curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
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			arch_set_irn_register(curr_sp, arch_env->sp);
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			be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
				                         arch_register_req_type_ignore);
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			/* pop ebp */
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			pop     = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
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			curr_bp = new_r_Proj(bl, pop, mode_bp, pn_ia32_Pop_res);
			curr_sp = new_r_Proj(bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
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			*mem = new_r_Proj(bl, pop, mode_M, pn_ia32_Pop_M);
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		}
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		arch_set_irn_register(curr_sp, arch_env->sp);
		arch_set_irn_register(curr_bp, arch_env->bp);
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	}

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	be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
	be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
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}

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/**
 * Initialize the callback object.
 * @param call The call object.
 * @param aenv The architecture environment.
 * @param irg  The graph with the method.
 * @return     Some pointer. This pointer is passed to all other callback functions as self object.
 */
static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
{
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	ia32_abi_env_t      *env = XMALLOC(ia32_abi_env_t);
	be_abi_call_flags_t  fl  = be_abi_call_get_flags(call);
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	env->flags = fl.bits;
	env->irg   = irg;
	env->aenv  = aenv;
	return env;
}

/**
 * Destroy the callback object.
 * @param self The callback object.
 */
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static void ia32_abi_done(void *self)
{
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	free(self);
}

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/**
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 * Build the between type and entities if not already build.
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 */
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static void ia32_build_between_type(void)
{
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#define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
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	if (! between_type) {
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		ir_type *old_bp_type   = new_type_primitive(IDENT("bp"), mode_Iu);
		ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
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		between_type           = new_type_struct(IDENT("ia32_between_type"));
		old_bp_ent             = new_entity(between_type, IDENT("old_bp"), old_bp_type);
		ret_addr_ent           = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
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		set_entity_offset(old_bp_ent, 0);
		set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
		set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
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		set_type_state(between_type, layout_fixed);
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		omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
		omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);

		set_entity_offset(omit_fp_ret_addr_ent, 0);
		set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
		set_type_state(omit_fp_between_type, layout_fixed);
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	}
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#undef IDENT
}

/**
 * Produces the type which sits between the stack args and the locals on the stack.
 * it will contain the return address and space to store the old base pointer.
 * @return The Firm type modeling the ABI between type.
 */
static ir_type *ia32_abi_get_between_type(void *self)
{
	ia32_abi_env_t *env = self;
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	ia32_build_between_type();
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	return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
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}

/**
 * Return the stack entity that contains the return address.
 */
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ir_entity *ia32_get_return_address_entity(void)
{
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	ia32_build_between_type();
	return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
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}

/**
 * Return the stack entity that contains the frame address.
 */
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ir_entity *ia32_get_frame_address_entity(void)
{
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	ia32_build_between_type();
	return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
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}

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/**
 * Get the estimated cycle count for @p irn.
 *
 * @param self The this pointer.
 * @param irn  The node.
 *
 * @return     The estimated cycle count for this operation
 */
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static int ia32_get_op_estimated_cost(const ir_node *irn)
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{
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	int            cost;
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	ia32_op_type_t op_tp;
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	if (is_Proj(irn))
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		return 0;
	if (!is_ia32_irn(irn))
		return 0;
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	assert(is_ia32_irn(irn));

	cost  = get_ia32_latency(irn);
	op_tp = get_ia32_op_type(irn);

	if (is_ia32_CopyB(irn)) {
		cost = 250;
	}
	else if (is_ia32_CopyB_i(irn)) {
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		int size = get_ia32_copyb_size(irn);
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		cost     = 20 + (int)ceil((4/3) * size);
	}
	/* in case of address mode operations add additional cycles */
	else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
		/*
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			In case of stack access and access to fixed addresses add 5 cycles
			(we assume they are in cache), other memory operations cost 20
			cycles.
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		*/
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		if (is_ia32_use_frame(irn) || (
		    	is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
		    	is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
		    )) {
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			cost += 5;
		} else {
			cost += 20;
		}
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	}

	return cost;
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}

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/**
 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
 *
 * @param irn       The original operation
 * @param i         Index of the argument we want the inverse operation to yield
 * @param inverse   struct to be filled with the resulting inverse op
 * @param obstack   The obstack to use for allocation of the returned nodes array
 * @return          The inverse operation or NULL if operation invertible
 */
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static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
{
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	ir_mode  *mode;
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	ir_mode  *irn_mode;
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	ir_node  *block, *noreg, *nomem;
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	dbg_info *dbg;
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	/* we cannot invert non-ia32 irns */
	if (! is_ia32_irn(irn))
		return NULL;

	/* operand must always be a real operand (not base, index or mem) */
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	if (i != n_ia32_binary_left && i != n_ia32_binary_right)
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		return NULL;

	/* we don't invert address mode operations */
	if (get_ia32_op_type(irn) != ia32_Normal)
		return NULL;

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	/* TODO: adjust for new immediates... */
	ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
	           irn);
	return NULL;

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	block    = get_nodes_block(irn);
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	mode     = get_irn_mode(irn);
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	irn_mode = get_irn_mode(irn);
	noreg    = get_irn_n(irn, 0);
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	nomem    = new_NoMem();
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	dbg      = get_irn_dbg_info(irn);
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	/* initialize structure */
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	inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
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	inverse->costs = 0;
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	inverse->n     = 1;
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	switch (get_ia32_irn_opcode(irn)) {
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		case iro_ia32_Add:
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			if (get_ia32_immop_type(irn) == ia32_ImmConst) {
				/* we have an add with a const here */
				/* invers == add with negated const */
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				inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
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				inverse->costs   += 1;
				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
				set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
				set_ia32_commutative(inverse->nodes[0]);
			}
			else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
				/* we have an add with a symconst here */
				/* invers == sub with const */
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				inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
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				inverse->costs   += 2;
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				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
			}
			else {
				/* normal add: inverse == sub */
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				inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
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				inverse->costs   += 2;
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			}
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#endif
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			break;
		case iro_ia32_Sub:
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			if (get_ia32_immop_type(irn) != ia32_ImmNone) {
				/* we have a sub with a const/symconst here */
				/* invers == add with this const */
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				inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
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				inverse->costs   += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
			}
			else {
				/* normal sub */
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				if (i == n_ia32_binary_left) {
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					inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
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				}
				else {
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					inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
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				}
				inverse->costs += 1;
			}
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#endif
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			break;
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		case iro_ia32_Xor:
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			if (get_ia32_immop_type(irn) != ia32_ImmNone) {
				/* xor with const: inverse = xor */
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				inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
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				inverse->costs   += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
			}
			else {
				/* normal xor */
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				inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
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				inverse->costs   += 1;
			}
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#endif
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			break;
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		case iro_ia32_Not: {
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			inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
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			inverse->costs   += 1;
			break;
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		}
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		case iro_ia32_Neg: {
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			inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
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			inverse->costs   += 1;
			break;
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		}
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		default:
			/* inverse operation not supported */
			return NULL;
	}

	return inverse;
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}

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static ir_mode *get_spill_mode_mode(const ir_mode *mode)
{
	if(mode_is_float(mode))
		return mode_D;

	return mode_Iu;
}

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/**
 * Get the mode that should be used for spilling value node
 */
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static ir_mode *get_spill_mode(const ir_node *node)
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{
	ir_mode *mode = get_irn_mode(node);
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	return get_spill_mode_mode(mode);
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}

/**
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 * Checks whether an addressmode reload for a node with mode mode is compatible
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 * with a spillslot of mode spill_mode
 */
static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
{
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	return !mode_is_float(mode) || mode == spillmode;
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}

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/**
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 * Check if irn can load its operand at position i from memory (source addressmode).
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 * @param irn    The irn to be checked
 * @param i      The operands position
 * @return Non-Zero if operand can be loaded
 */
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static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
{
	ir_node       *op        = get_irn_n(irn, i);
	const ir_mode *mode      = get_irn_mode(op);
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	const ir_mode *spillmode = get_spill_mode(op);
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	if (!is_ia32_irn(irn)                              ||  /* must be an ia32 irn */
	    get_ia32_op_type(irn) != ia32_Normal           ||  /* must not already be a addressmode irn */
	    !ia32_is_spillmode_compatible(mode, spillmode) ||
	    is_ia32_use_frame(irn))                            /* must not already use frame */
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		return 0;

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	switch (get_ia32_am_support(irn)) {
		case ia32_am_none:
			return 0;

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		case ia32_am_unary:
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			if (i != n_ia32_unary_op)
				return 0;
			break;
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		case ia32_am_binary:
			switch (i) {
				case n_ia32_binary_left: {
					const arch_register_req_t *req;
					if (!is_ia32_commutative(irn))
						return 0;

					/* we can't swap left/right for limited registers
					 * (As this (currently) breaks constraint handling copies)
					 */
					req = get_ia32_in_req(irn, n_ia32_binary_left);
					if (req->type & arch_register_req_type_limited)
						return 0;
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					break;
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				}

				case n_ia32_binary_right:
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					break;
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				default:
					return 0;
			}
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			break;
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		default:
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			panic("Unknown AM type");
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	}
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	/* HACK: must not already use "real" memory.
	 * This can happen for Call and Div */
	if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
		return 0;

	return 1;
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}

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static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
                                        unsigned int i)
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{
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	ir_mode *load_mode;
	ir_mode *dest_op_mode;

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	assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
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	set_ia32_op_type(irn, ia32_AddrModeS);
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	load_mode    = get_irn_mode(get_irn_n(irn, i));
	dest_op_mode = get_ia32_ls_mode(irn);
	if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
		set_ia32_ls_mode(irn, load_mode);
	}
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	set_ia32_use_frame(irn);
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	set_ia32_need_stackent(irn);
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	if (i == n_ia32_binary_left                    &&
	    get_ia32_am_support(irn) == ia32_am_binary &&
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	    /* immediates are only allowed on the right side */
	    !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
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		ia32_swap_left_right(irn);
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		i = n_ia32_binary_right;
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	}
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	assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));

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	set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
	set_irn_n(irn, n_ia32_mem,  spill);
	set_irn_n(irn, i,           ia32_get_admissible_noreg(ia32_current_cg, irn, i));
	set_ia32_is_reload(irn);
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}

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static const be_abi_callbacks_t ia32_abi_callbacks = {
	ia32_abi_init,
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	ia32_abi_done,
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	ia32_abi_get_between_type,
	ia32_abi_prologue,
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	ia32_abi_epilogue
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};

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/* register allocator interface */
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static const arch_irn_ops_t ia32_irn_ops = {
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	get_ia32_in_req,
	get_ia32_out_req,
	ia32_classify,
	ia32_get_frame_entity,
	ia32_set_frame_entity,
	ia32_set_frame_offset,
	ia32_get_sp_bias,
	ia32_get_inverse,
	ia32_get_op_estimated_cost,
	ia32_possible_memory_operand,
	ia32_perform_memory_operand,
};

/* special register allocator interface for SwitchJmp
   as it possibly has a WIDE range of Proj numbers.
   We don't want to allocate output for register constraints for
   all these. */
static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
	/* Note: we also use SwitchJmp_out_req for the inputs too:
	   This is because the bearch API has a conceptual problem at the moment.
	   Querying for negative proj numbers which can happen for switchs
	   isn't possible and will result in inputs getting queried */
	get_ia32_SwitchJmp_out_req,
	get_ia32_SwitchJmp_out_req,
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	ia32_classify,
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	ia32_get_frame_entity,
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	ia32_set_frame_entity,
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	ia32_set_frame_offset,
	ia32_get_sp_bias,
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	ia32_get_inverse,
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	ia32_get_op_estimated_cost,
	ia32_possible_memory_operand,
	ia32_perform_memory_operand,
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};

/**************************************************
 *                _                         _  __
 *               | |                       (_)/ _|
 *   ___ ___   __| | ___  __ _  ___ _ __    _| |_
 *  / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \  | |  _|
 * | (_| (_) | (_| |  __/ (_| |  __/ | | | | | |
 *  \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
 *                        __/ |
 *                       |___/
 **************************************************/

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static ir_entity *mcount = NULL;

#define ID(s) new_id_from_chars(s, sizeof(s) - 1)

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static void ia32_before_abi(void *self)
{
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	lower_mode_b_config_t lower_mode_b_config = {
		mode_Iu,  /* lowered mode */
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		mode_Bu,  /* preferred mode for set */
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		0,        /* don't lower direct compares */
	};
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	ia32_code_gen_t *cg = self;
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	ir_lower_mode_b(cg->irg, &lower_mode_b_config);
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	if (cg->dump)
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		be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
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	if (cg->gprof) {
		if (mcount == NULL) {
			ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
			mcount = new_entity(get_glob_type(), ID("mcount"), tp);
			/* FIXME: enter the right ld_ident here */
			set_entity_ld_ident(mcount, get_entity_ident(mcount));
			set_entity_visibility(mcount, visibility_external_allocated);
		}
		instrument_initcall(cg->irg, mcount);
	}
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}

/**
 * Transforms the standard firm graph into
 * an ia32 firm graph
 */
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static void ia32_prepare_graph(void *self)
{
	ia32_code_gen_t *cg  = self;
	ir_graph        *irg = cg->irg;
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	switch (be_transformer) {
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	case TRANSFORMER_DEFAULT:
		/* transform remaining nodes into assembler instructions */
		ia32_transform_graph(cg);
		break;
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#ifdef FIRM_GRGEN_BE
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	case TRANSFORMER_PBQP:
	case TRANSFORMER_RAND:
		/* transform nodes into assembler instructions by PBQP magic */
		ia32_transform_graph_by_pbqp(cg);
		break;
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#endif
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	default:
		panic("invalid transformer");
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	}

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	/* do local optimizations (mainly CSE) */
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	optimize_graph_df(cg->irg);
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	if (cg->dump)
		be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);