ia32_optimize.c

/*
 * This file is part of libFirm.
 * Copyright (C) 2012 University of Karlsruhe.
 */

/**
 * @file
 * @brief       Implements several optimizations for IA32.
 * @author      Matthias Braun, Christian Wuerdig
 */
#include "irnode.h"
#include "irprog_t.h"
#include "ircons.h"
#include "irtools.h"
#include "firm_types.h"
#include "iredges.h"
#include "tv.h"
#include "irgmod.h"
#include "irgwalk.h"
#include "heights.h"
#include "irprintf.h"
#include "irdump.h"
#include "panic.h"
#include "firmstat_t.h"

#include "be_t.h"
#include "beabi.h"
#include "benode.h"
#include "besched.h"
#include "bepeephole.h"

#include "ia32_new_nodes.h"
#include "ia32_optimize.h"
#include "bearch_ia32_t.h"
#include "gen_ia32_regalloc_if.h"
#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
#include "ia32_architecture.h"

DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

static void copy_mark(const ir_node *old, ir_node *newn)
{
	if (is_ia32_is_reload(old))
		set_ia32_is_reload(newn);
	if (is_ia32_is_spill(old))
		set_ia32_is_spill(newn);
	if (is_ia32_is_remat(old))
		set_ia32_is_remat(newn);
}

typedef enum produces_flag_t {
	produces_no_flag,
	produces_zero_sign,
	produces_zero_in_carry
} produces_flag_t;

/**
 * Return which usable flag the given node produces about the result.
 * That is zero (ZF) and sign(SF).
 * We do not check for carry (CF) or overflow (OF).
 *
 * @param node  the node to check
 * @param pn    the projection number of the used result
 */
static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
{
	if (!is_ia32_irn(node))
		return produces_no_flag;

	ir_node *count;

	switch (get_ia32_irn_opcode(node)) {
		case iro_ia32_Add:
		case iro_ia32_Adc:
		case iro_ia32_And:
		case iro_ia32_Or:
		case iro_ia32_Xor:
		case iro_ia32_Sub:
		case iro_ia32_Sbb:
		case iro_ia32_Neg:
		case iro_ia32_Inc:
		case iro_ia32_Dec:
			break;

		case iro_ia32_ShlD:
		case iro_ia32_ShrD:
			assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
			count = get_irn_n(node, n_ia32_ShlD_count);
			goto check_shift_amount;

		case iro_ia32_Shl:
		case iro_ia32_Shr:
		case iro_ia32_Sar:
			assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
					&& (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
			count = get_irn_n(node, n_ia32_Shl_count);
check_shift_amount:
			/* when shift count is zero the flags are not affected, so we can only
			 * do this for constants != 0 */
			if (!is_ia32_Immediate(count))
				return produces_no_flag;

			const ia32_immediate_attr_t *imm_attr = get_ia32_immediate_attr_const(count);
			if (imm_attr->entity != NULL)
				return produces_no_flag;
			if ((imm_attr->offset & 0x1f) == 0)
				return produces_no_flag;
			break;

		case iro_ia32_Mul:
			return pn == pn_ia32_Mul_res_high ?
				produces_zero_in_carry : produces_no_flag;

		default:
			return produces_no_flag;
	}

	return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
}

/**
 * Replace Cmp(x, 0) by a Test(x, x)
 */
static void peephole_ia32_Cmp(ir_node *const node)
{
	if (get_ia32_op_type(node) != ia32_Normal)
		return;

	ir_node *const right = get_irn_n(node, n_ia32_Cmp_right);
	if (!is_ia32_Immediate(right))
		return;

	ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
	if (imm->entity != NULL || imm->offset != 0)
		return;

	dbg_info *const dbgi         = get_irn_dbg_info(node);
	ir_node  *const block        = get_nodes_block(node);
	ir_graph *const irg          = get_Block_irg(block);
	ir_node  *const noreg        = ia32_new_NoReg_gp(irg);
	ir_node  *const nomem        = get_irg_no_mem(irg);
	ir_node  *const op           = get_irn_n(node, n_ia32_Cmp_left);
	int       const ins_permuted = get_ia32_attr(node)->data.ins_permuted;

	ir_mode *const ls_mode = get_ia32_ls_mode(node);
	ir_node *const test    = get_mode_size_bits(ls_mode) == 8
		? new_bd_ia32_Test_8bit(dbgi, block, noreg, noreg, nomem, op, op, ins_permuted)
		: new_bd_ia32_Test     (dbgi, block, noreg, noreg, nomem, op, op, ins_permuted);
	set_ia32_ls_mode(test, ls_mode);

	arch_register_t const *const reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
	arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);

	foreach_out_edge_safe(node, edge) {
		ir_node *const user = get_edge_src_irn(edge);

		if (is_Proj(user))
			exchange(user, test);
	}

	sched_add_before(node, test);
	copy_mark(node, test);
	be_peephole_exchange(node, test);
}

/**
 * Peephole optimization for Test instructions.
 * - Remove the Test, if an appropriate flag was produced which is still live
 * - Change a Test(x, c) to 8Bit, if 0 <= c < 128 (3 byte shorter opcode)
 */
static void peephole_ia32_Test(ir_node *node)
{
	ir_node *left  = get_irn_n(node, n_ia32_Test_left);
	ir_node *right = get_irn_n(node, n_ia32_Test_right);

	if (left == right) { /* we need a test for 0 */
		ir_node *block = get_nodes_block(node);
		if (get_nodes_block(left) != block)
			return;

		int      pn = pn_ia32_res;
		ir_node *op = left;
		if (is_Proj(op)) {
			pn = get_Proj_proj(op);
			op = get_Proj_pred(op);
		}

		/* walk schedule up and abort when we find left or some other node
		 * destroys the flags */
		ir_node *schedpoint = node;
		for (;;) {
			schedpoint = sched_prev(schedpoint);
			if (schedpoint == op)
				break;
			if (arch_irn_is(schedpoint, modify_flags))
				return;
			if (schedpoint == block)
				panic("couldn't find left");
		}

		produces_flag_t produced = check_produces_zero_sign(op, pn);
		if (produced == produces_no_flag)
			return;

		/* make sure users only look at the sign/zero flag */
		foreach_out_edge(node, edge) {
			ir_node *user = get_edge_src_irn(edge);
			if (is_ia32_CMovcc(user) || is_ia32_Jcc(user) ||
			    is_ia32_Setcc(user) || is_ia32_SetccMem(user)) {
				x86_condition_code_t  cc  = get_ia32_condcode(user);

				if (cc == x86_cc_equal || cc == x86_cc_not_equal)
					continue;
				if (produced == produces_zero_sign
					&& (cc == x86_cc_sign || cc == x86_cc_not_sign)) {
					continue;
				}
			}
			return;
		}

		ir_mode *op_mode = get_ia32_ls_mode(op);
		if (op_mode == NULL)
			op_mode = get_irn_mode(op);

		/* Make sure we operate on the same bit size */
		if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
			return;

		if (produced == produces_zero_in_carry) {
			/* patch users to look at the carry instead of the zero flag */
			foreach_out_edge(node, edge) {
				ir_node              *user = get_edge_src_irn(edge);
				x86_condition_code_t  cc   = get_ia32_condcode(user);

				switch (cc) {
				case x86_cc_equal:     cc = x86_cc_above_equal; break;
				case x86_cc_not_equal: cc = x86_cc_below;       break;
				default: panic("unexpected pn");
				}
				set_ia32_condcode(user, cc);
			}
		}

		if (get_irn_mode(op) != mode_T) {
			set_irn_mode(op, mode_T);

			/* If there are other users, reroute them to result proj */
			if (get_irn_n_edges(op) != 2) {
				ir_node *res = new_r_Proj(op, ia32_mode_gp, pn_ia32_res);
				edges_reroute_except(op, res, res);
			}
		} else {
			if (get_irn_n_edges(left) == 2)
				kill_node(left);
		}

		ir_mode *flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
		ir_node *flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
		arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);

		assert(get_irn_mode(node) != mode_T);

		be_peephole_exchange(node, flags_proj);
	} else if (is_ia32_Immediate(right)) {
		ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);

		/* A test with an entity is rather strange, but better safe than sorry */
		if (imm->entity != NULL)
			return;

		/*
		 * We have to take care that we end up with the same sign flag:
		 * testl(128, 128) -> SF=0
		 * testb(128, 128) -> SF=1
		 */
		unsigned offset = imm->offset;
		if (get_ia32_op_type(node) == ia32_AddrModeS) {
			ia32_attr_t *const attr = get_ia32_attr(node);
			ir_graph    *const irg  = get_irn_irg(node);

			if ((offset & 0xFFFFFF80) == 0) {
				/* attr->am_offs += 0; */
			} else if ((offset & 0xFFFF80FF) == 0) {
				ir_node *imm_node = ia32_create_Immediate(irg, NULL, offset >>  8);
				set_irn_n(node, n_ia32_Test_right, imm_node);
				attr->am_offs += 1;
			} else if ((offset & 0xFF80FFFF) == 0) {
				ir_node *imm_node = ia32_create_Immediate(irg, NULL, offset >> 16);
				set_irn_n(node, n_ia32_Test_right, imm_node);
				attr->am_offs += 2;
			} else if ((offset & 0x00FFFFFF) == 0) {
				ir_node *imm_node = ia32_create_Immediate(irg, NULL, offset >> 24);
				set_irn_n(node, n_ia32_Test_right, imm_node);
				attr->am_offs += 3;
			} else {
				return;
			}
		} else if ((offset & 0xFFFFFF80) == 0) {
			arch_register_t const* const reg = arch_get_irn_register(left);

			if (reg != &ia32_registers[REG_EAX] &&
					reg != &ia32_registers[REG_EBX] &&
					reg != &ia32_registers[REG_ECX] &&
					reg != &ia32_registers[REG_EDX]) {
				return;
			}
		} else {
			return;
		}

		/* Technically we should build a Test8Bit because of the register
		 * constraints, but nobody changes registers at this point anymore. */
		set_ia32_ls_mode(node, mode_Bu);
	}
}

/**
 * AMD Athlon works faster when RET is not destination of
 * conditional jump or directly preceded by other jump instruction.
 * Can be avoided by placing a Rep prefix before the return.
 */
static void peephole_ia32_Return(ir_node *node)
{
	if (!ia32_cg_config.use_pad_return)
		return;

	/* check if this return is the first on the block */
	sched_foreach_reverse_before(node, irn) {
		if (is_Phi(irn) || be_is_Start(irn))
			continue;
		/* arg, IncSP 0 nodes might occur, ignore these */
		if (be_is_IncSP(irn) && be_get_IncSP_offset(irn) == 0)
			continue;
		return;
	}

	/* ensure, that the 3 byte return is generated */
	be_Return_set_emit_pop(node, 1);
}

/* only optimize up to 48 stores behind IncSPs */
#define MAXPUSH_OPTIMIZE    48

/**
 * Tries to create Push's from IncSP, Store combinations.
 * The Stores are replaced by Push's, the IncSP is modified
 * (possibly into IncSP 0, but not removed).
 */
static void peephole_IncSP_Store_to_push(ir_node *irn)
{
	int inc_ofs = be_get_IncSP_offset(irn);
	if (inc_ofs < 4)
		return;

	int      maxslot                  = -1;
	ir_node *stores[MAXPUSH_OPTIMIZE];

	memset(stores, 0, sizeof(stores));

	/*
	 * We first walk the schedule after the IncSP node as long as we find
	 * suitable Stores that could be transformed to a Push.
	 * We save them into the stores array which is sorted by the frame offset/4
	 * attached to the node
	 */
	sched_foreach_after(irn, node) {
		/* it has to be a Store */
		if (!is_ia32_Store(node))
			break;

		/* it has to use our sp value */
		if (get_irn_n(node, n_ia32_base) != irn)
			continue;
		/* Store has to be attached to NoMem */
		ir_node *mem = get_irn_n(node, n_ia32_mem);
		if (!is_NoMem(mem))
			continue;

		/* unfortunately we can't support the full AMs possible for push at the
		 * moment. TODO: fix this */
		if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
			break;

		int offset = get_ia32_am_offs_int(node);
		/* we should NEVER access uninitialized stack BELOW the current SP */
		assert(offset >= 0);

		/* storing at half-slots is bad */
		if ((offset & 3) != 0)
			break;

		if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
			continue;

		int storeslot = offset >> 2;

		/* storing into the same slot twice is bad (and shouldn't happen...) */
		if (stores[storeslot] != NULL)
			break;

		stores[storeslot] = node;
		if (storeslot > maxslot)
			maxslot = storeslot;
	}

	ir_node *curr_sp = irn;
	int      i;
	for (i = -1; i < maxslot; ++i) {
		if (stores[i + 1] == NULL)
			break;
	}

	/* walk through the Stores and create Pushs for them */
	ir_node  *block      = get_nodes_block(irn);
	ir_mode  *spmode     = get_irn_mode(irn);
	ir_graph *irg        = get_irn_irg(irn);
	ir_node  *first_push = NULL;
	for (; i >= 0; --i) {
		ir_node               *store = stores[i];
		ir_node               *noreg = ia32_new_NoReg_gp(irg);
		ir_node               *val   = get_irn_n(store, n_ia32_unary_op);
		ir_node               *mem   = get_irn_n(store, n_ia32_mem);
		const arch_register_t *spreg = arch_get_irn_register(curr_sp);

		ir_node *push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
		                                 mem, val, curr_sp);
		set_ia32_ls_mode(push, ia32_mode_gp);
		copy_mark(store, push);

		if (first_push == NULL)
			first_push = push;

		sched_add_after(skip_Proj(curr_sp), push);

		/* create stackpointer Proj */
		curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
		arch_set_irn_register(curr_sp, spreg);

		/* create memory Proj */
		ir_node *mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);

		/* rewire Store Projs */
		foreach_out_edge_safe(store, edge) {
			ir_node *proj = get_edge_src_irn(edge);
			if (!is_Proj(proj))
				continue;
			switch (get_Proj_proj(proj)) {
			case pn_ia32_Store_M:
				exchange(proj, mem_proj);
				break;
			default:
				panic("unexpected Proj on Store->IncSp");
			}
		}

		/* use the memproj now */
		be_peephole_exchange(store, push);

		inc_ofs -= 4;
	}

	foreach_out_edge_safe(irn, edge) {
		ir_node *const src = get_edge_src_irn(edge);

		if (src == first_push)
			continue;

		const int pos = get_edge_src_pos(edge);
		set_irn_n(src, pos, curr_sp);
	}

	be_set_IncSP_offset(irn, inc_ofs);
}

/**
 * Tries to create Pops from Load, IncSP combinations.
 * The Loads are replaced by Pops, the IncSP is modified
 * (possibly into IncSP 0, but not removed).
 */
static void peephole_Load_IncSP_to_pop(ir_node *irn)
{

	int inc_ofs = -be_get_IncSP_offset(irn);
	if (inc_ofs < 4)
		return;

	ir_node  *loads[MAXPUSH_OPTIMIZE];
	unsigned  regmask                 = 0;
	unsigned  copymask                = ~0;

	memset(loads, 0, sizeof(loads));

	/*
	 * We first walk the schedule before the IncSP node as long as we find
	 * suitable Loads that could be transformed to a Pop.
	 * We save them into the stores array which is sorted by the frame offset/4
	 * attached to the node
	 */
	int      maxslot = -1;
	ir_node *pred_sp = be_get_IncSP_pred(irn);
	sched_foreach_reverse_before(irn, node) {
		/* it has to be a Load */
		if (!is_ia32_Load(node)) {
			if (be_is_Copy(node)) {
				const arch_register_t *dreg = arch_get_irn_register(node);
				if (dreg->reg_class != &ia32_reg_classes[CLASS_ia32_gp]) {
					/* not a GP copy, ignore */
					continue;
				}
				const arch_register_t *sreg = arch_get_irn_register(be_get_Copy_op(node));
				if (regmask & copymask & (1 << sreg->index)) {
					break;
				}
				if (regmask & copymask & (1 << dreg->index)) {
					break;
				}
				/* we CAN skip Copies if neither the destination nor the source
				 * is not in our regmask, ie none of our future Pop will overwrite it */
				regmask |= (1 << dreg->index) | (1 << sreg->index);
				copymask &= ~((1 << dreg->index) | (1 << sreg->index));
				continue;
			}
			break;
		}

		/* it has to use our predecessor sp value */
		if (get_irn_n(node, n_ia32_base) != pred_sp) {
			/* it would be ok if this load does not use a Pop result,
			 * but we do not check this */
			break;
		}

		/* should have NO index */
		if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
			break;

		int offset = get_ia32_am_offs_int(node);
		/* we should NEVER access uninitialized stack BELOW the current SP */
		assert(offset >= 0);

		/* storing at half-slots is bad */
		if ((offset & 3) != 0)
			break;

		if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
			continue;
		/* ignore those outside the possible windows */
		if (offset > inc_ofs - 4)
			continue;
		int loadslot = offset >> 2;

		/* loading from the same slot twice is bad (and shouldn't happen...) */
		if (loads[loadslot] != NULL)
			break;

		const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
		if (regmask & (1 << dreg->index)) {
			/* this register is already used */
			break;
		}
		regmask |= 1 << dreg->index;

		loads[loadslot] = node;
		if (loadslot > maxslot)
			maxslot = loadslot;
	}

	if (maxslot < 0)
		return;

	/* find the first slot */
	int i;
	for (i = maxslot; i >= 0; --i) {
		ir_node *load = loads[i];

		if (load == NULL)
			break;
	}

	int ofs = inc_ofs - (maxslot + 1) * 4;
	inc_ofs = (i + 1) * 4;

	/* create a new IncSP if needed */
	const arch_register_t *esp   = &ia32_registers[REG_ESP];
	ir_node               *const   block = get_nodes_block(irn);
	if (inc_ofs > 0) {
		pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
		sched_add_before(irn, pred_sp);
	}

	/* walk through the Loads and create Pops for them */
	for (++i; i <= maxslot; ++i) {
		ir_node               *load = loads[i];
		ir_node               *mem  = get_irn_n(load, n_ia32_mem);
		const arch_register_t *reg  = arch_get_irn_register_out(load, pn_ia32_Load_res);

		ir_node *pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
		arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
		set_ia32_ls_mode(pop, ia32_mode_gp);

		copy_mark(load, pop);

		/* create stackpointer Proj */
		pred_sp = new_r_Proj(pop, ia32_mode_gp, pn_ia32_Pop_stack);
		arch_set_irn_register(pred_sp, esp);

		sched_add_before(irn, pop);

		/* rewire now */
		foreach_out_edge_safe(load, edge) {
			ir_node *proj = get_edge_src_irn(edge);

			set_Proj_pred(proj, pop);
		}

		/* we can remove the Load now */
		sched_remove(load);
		kill_node(load);
	}

	be_set_IncSP_offset(irn, -ofs);
	be_set_IncSP_pred(irn, pred_sp);
}


/**
 * Find a free GP register if possible, else return NULL.
 */
static const arch_register_t *get_free_gp_reg(ir_graph *irg)
{
	be_irg_t *birg = be_birg_from_irg(irg);

	for (int i = 0; i < N_ia32_gp_REGS; ++i) {
		const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
		if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
			continue;

		if (be_peephole_get_value(reg->global_index) == NULL)
			return reg;
	}

	return NULL;
}

/**
 * Creates a Pop instruction before the given schedule point.
 *
 * @param dbgi        debug info
 * @param block       the block
 * @param stack       the previous stack value
 * @param schedpoint  the new node is added before this node
 * @param reg         the register to pop
 *
 * @return the new stack value
 */
static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
                           ir_node *stack, ir_node *schedpoint,
                           const arch_register_t *reg)
{
	const arch_register_t *esp = &ia32_registers[REG_ESP];
	ir_graph              *irg = get_irn_irg(block);

	ir_node *pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
	set_ia32_ls_mode(pop, ia32_mode_gp);

	stack = new_r_Proj(pop, ia32_mode_gp, pn_ia32_Pop_stack);
	arch_set_irn_register(stack, esp);
	ir_node *val = new_r_Proj(pop, ia32_mode_gp, pn_ia32_Pop_res);
	arch_set_irn_register(val, reg);

	sched_add_before(schedpoint, pop);

	ir_node *in[1] = { val };
	ir_node *keep  = be_new_Keep(block, 1, in);
	sched_add_before(schedpoint, keep);

	return stack;
}

/**
 * Optimize an IncSp by replacing it with Push/Pop.
 */
static void peephole_be_IncSP(ir_node *node)
{
	const arch_register_t *esp = &ia32_registers[REG_ESP];

	/* first optimize incsp->incsp combinations */
	node = be_peephole_IncSP_IncSP(node);

	/* transform IncSP->Store combinations to Push where possible */
	peephole_IncSP_Store_to_push(node);

	/* transform Load->IncSP combinations to Pop where possible */
	peephole_Load_IncSP_to_pop(node);

	if (arch_get_irn_register(node) != esp)
		return;

	/* replace IncSP -4 by Pop freereg when possible */
	int offset = be_get_IncSP_offset(node);
	if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
	    (offset != -4 || ia32_cg_config.use_add_esp_4) &&
	    (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
	    (offset != +8 || ia32_cg_config.use_sub_esp_8))
		return;

	ir_node *stack;

	if (offset < 0) {
		/* we need a free register for pop */
		const arch_register_t *reg = get_free_gp_reg(get_irn_irg(node));
		if (reg == NULL)
			return;

		dbg_info *dbgi  = get_irn_dbg_info(node);
		ir_node  *block = get_nodes_block(node);

		stack = be_get_IncSP_pred(node);
		stack = create_pop(dbgi, block, stack, node, reg);

		if (offset == -8) {
			stack = create_pop(dbgi, block, stack, node, reg);
		}
	} else {
		dbg_info *dbgi  = get_irn_dbg_info(node);
		ir_node  *block = get_nodes_block(node);

		stack = be_get_IncSP_pred(node);
		stack = new_bd_ia32_PushEax(dbgi, block, stack);
		arch_set_irn_register(stack, esp);
		sched_add_before(node, stack);

		if (offset == +8) {
			stack = new_bd_ia32_PushEax(dbgi, block, stack);
			arch_set_irn_register(stack, esp);
			sched_add_before(node, stack);
		}
	}

	be_peephole_exchange(node, stack);
}

/**
 * Peephole optimization for ia32_Const's
 */
static void peephole_ia32_Const(ir_node *node)
{
	const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);

	/* try to transform a mov 0, reg to xor reg reg */
	if (attr->offset != 0 || attr->entity != NULL)
		return;
	if (ia32_cg_config.use_mov_0)
		return;
	/* xor destroys the flags, so no-one must be using them */
	if (be_peephole_get_value(REG_EFLAGS) != NULL)
		return;

	const arch_register_t *reg = arch_get_irn_register(node);
	assert(be_peephole_get_reg_value(reg) == NULL);

	ir_node  *block = get_nodes_block(node);
	dbg_info *dbgi  = get_irn_dbg_info(node);
	ir_node  *xorn  = new_bd_ia32_Xor0(dbgi, block);
	arch_set_irn_register(xorn, reg);

	sched_add_before(node, xorn);

	copy_mark(node, xorn);
	be_peephole_exchange(node, xorn);
}

static inline int is_noreg(const ir_node *node)
{
	return is_ia32_NoReg_GP(node);
}

ir_node *ia32_immediate_from_long(ir_graph *const irg, long const val)
{
	ir_node *start_block = get_irg_start_block(irg);
	ir_node *immediate   = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, val);
	arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);

	return immediate;
}

static ir_node *create_immediate_from_am(const ir_node *node)
{
	ir_node           *block            = get_nodes_block(node);
	int                offset           = get_ia32_am_offs_int(node);
	const ia32_attr_t *attr             = get_ia32_attr_const(node);
	int                sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
	ir_entity         *entity           = get_ia32_am_ent(node);

	ir_node *res = new_bd_ia32_Immediate(NULL, block, entity, sc_no_pic_adjust, offset);
	arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
	return res;
}

static int is_am_one(const ir_node *node)
{
	int        offset  = get_ia32_am_offs_int(node);
	ir_entity *entity  = get_ia32_am_ent(node);

	return offset == 1 && entity == NULL;
}

static int is_am_minus_one(const ir_node *node)
{
	int        offset  = get_ia32_am_offs_int(node);
	ir_entity *entity  = get_ia32_am_ent(node);

	return offset == -1 && entity == NULL;
}

/**
 * Transforms a LEA into an Add or SHL if possible.
 */
static void peephole_ia32_Lea(ir_node *node)
{
	assert(is_ia32_Lea(node));

	/* we can only do this if it is allowed to clobber the flags */
	if (be_peephole_get_value(REG_EFLAGS) != NULL)
		return;

	ir_node *base  = get_irn_n(node, n_ia32_Lea_base);
	ir_node *index = get_irn_n(node, n_ia32_Lea_index);
	const arch_register_t *base_reg;
	const arch_register_t *index_reg;

	if (is_noreg(base)) {
		base     = NULL;
		base_reg = NULL;
	} else {
		base_reg = arch_get_irn_register(base);
	}
	if (is_noreg(index)) {
		index     = NULL;
		index_reg = NULL;
	} else {
		index_reg = arch_get_irn_register(index);
	}

	if (base == NULL && index == NULL) {
		/* we shouldn't construct these in the first place... */
#ifdef DEBUG_libfirm
		ir_fprintf(stderr, "Optimization warning: found immediate only lea\n");
#endif
		return;
	}

	const arch_register_t *out_reg        = arch_get_irn_register(node);
	int                    scale          = get_ia32_am_scale(node);
	int                    has_immediates;
	ir_node               *op1;
	ir_node               *op2;
	assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
	/* check if we have immediates values (frame entities should already be
	 * expressed in the offsets) */
	if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_ent(node) != NULL) {
		has_immediates = 1;
	} else {
		has_immediates = 0;
	}

	/* we can transform leas where the out register is the same as either the
	 * base or index register back to an Add or Shl */
	if (out_reg == base_reg) {
		if (index == NULL) {
#ifdef DEBUG_libfirm
			if (!has_immediates) {
				ir_fprintf(stderr, "Optimization warning: found lea which is "
				           "just a copy\n");
			}
#endif
			op1 = base;
			goto make_add_immediate;
		}
		if (scale == 0 && !has_immediates) {