lower_dw.c

/*
 * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

/**
 * @file
 * @brief   Lower Double word operations, ie 64bit -> 32bit, 32bit -> 16bit etc.
 * @date    8.10.2004
 * @author  Michael Beck
 * @version $Id$
 */
#include "config.h"

#include <string.h>
#include <stdlib.h>
#include <stdbool.h>
#include <assert.h>

#include "error.h"
#include "lowering.h"
#include "irnode_t.h"
#include "irgraph_t.h"
#include "irmode_t.h"
#include "iropt_t.h"
#include "irgmod.h"
#include "tv_t.h"
#include "dbginfo_t.h"
#include "iropt_dbg.h"
#include "irflag_t.h"
#include "firmstat.h"
#include "irgwalk.h"
#include "ircons.h"
#include "irflag.h"
#include "irtools.h"
#include "debug.h"
#include "set.h"
#include "pmap.h"
#include "pdeq.h"
#include "irdump.h"
#include "array_t.h"
#include "irpass_t.h"

typedef struct lower_env_t lower_env_t;

/**
 * The type of a lower function.
 *
 * @param node   the node to be lowered
 * @param env    the lower environment
 */
typedef void (*lower_func)(ir_node *node, ir_mode *mode, lower_env_t *env);

/** A map from (op, imode, omode) to Intrinsic functions entities. */
static set *intrinsic_fkt;

/** A map from (imode, omode) to conv function types. */
static set *conv_types;

/** A map from a method type to its lowered type. */
static pmap *lowered_type;

/** The types for the binop and unop intrinsics. */
static ir_type *binop_tp_u, *binop_tp_s, *unop_tp_u, *unop_tp_s, *shiftop_tp_u, *shiftop_tp_s, *tp_s, *tp_u;

/** the debug handle */
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)

/**
 * An entry in the (op, imode, omode) -> entity map.
 */
typedef struct op_mode_entry {
	const ir_op   *op;    /**< the op */
	const ir_mode *imode; /**< the input mode */
	const ir_mode *omode; /**< the output mode */
	ir_entity     *ent;   /**< the associated entity of this (op, imode, omode) triple */
} op_mode_entry_t;

/**
 * An entry in the (imode, omode) -> tp map.
 */
typedef struct conv_tp_entry {
	const ir_mode *imode; /**< the input mode */
	const ir_mode *omode; /**< the output mode */
	ir_type       *mtd;   /**< the associated method type of this (imode, omode) pair */
} conv_tp_entry_t;

/**
 * Every double word node will be replaced,
 * we need some store to hold the replacement:
 */
typedef struct node_entry_t {
	ir_node *low_word;    /**< the low word */
	ir_node *high_word;   /**< the high word */
} node_entry_t;

enum lower_flags {
	MUST_BE_LOWERED = 1,  /**< graph must be lowered */
	CF_CHANGED      = 2,  /**< control flow was changed */
};

/**
 * The lower environment.
 */
struct lower_env_t {
	node_entry_t **entries;       /**< entries per node */
	ir_graph      *irg;
	struct obstack obst;          /**< an obstack holding the temporary data */
	ir_type  *l_mtp;              /**< lowered method type of the current method */
	tarval   *tv_mode_bytes;      /**< a tarval containing the number of bytes in the lowered modes */
	tarval   *tv_mode_bits;       /**< a tarval containing the number of bits in the lowered modes */
	pdeq     *waitq;              /**< a wait queue of all nodes that must be handled later */
	ir_node **lowered_phis;       /**< list of lowered phis */
	pmap     *proj_2_block;       /**< a map from ProjX to its destination blocks */
	ir_mode  *high_signed;        /**< doubleword signed type */
	ir_mode  *high_unsigned;      /**< doubleword unsigned type */
	ir_mode  *low_signed;         /**< word signed type */
	ir_mode  *low_unsigned;       /**< word unsigned type */
	ident    *first_id;           /**< .l for little and .h for big endian */
	ident    *next_id;            /**< .h for little and .l for big endian */
	const lwrdw_param_t *params;  /**< transformation parameter */
	unsigned flags;               /**< some flags */
	unsigned n_entries;           /**< number of entries */
	ir_type  *value_param_tp;     /**< the old value param type */
};

/**
 * Create a method type for a Conv emulation from imode to omode.
 */
static ir_type *get_conv_type(ir_mode *imode, ir_mode *omode, lower_env_t *env)
{
	conv_tp_entry_t key, *entry;
	ir_type *mtd;

	key.imode = imode;
	key.omode = omode;
	key.mtd   = NULL;

	entry = set_insert(conv_types, &key, sizeof(key), HASH_PTR(imode) ^ HASH_PTR(omode));
	if (! entry->mtd) {
		int n_param = 1, n_res = 1;

		if (imode == env->high_signed || imode == env->high_unsigned)
			n_param = 2;
		if (omode == env->high_signed || omode == env->high_unsigned)
			n_res = 2;

		/* create a new one */
		mtd = new_type_method(n_param, n_res);

		/* set param types and result types */
		n_param = 0;
		if (imode == env->high_signed) {
			set_method_param_type(mtd, n_param++, tp_u);
			set_method_param_type(mtd, n_param++, tp_s);
		} else if (imode == env->high_unsigned) {
			set_method_param_type(mtd, n_param++, tp_u);
			set_method_param_type(mtd, n_param++, tp_u);
		} else {
			ir_type *tp = get_type_for_mode(imode);
			set_method_param_type(mtd, n_param++, tp);
		}

		n_res = 0;
		if (omode == env->high_signed) {
			set_method_res_type(mtd, n_res++, tp_u);
			set_method_res_type(mtd, n_res++, tp_s);
		} else if (omode == env->high_unsigned) {
			set_method_res_type(mtd, n_res++, tp_u);
			set_method_res_type(mtd, n_res++, tp_u);
		} else {
			ir_type *tp = get_type_for_mode(omode);
			set_method_res_type(mtd, n_res++, tp);
		}
		entry->mtd = mtd;
	} else {
		mtd = entry->mtd;
	}
	return mtd;
}

/**
 * Add an additional control flow input to a block.
 * Patch all Phi nodes. The new Phi inputs are copied from
 * old input number nr.
 */
static void add_block_cf_input_nr(ir_node *block, int nr, ir_node *cf)
{
	int i, arity = get_irn_arity(block);
	ir_node **in, *phi;

	assert(nr < arity);

	NEW_ARR_A(ir_node *, in, arity + 1);
	for (i = 0; i < arity; ++i)
		in[i] = get_irn_n(block, i);
	in[i] = cf;

	set_irn_in(block, i + 1, in);

	for (phi = get_Block_phis(block); phi != NULL; phi = get_Phi_next(phi)) {
		for (i = 0; i < arity; ++i)
			in[i] = get_irn_n(phi, i);
		in[i] = in[nr];
		set_irn_in(phi, i + 1, in);
	}
}

/**
 * Add an additional control flow input to a block.
 * Patch all Phi nodes. The new Phi inputs are copied from
 * old input from cf tmpl.
 */
static void add_block_cf_input(ir_node *block, ir_node *tmpl, ir_node *cf)
{
	int i, arity = get_irn_arity(block);
	int nr = 0;

	for (i = 0; i < arity; ++i) {
		if (get_irn_n(block, i) == tmpl) {
			nr = i;
			break;
		}
	}
	assert(i < arity);
	add_block_cf_input_nr(block, nr, cf);
}

/**
 * Return the "operational" mode of a Firm node.
 */
static ir_mode *get_irn_op_mode(ir_node *node)
{
	switch (get_irn_opcode(node)) {
	case iro_Load:
		return get_Load_mode(node);
	case iro_Store:
		return get_irn_mode(get_Store_value(node));
	case iro_DivMod:
		return get_irn_mode(get_DivMod_left(node));
	case iro_Div:
		return get_irn_mode(get_Div_left(node));
	case iro_Mod:
		return get_irn_mode(get_Mod_left(node));
	case iro_Cmp:
		return get_irn_mode(get_Cmp_left(node));
	default:
		return get_irn_mode(node);
	}
}

/**
 * Walker, prepare the node links and determine which nodes need to be lowered
 * at all.
 */
static void prepare_links(lower_env_t *env, ir_node *node)
{
	ir_mode      *mode = get_irn_op_mode(node);
	node_entry_t *link;
	int           i;

	if (mode == env->high_signed || mode == env->high_unsigned) {
		unsigned idx = get_irn_idx(node);
		/* ok, found a node that will be lowered */
		link = OALLOCZ(&env->obst, node_entry_t);

		if (idx >= env->n_entries) {
			/* enlarge: this happens only for Rotl nodes which is RARELY */
			unsigned old   = env->n_entries;
			unsigned n_idx = idx + (idx >> 3);

			ARR_RESIZE(node_entry_t *, env->entries, n_idx);
			memset(&env->entries[old], 0, (n_idx - old) * sizeof(env->entries[0]));
			env->n_entries = n_idx;
		}
		env->entries[idx] = link;
		env->flags |= MUST_BE_LOWERED;
	} else if (is_Conv(node)) {
		/* Conv nodes have two modes */
		ir_node *pred = get_Conv_op(node);
		mode = get_irn_mode(pred);

		if (mode == env->high_signed || mode == env->high_unsigned) {
			/* must lower this node either but don't need a link */
			env->flags |= MUST_BE_LOWERED;
		}
		return;
	}

	if (is_Proj(node)) {
		/* link all Proj nodes to its predecessor:
		   Note that Tuple Proj's and its Projs are linked either. */
		ir_node *pred = get_Proj_pred(node);

		set_irn_link(node, get_irn_link(pred));
		set_irn_link(pred, node);
	} else if (is_Phi(node)) {
		/* link all Phi nodes to its block */
		ir_node *block = get_nodes_block(node);
		add_Block_phi(block, node);
	} else if (is_Block(node)) {
		/* fill the Proj -> Block map */
		for (i = get_Block_n_cfgpreds(node) - 1; i >= 0; --i) {
			ir_node *pred = get_Block_cfgpred(node, i);

			if (is_Proj(pred))
				pmap_insert(env->proj_2_block, pred, node);
		}
	}
}

static node_entry_t *get_node_entry(lower_env_t *env, ir_node *node)
{
	unsigned idx = get_irn_idx(node);
	assert(idx < env->n_entries);
	return env->entries[idx];
}

static void set_lowered(lower_env_t *env, ir_node *old,
                        ir_node *new_low, ir_node *new_high)
{
	node_entry_t *entry = get_node_entry(env, old);
	entry->low_word  = new_low;
	entry->high_word = new_high;
}

/**
 * Translate a Constant: create two.
 */
static void lower_Const(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_graph *irg      = get_irn_irg(node);
	dbg_info *dbg      = get_irn_dbg_info(node);
	ir_mode  *low_mode = env->low_unsigned;
	tarval   *tv       = get_Const_tarval(node);
	tarval   *tv_l     = tarval_convert_to(tv, low_mode);
	ir_node  *res_low  = new_rd_Const(dbg, irg, tv_l);
	tarval   *tv_shrs  = tarval_shrs(tv, env->tv_mode_bits);
	tarval   *tv_h     = tarval_convert_to(tv_shrs, mode);
	ir_node  *res_high = new_rd_Const(dbg, irg, tv_h);

	set_lowered(env, node, res_low, res_high);
}

/**
 * Translate a Load: create two.
 */
static void lower_Load(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_mode    *low_mode = env->low_unsigned;
	ir_graph   *irg = get_irn_irg(node);
	ir_node    *adr = get_Load_ptr(node);
	ir_node    *mem = get_Load_mem(node);
	ir_node    *low, *high, *proj;
	dbg_info   *dbg;
	ir_node    *block = get_nodes_block(node);
	ir_cons_flags volatility = get_Load_volatility(node) == volatility_is_volatile
	                         ? cons_volatile : 0;

	if (env->params->little_endian) {
		low  = adr;
		high = new_r_Add(block, adr, new_r_Const(irg, env->tv_mode_bytes), get_irn_mode(adr));
	} else {
		low  = new_r_Add(block, adr, new_r_Const(irg, env->tv_mode_bytes), get_irn_mode(adr));
		high = adr;
	}

	/* create two loads */
	dbg  = get_irn_dbg_info(node);
	low  = new_rd_Load(dbg, block, mem,  low,  low_mode, volatility);
	proj = new_r_Proj(low, mode_M, pn_Load_M);
	high = new_rd_Load(dbg, block, proj, high, mode, volatility);

	set_lowered(env, node, low, high);

	for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
		switch (get_Proj_proj(proj)) {
		case pn_Load_M:         /* Memory result. */
			/* put it to the second one */
			set_Proj_pred(proj, high);
			break;
		case pn_Load_X_except:  /* Execution result if exception occurred. */
			/* put it to the first one */
			set_Proj_pred(proj, low);
			break;
		case pn_Load_res: {       /* Result of load operation. */
			ir_node *res_low  = new_r_Proj(low,  low_mode, pn_Load_res);
			ir_node *res_high = new_r_Proj(high, mode,     pn_Load_res);
			set_lowered(env, proj, res_low, res_high);
			break;
		}
		default:
			assert(0 && "unexpected Proj number");
		}
		/* mark this proj: we have handled it already, otherwise we might fall
		 * into out new nodes. */
		mark_irn_visited(proj);
	}
}

/**
 * Translate a Store: create two.
 */
static void lower_Store(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_graph     *irg;
	ir_node      *block, *adr, *mem;
	ir_node      *low, *high, *proj;
	dbg_info     *dbg;
	ir_node            *value = get_Store_value(node);
	const node_entry_t *entry = get_node_entry(env, value);
	ir_cons_flags volatility = get_Store_volatility(node) == volatility_is_volatile
	                           ? cons_volatile : 0;
	(void) mode;

	assert(entry);

	if (! entry->low_word) {
		/* not ready yet, wait */
		pdeq_putr(env->waitq, node);
		return;
	}

	irg = get_irn_irg(node);
	adr = get_Store_ptr(node);
	mem = get_Store_mem(node);
	block = get_nodes_block(node);

	if (env->params->little_endian) {
		low  = adr;
		high = new_r_Add(block, adr, new_r_Const(irg, env->tv_mode_bytes), get_irn_mode(adr));
	} else {
		low  = new_r_Add(block, adr, new_r_Const(irg, env->tv_mode_bytes), get_irn_mode(adr));
		high = adr;
	}

	/* create two Stores */
	dbg = get_irn_dbg_info(node);
	low  = new_rd_Store(dbg, block, mem, low,  entry->low_word, volatility);
	proj = new_r_Proj(low, mode_M, pn_Store_M);
	high = new_rd_Store(dbg, block, proj, high, entry->high_word, volatility);

	set_lowered(env, node, low, high);

	for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
		switch (get_Proj_proj(proj)) {
		case pn_Store_M:         /* Memory result. */
			/* put it to the second one */
			set_Proj_pred(proj, high);
			break;
		case pn_Store_X_except:  /* Execution result if exception occurred. */
			/* put it to the first one */
			set_Proj_pred(proj, low);
			break;
		default:
			assert(0 && "unexpected Proj number");
		}
		/* mark this proj: we have handled it already, otherwise we might fall into
		 * out new nodes. */
		mark_irn_visited(proj);
	}
}

/**
 * Return a node containing the address of the intrinsic emulation function.
 *
 * @param method  the method type of the emulation function
 * @param op      the emulated ir_op
 * @param imode   the input mode of the emulated opcode
 * @param omode   the output mode of the emulated opcode
 * @param env     the lower environment
 */
static ir_node *get_intrinsic_address(ir_type *method, ir_op *op,
                                      ir_mode *imode, ir_mode *omode,
                                      lower_env_t *env)
{
	symconst_symbol sym;
	ir_entity *ent;
	op_mode_entry_t key, *entry;

	key.op    = op;
	key.imode = imode;
	key.omode = omode;
	key.ent   = NULL;

	entry = set_insert(intrinsic_fkt, &key, sizeof(key),
				HASH_PTR(op) ^ HASH_PTR(imode) ^ (HASH_PTR(omode) << 8));
	if (! entry->ent) {
		/* create a new one */
		ent = env->params->create_intrinsic(method, op, imode, omode, env->params->ctx);

		assert(ent && "Intrinsic creator must return an entity");
		entry->ent = ent;
	} else {
		ent = entry->ent;
	}
	sym.entity_p = ent;
	return new_r_SymConst(env->irg, mode_P_code, sym, symconst_addr_ent);
}

/**
 * Translate a Div.
 *
 * Create an intrinsic Call.
 */
static void lower_Div(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_node            *left        = get_Div_left(node);
	ir_node            *right       = get_Div_right(node);
	const node_entry_t *left_entry  = get_node_entry(env, left);
	const node_entry_t *right_entry = get_node_entry(env, right);
	ir_node            *block       = get_nodes_block(node);
	dbg_info           *dbgi        = get_irn_dbg_info(node);
	ir_type            *mtp
		= mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
	ir_mode            *opmode = get_irn_op_mode(node);
	ir_node            *addr
		= get_intrinsic_address(mtp, get_irn_op(node), opmode, opmode, env);
	ir_node  *in[4] = {
		left_entry->low_word, left_entry->high_word,
		right_entry->low_word, right_entry->high_word };
	ir_node            *call
		= new_rd_Call(dbgi, block, get_Div_mem(node), addr, 4, in, mtp);
	ir_node            *resproj = new_r_Proj(call, mode_T, pn_Call_T_result);
	ir_node            *proj;

	set_irn_pinned(call, get_irn_pinned(node));

	for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
		switch (get_Proj_proj(proj)) {
		case pn_Div_M:         /* Memory result. */
			/* reroute to the call */
			set_Proj_pred(proj, call);
			set_Proj_proj(proj, pn_Call_M);
			break;
		case pn_Div_X_except:  /* Execution result if exception occurred. */
			/* reroute to the call */
			set_Proj_pred(proj, call);
			set_Proj_proj(proj, pn_Call_X_except);
			break;
		case pn_Div_res: {
			/* Result of computation. */
			ir_node *res_low  = new_r_Proj(resproj, env->low_unsigned, 0);
			ir_node *res_high = new_r_Proj(resproj, mode,              1);
			set_lowered(env, proj, res_low, res_high);
			break;
		}
		default:
			assert(0 && "unexpected Proj number");
		}
		/* mark this proj: we have handled it already, otherwise we might fall into
		 * out new nodes. */
		mark_irn_visited(proj);
	}
}

/**
 * Translate a Mod.
 *
 * Create an intrinsic Call.
 */
static void lower_Mod(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_node            *left        = get_Mod_left(node);
	ir_node            *right       = get_Mod_right(node);
	const node_entry_t *left_entry  = get_node_entry(env, left);
	const node_entry_t *right_entry = get_node_entry(env, right);
	ir_node            *in[4]       = {
		left_entry->low_word, left_entry->high_word,
		right_entry->low_word, right_entry->high_word
	};
	dbg_info           *dbgi        = get_irn_dbg_info(node);
	ir_node            *block       = get_nodes_block(node);
	ir_type            *mtp
		= mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
	ir_mode            *opmode = get_irn_op_mode(node);
	ir_node            *addr
		= get_intrinsic_address(mtp, get_irn_op(node), opmode, opmode, env);
	ir_node            *call
		= new_rd_Call(dbgi, block, get_Mod_mem(node), addr, 4, in, mtp);
	ir_node            *resproj = new_r_Proj(call, mode_T, pn_Call_T_result);
	ir_node            *proj;
	set_irn_pinned(call, get_irn_pinned(node));

	for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
		switch (get_Proj_proj(proj)) {
		case pn_Mod_M:         /* Memory result. */
			/* reroute to the call */
			set_Proj_pred(proj, call);
			set_Proj_proj(proj, pn_Call_M);
			break;
		case pn_Mod_X_except:  /* Execution result if exception occurred. */
			/* reroute to the call */
			set_Proj_pred(proj, call);
			set_Proj_proj(proj, pn_Call_X_except);
			break;
		case pn_Mod_res: {
			/* Result of computation. */
			ir_node *res_low  = new_r_Proj(resproj, env->low_unsigned, 0);
			ir_node *res_high = new_r_Proj(resproj, mode,              1);
			set_lowered(env, proj, res_low, res_high);
			break;
		}
		default:
			assert(0 && "unexpected Proj number");
		}
		/* mark this proj: we have handled it already, otherwise we might fall
		 * into out new nodes. */
		mark_irn_visited(proj);
	}
}

static void lower_DivMod(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	(void) node;
	(void) mode;
	(void) env;
	panic("DivMod is deprecated, no doubleword lowering");
}

/**
 * Translate a binop.
 *
 * Create an intrinsic Call.
 */
static void lower_binop(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_node            *left        = get_binop_left(node);
	ir_node            *right       = get_binop_right(node);
	const node_entry_t *left_entry  = get_node_entry(env, left);
	const node_entry_t *right_entry = get_node_entry(env, right);
	ir_node            *in[4]       = {
		left_entry->low_word, left_entry->high_word,
		right_entry->low_word, right_entry->high_word
	};
	dbg_info           *dbgi        = get_irn_dbg_info(node);
	ir_node            *block       = get_nodes_block(node);
	ir_graph           *irg         = get_irn_irg(block);
	ir_type            *mtp
		= mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
	ir_node            *addr
		= get_intrinsic_address(mtp, get_irn_op(node), mode, mode, env);
	ir_node            *call
		= new_rd_Call(dbgi, block, get_irg_no_mem(irg), addr, 4, in, mtp);
	ir_node            *resproj  = new_r_Proj(call, mode_T, pn_Call_T_result);
	ir_node            *res_low  = new_r_Proj(resproj, env->low_unsigned, 0);
	ir_node            *res_high = new_r_Proj(resproj, mode,              1);
	set_irn_pinned(call, get_irn_pinned(node));
	set_lowered(env, node, res_low, res_high);
}

/**
 * Translate a Shiftop.
 *
 * Create an intrinsic Call.
 */
static void lower_Shiftop(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_node            *left       = get_binop_left(node);
	const node_entry_t *left_entry = get_node_entry(env, left);
	ir_node            *right      = get_binop_right(node);
	ir_node            *in[3]      = {
		left_entry->low_word, left_entry->high_word, right
	};
	dbg_info           *dbgi       = get_irn_dbg_info(node);
	ir_node            *block      = get_nodes_block(node);
	ir_graph           *irg        = get_irn_irg(block);
	ir_type            *mtp
		= mode_is_signed(mode) ? shiftop_tp_s : shiftop_tp_u;
	ir_node            *addr
		= get_intrinsic_address(mtp, get_irn_op(node), mode, mode, env);
	ir_node            *call
		= new_rd_Call(dbgi, block, get_irg_no_mem(irg), addr, 3, in, mtp);
	ir_node            *resproj  = new_r_Proj(call, mode_T, pn_Call_T_result);
	ir_node            *res_low  = new_r_Proj(resproj, env->low_unsigned, 0);
	ir_node            *res_high = new_r_Proj(resproj, mode,              1);

	set_irn_pinned(call, get_irn_pinned(node));
	set_lowered(env, node, res_low, res_high);

	/* The shift count is always mode_Iu, no need for lowering */
	assert(get_irn_mode(right) != env->high_signed
			&& get_irn_mode(right) != env->high_unsigned);
}

/**
 * Translate a Shr and handle special cases.
 */
static void lower_Shr(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_graph *irg   = get_irn_irg(node);
	ir_node  *right = get_Shr_right(node);

	if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
		tarval *tv = get_Const_tarval(right);

		if (tarval_is_long(tv) &&
		    get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
			ir_node *block        = get_nodes_block(node);
			ir_node *left         = get_Shr_left(node);
			ir_mode *low_unsigned = env->low_unsigned;
			long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
			const node_entry_t *left_entry = get_node_entry(env, left);
			ir_node *res_low;
			ir_node *res_high;

			left = left_entry->high_word;

			/* convert high word into low_unsigned mode if necessary */
			if (get_irn_mode(left) != low_unsigned)
				left = new_r_Conv(block, left, low_unsigned);

			if (shf_cnt > 0) {
				ir_node *c = new_r_Const_long(irg, low_unsigned, shf_cnt);
				res_low = new_r_Shr(block, left, c, low_unsigned);
			} else {
				res_low = left;
			}
			res_high = new_r_Const(irg, get_mode_null(mode));
			set_lowered(env, node, res_low, res_high);

			return;
		}
	}
	lower_Shiftop(node, mode, env);
}

/**
 * Translate a Shl and handle special cases.
 */
static void lower_Shl(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_graph *irg   = get_irn_irg(node);
	ir_node  *right = get_Shl_right(node);

	if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
		tarval *tv = get_Const_tarval(right);

		if (tarval_is_long(tv) &&
		    get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
			ir_mode *mode_l;
			ir_node *block = get_nodes_block(node);
			ir_node *left = get_Shl_left(node);
			ir_node *c;
			long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
			const node_entry_t *left_entry = get_node_entry(env, left);
			ir_node  *res_low;
			ir_node  *res_high;

			left = left_entry->low_word;
			left = new_r_Conv(block, left, mode);

			mode_l = env->low_unsigned;
			if (shf_cnt > 0) {
				c        = new_r_Const_long(irg, mode_l, shf_cnt);
				res_high = new_r_Shl(block, left, c, mode);
			} else {
				res_high = left;
			}
			res_low = new_r_Const(irg, get_mode_null(mode_l));
			set_lowered(env, node, res_low, res_high);

			return;
		}
	}
	lower_Shiftop(node, mode, env);
}

/**
 * Translate a Shrs and handle special cases.
 */
static void lower_Shrs(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_graph *irg   = get_irn_irg(node);
	ir_node  *right = get_Shrs_right(node);

	if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
		tarval *tv = get_Const_tarval(right);

		if (tarval_is_long(tv) &&
		    get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
			ir_node *block         = get_nodes_block(node);
			ir_node *left          = get_Shrs_left(node);
			ir_mode *low_unsigned  = env->low_unsigned;
			long     shf_cnt       = get_tarval_long(tv) - get_mode_size_bits(mode);
			const node_entry_t *left_entry = get_node_entry(env, left);
			ir_node *left_unsigned = left;
			ir_node *res_low;
			ir_node *res_high;
			ir_node *c;

			left = left_entry->high_word;

			/* convert high word into low_unsigned mode if necessary */
			if (get_irn_mode(left_unsigned) != low_unsigned)
				left_unsigned = new_r_Conv(block, left, low_unsigned);

			if (shf_cnt > 0) {
				c       = new_r_Const_long(irg, low_unsigned, shf_cnt);
				res_low = new_r_Shrs(block, left_unsigned, c, low_unsigned);
			} else {
				res_low = left_unsigned;
			}

			c        = new_r_Const(irg, get_mode_all_one(low_unsigned));
			res_high = new_r_Shrs(block, left, c, mode);
			set_lowered(env, node, res_low, res_high);
			return;
		}
	}
	lower_Shiftop(node, mode, env);
}

/**
 * Rebuild Rotl nodes into Or(Shl, Shr) and prepare all nodes.
 */
static void prepare_links_and_handle_rotl(ir_node *node, void *env)
{
	lower_env_t *lenv = env;

	if (is_Rotl(node)) {
		ir_mode  *mode = get_irn_op_mode(node);
		ir_node  *right;
		ir_node  *left, *shl, *shr, *or, *block, *sub, *c;
		ir_mode  *omode, *rmode;
		ir_graph *irg;
		dbg_info *dbg;
		optimization_state_t state;

		if (mode != lenv->high_signed && mode != lenv->high_unsigned) {
			prepare_links(lenv, node);
			return;
		}

		/* replace the Rotl(x,y) by an Or(Shl(x,y), Shr(x,64-y)) */
		right = get_Rotl_right(node);
		irg   = get_irn_irg(node);
		dbg   = get_irn_dbg_info(node);
		omode = get_irn_mode(node);
		left  = get_Rotl_left(node);
		block = get_nodes_block(node);
		shl   = new_rd_Shl(dbg, block, left, right, omode);
		rmode = get_irn_mode(right);
		c     = new_r_Const_long(irg, rmode, get_mode_size_bits(omode));
		sub   = new_rd_Sub(dbg, block, c, right, rmode);
		shr   = new_rd_Shr(dbg, block, left, sub, omode);

		/* switch optimization off here, or we will get the Rotl back */
		save_optimization_state(&state);
		set_opt_algebraic_simplification(0);
		or = new_rd_Or(dbg, block, shl, shr, omode);
		restore_optimization_state(&state);

		exchange(node, or);

		/* do lowering on the new nodes */
		prepare_links(lenv, shl);
		prepare_links(lenv, c);
		prepare_links(lenv, sub);
		prepare_links(lenv, shr);
		prepare_links(lenv, or);
		return;
	}

	prepare_links(lenv, node);
}

/**
 * Translate an Unop.
 *
 * Create an intrinsic Call.
 */
static void lower_Unop(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_node            *op       = get_unop_op(node);
	const node_entry_t *op_entry = get_node_entry(env, op);
	ir_node            *in[2]    = { op_entry->low_word, op_entry->high_word };
	dbg_info           *dbgi     = get_irn_dbg_info(node);
	ir_node            *block    = get_nodes_block(node);
	ir_graph           *irg      = get_irn_irg(block);
	ir_type            *mtp      = mode_is_signed(mode) ? unop_tp_s : unop_tp_u;
	ir_op              *irop     = get_irn_op(node);
	ir_node            *addr     = get_intrinsic_address(mtp, irop, mode, mode, env);
	ir_node            *nomem    = get_irg_no_mem(irg);
	ir_node            *call     = new_rd_Call(dbgi, block, nomem, addr, 2, in, mtp);
	ir_node            *resproj  = new_r_Proj(call, mode_T, pn_Call_T_result);
	ir_node            *res_low  = new_r_Proj(resproj, env->low_unsigned, 0);
	ir_node            *res_high = new_r_Proj(resproj, mode,              1);
	set_irn_pinned(call, get_irn_pinned(node));
	set_lowered(env, node, res_low, res_high);
}

/**
 * Translate a logical binop.
 *
 * Create two logical binops.
 */
static void lower_binop_logical(ir_node *node, ir_mode *mode, lower_env_t *env,
								ir_node *(*constr_rd)(dbg_info *db, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) )
{
	ir_node            *left        = get_binop_left(node);
	ir_node            *right       = get_binop_right(node);
	const node_entry_t *left_entry  = get_node_entry(env, left);
	const node_entry_t *right_entry = get_node_entry(env, right);
	dbg_info           *dbgi        = get_irn_dbg_info(node);
	ir_node            *block       = get_nodes_block(node);
	ir_node            *res_low
		= constr_rd(dbgi, block, left_entry->low_word, right_entry->low_word,
		            env->low_unsigned);
	ir_node            *res_high
		= constr_rd(dbgi, block, left_entry->high_word, right_entry->high_word,
		            mode);
	set_lowered(env, node, res_low, res_high);
}

static void lower_And(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	lower_binop_logical(node, mode, env, new_rd_And);
}

static void lower_Or(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	lower_binop_logical(node, mode, env, new_rd_Or);
}

static void lower_Eor(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	lower_binop_logical(node, mode, env, new_rd_Eor);
}

/**
 * Translate a Not.
 *
 * Create two logical Nots.
 */
static void lower_Not(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_node            *op       = get_Not_op(node);
	const node_entry_t *op_entry = get_node_entry(env, op);
	dbg_info           *dbgi     = get_irn_dbg_info(node);
	ir_node            *block    = get_nodes_block(node);
	ir_node            *res_low
		= new_rd_Not(dbgi, block, op_entry->low_word, env->low_unsigned);
	ir_node            *res_high
		= new_rd_Not(dbgi, block, op_entry->high_word, mode);
	set_lowered(env, node, res_low, res_high);
}

/**
 * Translate a Cond.
 */
static void lower_Cond(ir_node *node, ir_mode *mode, lower_env_t *env)
{
	ir_node *cmp, *left, *right, *block;
	ir_node *sel = get_Cond_selector(node);
	ir_mode *m = get_irn_mode(sel);
	ir_mode *cmp_mode;
	const node_entry_t *lentry, *rentry;
	ir_node  *proj, *projT = NULL, *projF = NULL;
	ir_node  *new_bl, *cmpH, *cmpL, *irn;
	ir_node  *projHF, *projHT;
	ir_node  *dst_blk;
	pn_Cmp   pnc;
	ir_graph *irg;
	dbg_info *dbg;

	(void) mode;

	if (m != mode_b) {
		if (m == env->high_signed || m == env->high_unsigned) {
			/* bad we can't really handle Switch with 64bit offsets */
			panic("Cond with 64bit jumptable not supported");
		}
		return;
	}

	if (!is_Proj(sel))
		return;

	cmp = get_Proj_pred(sel);
	if (!is_Cmp(cmp))
		return;

	left     = get_Cmp_left(cmp);
	cmp_mode = get_irn_mode(left);
	if (cmp_mode != env->high_signed && cmp_mode != env->high_unsigned)
		return;

	right  = get_Cmp_right(cmp);
	lentry = get_node_entry(env, left);
	rentry = get_node_entry(env, right);

	/* all right, build the code */
	for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
		long proj_nr = get_Proj_proj(proj);

		if (proj_nr == pn_Cond_true) {
			assert(projT == NULL && "more than one Proj(true)");
			projT = proj;
		} else {
			assert(proj_nr == pn_Cond_false);
			assert(projF == NULL && "more than one Proj(false)");
			projF = proj;
		}
		mark_irn_visited(proj);
	}
	assert(projT && projF);

	/* create a new high compare */
	block = get_nodes_block(node);
	irg   = get_Block_irg(block);
	dbg   = get_irn_dbg_info(cmp);
	pnc   = get_Proj_proj(sel);

	if (is_Const(right) && is_Const_null(right)) {
		if (pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) {
			/* x ==/!= 0 ==> or(low,high) ==/!= 0 */
			ir_mode *mode = env->low_unsigned;
			ir_node *low  = new_r_Conv(block, lentry->low_word, mode);
			ir_node *high = new_r_Conv(block, lentry->high_word, mode);
			ir_node *or   = new_rd_Or(dbg, block, low, high, mode);
			ir_node *cmp  = new_rd_Cmp(dbg, block, or, new_r_Const_long(irg, mode, 0));

			ir_node *proj = new_r_Proj(cmp, mode_b, pnc);
			set_Cond_selector(node, proj);
			return;
		}
	}

	cmpH = new_rd_Cmp(dbg, block, lentry->high_word, rentry->high_word);

	if (pnc == pn_Cmp_Eq) {
		/* simple case:a == b <==> a_h == b_h && a_l == b_l */
		pmap_entry *entry = pmap_find(env->proj_2_block, projF);

		assert(entry);
		dst_blk = entry->value;

		irn = new_r_Proj(cmpH, mode_b, pn_Cmp_Eq);
		dbg = get_irn_dbg_info(node);
		irn = new_rd_Cond(dbg, block, irn);