ia32_spec.pl 36.9 KB
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# Creation: 2005/10/19
# $Id$
# This is the specification for the ia32 assembler Firm-operations

# the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
$arch = "ia32";

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# this string marks the beginning of a comment in emit
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$comment_string = "/*";
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# the number of additional opcodes you want to register
$additional_opcodes = 0;

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# The node description is done as a perl hash initializer with the
# following structure:
#
# %nodes = (
#
# <op-name> => {
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#   "op_flags"  => "N|L|C|X|I|F|Y|H|c|K",
#   "irn_flags" => "R|N|I"
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#   "arity"     => "0|1|2|3 ... |variable|dynamic|any",
#   "state"     => "floats|pinned|mem_pinned|exc_pinned",
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#   "args"      => [
#                    { "type" => "type 1", "name" => "name 1" },
#                    { "type" => "type 2", "name" => "name 2" },
#                    ...
#                  ],
#   "comment"   => "any comment for constructor",
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#   "reg_req"   => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
#   "cmp_attr"  => "c source code for comparing node attributes",
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#   "emit"      => "emit code with templates",
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#   "attr"      => "attitional attribute arguments for constructor"
#   "init_attr" => "emit attribute initialization template"
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#   "rd_constructor" => "c source code which constructs an ir_node"
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# },
#
# ... # (all nodes you need to describe)
#
# ); # close the %nodes initializer

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# op_flags: flags for the operation, OPTIONAL (default is "N")
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# the op_flags correspond to the firm irop_flags:
#   N   irop_flag_none
#   L   irop_flag_labeled
#   C   irop_flag_commutative
#   X   irop_flag_cfopcode
#   I   irop_flag_ip_cfopcode
#   F   irop_flag_fragile
#   Y   irop_flag_forking
#   H   irop_flag_highlevel
#   c   irop_flag_constlike
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#   K   irop_flag_keep
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#
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# irn_flags: special node flags, OPTIONAL (default is 0)
# following irn_flags are supported:
#   R   rematerializeable
#   N   not spillable
#   I   ignore for register allocation
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#
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# state: state of the operation, OPTIONAL (default is "floats")
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#
# arity: arity of the operation, MUST NOT BE OMITTED
#
# args:  the OPTIONAL arguments of the node constructor (debug, irg and block
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#        are always the first 3 arguments and are always autmatically
#        created)
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#        If this key is missing the following arguments will be created:
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#        for i = 1 .. arity: ir_node *op_i
#        ir_mode *mode
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#
# comment: OPTIONAL comment for the node constructor
#
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# rd_constructor: for every operation there will be a
#      new_rd_<arch>_<op-name> function with the arguments from above
#      which creates the ir_node corresponding to the defined operation
#      you can either put the complete source code of this function here
#
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#      This key is OPTIONAL. If omitted, the following constructor will
#      be created:
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#      if (!op_<arch>_<op-name>) assert(0);
#      for i = 1 to arity
#         set in[i] = op_i
#      done
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#      res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
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#      return res
#
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# NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
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# register types:
#   0 - no special type
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#   1 - caller save (register must be saved by the caller of a function)
#   2 - callee save (register must be saved by the called function)
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#   4 - ignore (do not assign this register)
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# NOTE: Last entry of each class is the largest Firm-Mode a register can hold
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%reg_classes = (
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  "gp" => [
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            { "name" => "eax", "type" => 1 },
            { "name" => "edx", "type" => 1 },
            { "name" => "ebx", "type" => 2 },
            { "name" => "ecx", "type" => 1 },
            { "name" => "esi", "type" => 2 },
            { "name" => "edi", "type" => 2 },
            { "name" => "ebp", "type" => 2 },
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            { "name" => "esp", "type" => 4 },
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            { "name" => "gp_NOREG", "type" => 6 },  # we need a dummy register for NoReg and Unknown nodes
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			{ "mode" => "mode_P" }
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          ],
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  "xmm" => [
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            { "name" => "xmm0", "type" => 1 },
            { "name" => "xmm1", "type" => 1 },
            { "name" => "xmm2", "type" => 1 },
            { "name" => "xmm3", "type" => 1 },
            { "name" => "xmm4", "type" => 1 },
            { "name" => "xmm5", "type" => 1 },
            { "name" => "xmm6", "type" => 1 },
            { "name" => "xmm7", "type" => 1 },
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            { "name" => "xmm_NOREG", "type" => 6 },  # we need a dummy register for NoReg and Unknown nodes
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			{ "mode" => "mode_D" }
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          ],
  "vfp" => [
            { "name" => "vf0", "type" => 1 },
            { "name" => "vf1", "type" => 1 },
            { "name" => "vf2", "type" => 1 },
            { "name" => "vf3", "type" => 1 },
            { "name" => "vf4", "type" => 1 },
            { "name" => "vf5", "type" => 1 },
            { "name" => "vf6", "type" => 1 },
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            { "name" => "vf7", "type" => 1 },
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            { "name" => "vfp_NOREG", "type" => 6 },  # we need a dummy register for NoReg and Unknown nodes
			{ "mode" => "mode_E" }
          ],
  "st" => [
            { "name" => "st0", "type" => 1 },
            { "name" => "st1", "type" => 1 },
            { "name" => "st2", "type" => 1 },
            { "name" => "st3", "type" => 1 },
            { "name" => "st4", "type" => 1 },
            { "name" => "st5", "type" => 1 },
            { "name" => "st6", "type" => 1 },
            { "name" => "st7", "type" => 1 },
            { "name" => "st_NOREG", "type" => 6 },  # we need a dummy register for NoReg and Unknown nodes
			{ "mode" => "mode_E" }
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          ]
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); # %reg_classes

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#--------------------------------------------------#
#                        _                         #
#                       (_)                        #
#  _ __   _____      __  _ _ __    ___  _ __  ___  #
# | '_ \ / _ \ \ /\ / / | | '__|  / _ \| '_ \/ __| #
# | | | |  __/\ V  V /  | | |    | (_) | |_) \__ \ #
# |_| |_|\___| \_/\_/   |_|_|     \___/| .__/|___/ #
#                                      | |         #
#                                      |_|         #
#--------------------------------------------------#

%nodes = (

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#-----------------------------------------------------------------#
#  _       _                                         _            #
# (_)     | |                                       | |           #
#  _ _ __ | |_ ___  __ _  ___ _ __   _ __   ___   __| | ___  ___  #
# | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
# | | | | | ||  __/ (_| |  __/ |    | | | | (_) | (_| |  __/\__ \ #
# |_|_| |_|\__\___|\__, |\___|_|    |_| |_|\___/ \__,_|\___||___/ #
#                   __/ |                                         #
#                  |___/                                          #
#-----------------------------------------------------------------#
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# commutative operations

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# NOTE:
# All nodes supporting Addressmode have 5 INs:
# 1 - base    r1 == NoReg in case of no AM or no base
# 2 - index   r2 == NoReg in case of no AM or no index
# 3 - op1     r3 == always present
# 4 - op2     r4 == NoReg in case of immediate operation
# 5 - mem     NoMem in case of no AM otherwise it takes the mem from the Load
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"Add" => {
  "irn_flags" => "R",
  "comment"   => "construct Add: Add(a, b) = Add(b, a) = a + b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
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},

"Mul" => {
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  "irn_flags" => "A",
  "comment"   => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
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},

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# Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
"Mulh" => {
  "comment"   => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
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  "emit"      => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */'
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},

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"And" => {
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  "irn_flags" => "R",
  "comment"   => "construct And: And(a, b) = And(b, a) = a AND b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
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},

"Or" => {
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  "irn_flags" => "R",
  "comment"   => "construct Or: Or(a, b) = Or(b, a) = a OR b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
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},

"Eor" => {
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  "irn_flags" => "R",
  "comment"   => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
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},

"Max" => {
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  "irn_flags" => "R",
  "comment"   => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
  "emit"      =>
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'2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
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  if (mode_is_signed(get_irn_mode(n))) {
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4.  cmovl %D1, %S2 /* %S1 is less %S2 */
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  }
  else {
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4.  cmovb %D1, %S2 /* %S1 is below %S2 */
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  }
'
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},

"Min" => {
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  "irn_flags" => "R",
  "comment"   => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
  "emit"      =>
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'2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
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  if (mode_is_signed(get_irn_mode(n))) {
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2.  cmovg %D1, %S2 /* %S1 is greater %S2 */
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  }
  else {
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2.  cmova %D1, %S2, %D1 /* %S1 is above %S2 */
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  }
'
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},

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"CMov" => {
  "irn_flags" => "R",
  "comment"   => "construct Mux: Mux(sel, a, b) == sel ? a : b",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
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  "emit"      =>
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'. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
. cmovne %D1, %S3 /* sel == true -> return %S3 */
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'
},

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# not commutative operations

"Sub" => {
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  "irn_flags" => "R",
  "comment"   => "construct Sub: Sub(a, b) = a - b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
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},

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"DivMod" => {
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  "op_flags" => "F|L",
  "state"    => "exc_pinned",
  "reg_req"  => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
  "emit"     =>
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'  if (mode_is_signed(get_irn_mode(n))) {
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4.  idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
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  }
  else {
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4.  div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
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  }
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'
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},

"Shl" => {
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  "irn_flags" => "R",
  "comment"   => "construct Shl: Shl(a, b) = a << b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
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  "emit"      => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
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},

"Shr" => {
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  "irn_flags" => "R",
  "comment"   => "construct Shr: Shr(a, b) = a >> b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
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  "emit"      => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
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},

"Shrs" => {
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  "irn_flags" => "R",
  "comment"   => "construct Shrs: Shrs(a, b) = a >> b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
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  "emit"      => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
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},

"RotR" => {
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  "irn_flags" => "R",
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  "comment"     => "construct RotR: RotR(a, b) = a ROTR b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"     => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
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  "emit"        => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
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},

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"RotL" => {
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  "irn_flags" => "R",
  "comment"   => "construct RotL: RotL(a, b) = a ROTL b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
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  "emit"      => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
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},

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# unary operations
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"Minus" => {
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  "irn_flags" => "R",
  "comment"   => "construct Minus: Minus(a) = -a",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
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},

"Inc" => {
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  "irn_flags" => "R",
  "comment"   => "construct Increment: Inc(a) = a++",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
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},

"Dec" => {
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  "irn_flags" => "R",
  "comment"   => "construct Decrement: Dec(a) = a--",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
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},

"Not" => {
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  "irn_flags" => "R",
  "comment"   => "construct Not: Not(a) = !a",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
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},

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# other operations

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"CondJmp" => {
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  "op_flags"  => "L|X|Y",
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  "comment"   => "construct conditional jump: CMP A, B && JMPxx LABEL",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
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},

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"TestJmp" => {
  "op_flags"  => "L|X|Y",
  "comment"   => "construct conditional jump: TEST A, B && JMPxx LABEL",
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  "reg_req"  => { "in" => [ "gp", "gp" ] },
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
},

"CJmpAM" => {
  "op_flags"  => "L|X|Y",
  "comment"   => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
},

"CJmp" => {
  "op_flags"  => "L|X|Y",
  "comment"   => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp" ] },
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},

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"SwitchJmp" => {
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  "op_flags"  => "L|X|Y",
  "comment"   => "construct switch",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp" ], "out" => [ "none" ] },
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},

"Const" => {
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  "op_flags"  => "c",
  "irn_flags" => "R",
  "comment"   => "represents an integer constant",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "out" => [ "gp" ] },
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  "emit"      =>
'  if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
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4.   sub %D1, %D1 /* optimized mov 0 to register */
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  }
  else {
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    if (get_ia32_op_type(n) == ia32_SymConst) {
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6.    mov %D1, OFFSET FLAT:%C /* Move address of SymConst into register */
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    }
	else {
6.    mov %D1, %C /* Mov Const into register */
	}
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  }
',
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},

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"Cdq" => {
  "irn_flags" => "R",
  "comment"   => "construct CDQ: sign extend EAX -> EDX:EAX",
  "reg_req"   => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
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  "emit"      => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
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},

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# Load / Store

"Load" => {
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  "op_flags"  => "L|F",
  "irn_flags" => "R",
  "state"     => "exc_pinned",
  "comment"   => "construct Load: Load(ptr, mem) = LD ptr -> reg",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
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  "emit"      =>
'  if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
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4.   mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
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  }
  else {
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4.   mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
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  }
'
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},

"Store" => {
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  "op_flags"  => "L|F",
  "state"     => "exc_pinned",
  "comment"   => "construct Store: Store(ptr, val, mem) = ST ptr,val",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ] },
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  "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
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},

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"Store8Bit" => {
  "op_flags"  => "L|F",
  "state"     => "exc_pinned",
  "comment"   => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
  "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
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},

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"Lea" => {
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  "irn_flags" => "R",
  "comment"   => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
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  "emit"      => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
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},

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#--------------------------------------------------------#
#    __ _             _                     _            #
#   / _| |           | |                   | |           #
#  | |_| | ___   __ _| |_   _ __   ___   __| | ___  ___  #
#  |  _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
#  | | | | (_) | (_| | |_  | | | | (_) | (_| |  __/\__ \ #
#  |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#--------------------------------------------------------#

# commutative operations

"fAdd" => {
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  "irn_flags" => "R",
  "comment"   => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
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},

"fMul" => {
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  "irn_flags" => "R",
  "comment"   => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
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},

"fMax" => {
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  "irn_flags" => "R",
  "comment"   => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
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},

"fMin" => {
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  "irn_flags" => "R",
  "comment"   => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
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},

"fAnd" => {
  "irn_flags" => "R",
  "comment"   => "construct SSE And: And(a, b) = a AND b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
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},

"fOr" => {
  "irn_flags" => "R",
  "comment"   => "construct SSE Or: Or(a, b) = a OR b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
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},

"fEor" => {
  "irn_flags" => "R",
  "comment"   => "construct SSE Eor: Eor(a, b) = a XOR b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
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},

# not commutative operations

"fSub" => {
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  "irn_flags" => "R",
  "comment"   => "construct SSE Sub: Sub(a, b) = a - b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
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  "emit"      => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
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},

"fDiv" => {
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  "irn_flags" => "R",
  "comment"   => "construct SSE Div: Div(a, b) = a / b",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
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  "emit"      => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
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},

# other operations

"fCondJmp" => {
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  "op_flags"  => "L|X|Y",
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  "comment"   => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
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},
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"fConst" => {
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  "op_flags"  => "c",
  "irn_flags" => "R",
  "comment"   => "represents a SSE constant",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "out" => [ "xmm" ] },
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  "emit"      => '. mov%M %D1, %C /* Load fConst into register */',
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},
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# Load / Store
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"fLoad" => {
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  "op_flags"  => "L|F",
  "irn_flags" => "R",
  "state"     => "exc_pinned",
  "comment"   => "construct SSE Load: Load(ptr, mem) = LD ptr",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
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  "emit"      => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
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},
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"fStore" => {
  "op_flags" => "L|F",
  "state"    => "exc_pinned",
  "comment"  => "construct Store: Store(ptr, val, mem) = ST ptr,val",
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ] },
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  "emit"     => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
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},

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# CopyB

"CopyB" => {
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  "op_flags" => "F|H",
  "state"    => "pinned",
  "comment"  => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
  "reg_req"  => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
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},

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"CopyB_i" => {
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  "op_flags" => "F|H",
  "state"    => "pinned",
  "comment"  => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"  => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
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},

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# Conversions

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"Conv_I2I" => {
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  "reg_req"  => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "comment"  => "construct Conv Int -> Int"
},

"Conv_I2I8Bit" => {
  "reg_req"  => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "comment"  => "construct Conv Int -> Int"
},

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"Conv_I2FP" => {
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  "reg_req"  => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "comment"  => "construct Conv Int -> Floating Point"
},

"Conv_FP2I" => {
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  "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
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  "comment"  => "construct Conv Floating Point -> Int"
},

"Conv_FP2FP" => {
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  "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
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  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "comment"  => "construct Conv Floating Point -> Floating Point",
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},

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#--------------------------------------------------------#
#    __ _             _                     _            #
#   / _| |           | |                   | |           #
#  | |_| | ___   __ _| |_   _ __   ___   __| | ___  ___  #
#  |  _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
#  | | | | (_) | (_| | |_  | | | | (_) | (_| |  __/\__ \ #
#  |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#--------------------------------------------------------#

# virtual float nodes

"vfadd" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
},

"vfmul" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
},

"vfsub" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Sub: Sub(a, b) = a - b",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
},

"vfdiv" => {
  "comment"   => "virtual fp Div: Div(a, b) = a / b",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
},

"vfabs" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Abs: Abs(a) = |a|",
  "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
},

"vfchs" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Chs: Chs(a) = -a",
  "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
},

"vfsin" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Sin: Sin(a) = sin(a)",
  "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
},

"vfcos" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Cos: Cos(a) = cos(a)",
  "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
},

"vfsqrt" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
  "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
},

# virtual Load and Store

"vfld" => {
  "op_flags"  => "L|F",
  "irn_flags" => "R",
  "state"     => "exc_pinned",
  "comment"   => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
},

"vfst" => {
  "op_flags"  => "L|F",
  "state"     => "exc_pinned",
  "comment"   => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "none" ] },
},

737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
# Conversions

"vfild" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
},

"vfist" => {
  "comment"   => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "none" ] },
},

752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
# constants

"vfldz" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Load 0.0: Ld 0.0 -> reg",
  "reg_req"   => { "out" => [ "vfp" ] },
},

"vfld1" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Load 1.0: Ld 1.0 -> reg",
  "reg_req"   => { "out" => [ "vfp" ] },
},

"vfldpi" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Load pi: Ld pi -> reg",
  "reg_req"   => { "out" => [ "vfp" ] },
},

"vfldln2" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Load ln 2: Ld ln 2 -> reg",
  "reg_req"   => { "out" => [ "vfp" ] },
},

"vfldlg2" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Load lg 2: Ld lg 2 -> reg",
  "reg_req"   => { "out" => [ "vfp" ] },
},

"vfldl2t" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Load ld 10: Ld ld 10 -> reg",
  "reg_req"   => { "out" => [ "vfp" ] },
},

"vfldl2e" => {
  "irn_flags" => "R",
  "comment"   => "virtual fp Load ld e: Ld ld e -> reg",
  "reg_req"   => { "out" => [ "vfp" ] },
},

"vfConst" => {
  "op_flags"  => "c",
  "irn_flags" => "R",
  "comment"   => "represents a virtual floating point constant",
  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
  "reg_req"   => { "out" => [ "vfp" ] },
},

#--------------------------------------------------------#
#    __ _             _                     _            #
#   / _| |           | |                   | |           #
#  | |_| | ___   __ _| |_   _ __   ___   __| | ___  ___  #
#  |  _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
#  | | | | (_) | (_| | |_  | | | | (_) | (_| |  __/\__ \ #
#  |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#--------------------------------------------------------#

# x87 float nodes

"fadd" => {
816
  "op_flags"  => "R",
817
  "rd_constructor" => "NONE",
818
819
  "comment"   => "x87 Add: Add(a, b) = Add(b, a) = a + b",
  "reg_req"   => { },
820
821
  "emit"      => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
#  "emit"      => '. fadd %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 */'
822
823
824
},

"faddp" => {
825
  "op_flags"  => "R",
826
827
828
  "rd_constructor" => "NONE",
  "comment"   => "x87 Add: Add(a, b) = Add(b, a) = a + b",
  "reg_req"   => { },
829
830
  "emit"      => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
#  "emit"      => '. faddp %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 and pop */'
831
832
833
},

"fmul" => {
834
  "op_flags"  => "R",
835
  "rd_constructor" => "NONE",
836
837
838
  "comment"   => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
  "reg_req"   => { },
#  "emit"      => '. fmul %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */'
839
840
841
842
  "emit"      => '. fmul %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 */'
},

"fmulp" => {
843
  "op_flags"  => "R",
844
845
846
847
848
  "rd_constructor" => "NONE",
  "comment"   => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
  "reg_req"   => { },
#  "emit"      => '. fmulp %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */'
  "emit"      => '. fmulp %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 and pop */'
849
850
851
},

"fsub" => {
852
  "op_flags"  => "R",
853
  "rd_constructor" => "NONE",
854
855
  "comment"   => "x87 fp Sub: Sub(a, b) = a - b",
  "reg_req"   => { },
856
857
858
859
860
#  "emit"      => '. fsub %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */'
  "emit"      => '. fsub %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 */'
},

"fsubp" => {
861
  "op_flags"  => "R",
862
863
864
865
866
  "rd_constructor" => "NONE",
  "comment"   => "x87 fp Sub: Sub(a, b) = a - b",
  "reg_req"   => { },
#  "emit"      => '. fsubp %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */'
  "emit"      => '. fsubp %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 and pop */'
867
868
869
},

"fsubr" => {
870
  "op_flags"  => "R",
871
  "rd_constructor" => "NONE",
872
873
874
  "irn_flags" => "R",
  "comment"   => "x87 fp SubR: SubR(a, b) = b - a",
  "reg_req"   => { },
875
876
877
878
879
#  "emit"      => '. fsubr %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
  "emit"      => '. fsubr %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 */'
},

"fsubrp" => {
880
  "op_flags"  => "R",
881
882
883
884
885
886
  "rd_constructor" => "NONE",
  "irn_flags" => "R",
  "comment"   => "x87 fp SubR: SubR(a, b) = b - a",
  "reg_req"   => { },
#  "emit"      => '. fsubrp %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
  "emit"      => '. fsubrp %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 and pop */'
887
888
889
},

"fdiv" => {
890
  "op_flags"  => "R",
891
  "rd_constructor" => "NONE",
892
893
  "comment"   => "x87 fp Div: Div(a, b) = a / b",
  "reg_req"   => { },
894
895
896
897
898
#  "emit"      => '. fdiv %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
  "emit"      => '. fdiv %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 */'
},

"fdivp" => {
899
  "op_flags"  => "R",
900
901
902
903
904
  "rd_constructor" => "NONE",
  "comment"   => "x87 fp Div: Div(a, b) = a / b",
  "reg_req"   => { },
#  "emit"      => '. fdivp %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
  "emit"      => '. fdivp %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 and pop */'
905
906
907
},

"fdivr" => {
908
  "op_flags"  => "R",
909
  "rd_constructor" => "NONE",
910
911
  "comment"   => "x87 fp DivR: DivR(a, b) = b / a",
  "reg_req"   => { },
912
913
914
915
916
#  "emit"      => '. fdivr %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
  "emit"      => '. fdivr %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 */'
},

"fdivrp" => {
917
  "op_flags"  => "R",
918
919
920
921
922
  "rd_constructor" => "NONE",
  "comment"   => "x87 fp DivR: DivR(a, b) = b / a",
  "reg_req"   => { },
#  "emit"      => '. fdivrp %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
  "emit"      => '. fdivrp %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 and pop */'
923
924
925
},

"fabs" => {
926
  "op_flags"  => "R",
927
  "rd_constructor" => "NONE",
928
929
  "comment"   => "x87 fp Abs: Abs(a) = |a|",
  "reg_req"   => { },
930
  "emit"      => '. fabs %X1 /* x87 fabs(%X1) -> %X3 */'
931
932
933
},

"fchs" => {
934
  "op_flags"  => "R",
935
  "rd_constructor" => "NONE",
936
937
  "comment"   => "x87 fp Chs: Chs(a) = -a",
  "reg_req"   => { },
938
  "emit"      => '. fchs %X1 /* x87 fchs(%X1) -> %X3 */'
939
940
941
},

"fsin" => {
942
  "op_flags"  => "R",
943
  "rd_constructor" => "NONE",
944
945
  "comment"   => "x87 fp Sin: Sin(a) = sin(a)",
  "reg_req"   => { },
946
  "emit"      => '. fsin %X1 /* x87 sin(%X1) -> %X3 */'
947
948
949
},

"fcos" => {
950
  "op_flags"  => "R",
951
  "rd_constructor" => "NONE",
952
953
  "comment"   => "x87 fp Cos: Cos(a) = cos(a)",
  "reg_req"   => { },
954
  "emit"      => '. fcos %X1 /* x87 cos(%X1) -> %X3 */'
955
956
957
},

"fsqrt" => {
958
  "op_flags"  => "R",
959
  "rd_constructor" => "NONE",
960
961
  "comment"   => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
  "reg_req"   => { },
962
  "emit"      => '. fsqrt %X1 $ /* x87 sqrt(%X1) -> %X3 */'
963
964
},

965
# x87 Load and Store
966
967

"fld" => {
968
  "op_flags"  => "R",
969
  "rd_constructor" => "NONE",
970
971
972
973
  "op_flags"  => "L|F",
  "state"     => "exc_pinned",
  "comment"   => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
  "reg_req"   => { },
974
  "emit"      => '. fld %ia32_emit_x87_binop /* Load((%A1)) -> %X3 */'