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Zwinkau
libfirm
Commits
04ead3ea
Commit
04ead3ea
authored
Oct 16, 2014
by
Christoph Mallon
Browse files
arm: Give some node operands a name.
parent
bf78acfe
Changes
3
Hide whitespace changes
Inline
Side-by-side
ir/be/arm/arm_emitter.c
View file @
04ead3ea
...
...
@@ -460,7 +460,7 @@ static void emit_arm_B(const ir_node *irn)
}
}
ir_node
*
const
op1
=
get_irn_n
(
irn
,
0
);
ir_node
*
const
op1
=
get_irn_n
(
irn
,
n_arm_B_flags
);
assert
(
is_arm_Cmp
(
op1
)
||
is_arm_Tst
(
op1
));
arm_cmp_attr_t
const
*
const
cmp_attr
=
get_arm_cmp_attr_const
(
op1
);
...
...
ir/be/arm/arm_spec.pl
View file @
04ead3ea
...
...
@@ -83,16 +83,19 @@ my %unop_shifter_operand_constructors = (
reg
=>
{
custominit
=>
"
init_arm_shifter_operand(res, 0, 0, ARM_SHF_REG, 0);
",
reg_req
=>
{
in
=>
[
"
gp
"
],
out
=>
[
"
gp
"
]
},
ins
=>
[
"
Rm
"
],
},
reg_shift_reg
=>
{
attr
=>
"
arm_shift_modifier_t shift_modifier
",
custominit
=>
"
init_arm_shifter_operand(res, 0, 0, shift_modifier, 0);
",
reg_req
=>
{
in
=>
[
"
gp
",
"
gp
"
],
out
=>
[
"
gp
"
]
},
ins
=>
[
"
Rm
",
"
Rs
"
],
},
reg_shift_imm
=>
{
attr
=>
"
arm_shift_modifier_t shift_modifier, unsigned shift_immediate
",
custominit
=>
"
init_arm_shifter_operand(res, 0, 0, shift_modifier, shift_immediate);
",
reg_req
=>
{
in
=>
[
"
gp
"
],
out
=>
[
"
gp
"
]
},
ins
=>
[
"
Rm
"
],
},
);
...
...
@@ -392,6 +395,7 @@ Mov => {
mode
=>
$mode_gp
,
attr_type
=>
"
arm_shifter_operand_t
",
constructors
=>
\
%unop_shifter_operand_constructors
,
ins
=>
[
"
Rm
",
"
Rs
"
],
},
Mvn
=>
{
...
...
@@ -521,6 +525,7 @@ B => {
state
=>
"
pinned
",
mode
=>
"
mode_T
",
reg_req
=>
{
in
=>
[
"
flags
"
],
out
=>
[
"
none
",
"
none
"
]
},
ins
=>
[
"
flags
"
],
attr
=>
"
ir_relation relation
",
attr_type
=>
"
arm_CondJmp_attr_t
",
init_attr
=>
"
\t
set_arm_CondJmp_relation(res, relation);
",
...
...
ir/be/arm/arm_transform.c
View file @
04ead3ea
...
...
@@ -454,7 +454,7 @@ static ir_node *gen_int_binop_ops(ir_node *node, ir_node *op1, ir_node *op2,
case
ARM_SHF_LSR_IMM
:
case
ARM_SHF_ROR_IMM
:
if
(
factory
->
new_binop_reg_shift_imm
)
{
ir_node
*
mov_op
=
get_irn_n
(
new_op2
,
0
);
ir_node
*
mov_op
=
get_irn_n
(
new_op2
,
n_arm_Mov_Rm
);
return
factory
->
new_binop_reg_shift_imm
(
dbgi
,
block
,
new_op1
,
mov_op
,
attr
->
shift_modifier
,
attr
->
shift_immediate
);
}
...
...
@@ -465,8 +465,8 @@ static ir_node *gen_int_binop_ops(ir_node *node, ir_node *op1, ir_node *op2,
case
ARM_SHF_LSR_REG
:
case
ARM_SHF_ROR_REG
:
if
(
factory
->
new_binop_reg_shift_reg
)
{
ir_node
*
mov_op
=
get_irn_n
(
new_op2
,
0
);
ir_node
*
mov_sft
=
get_irn_n
(
new_op2
,
1
);
ir_node
*
mov_op
=
get_irn_n
(
new_op2
,
n_arm_Mov_Rm
);
ir_node
*
mov_sft
=
get_irn_n
(
new_op2
,
n_arm_Mov_Rs
);
return
factory
->
new_binop_reg_shift_reg
(
dbgi
,
block
,
new_op1
,
mov_op
,
mov_sft
,
attr
->
shift_modifier
);
}
...
...
@@ -489,7 +489,7 @@ static ir_node *gen_int_binop_ops(ir_node *node, ir_node *op1, ir_node *op2,
case
ARM_SHF_LSR_IMM
:
case
ARM_SHF_ROR_IMM
:
if
(
factory
[
idx
].
new_binop_reg_shift_imm
)
{
ir_node
*
mov_op
=
get_irn_n
(
new_op1
,
0
);
ir_node
*
mov_op
=
get_irn_n
(
new_op1
,
n_arm_Mov_Rm
);
return
factory
[
idx
].
new_binop_reg_shift_imm
(
dbgi
,
block
,
new_op2
,
mov_op
,
attr
->
shift_modifier
,
attr
->
shift_immediate
);
}
...
...
@@ -500,8 +500,8 @@ static ir_node *gen_int_binop_ops(ir_node *node, ir_node *op1, ir_node *op2,
case
ARM_SHF_LSR_REG
:
case
ARM_SHF_ROR_REG
:
if
(
factory
[
idx
].
new_binop_reg_shift_reg
)
{
ir_node
*
mov_op
=
get_irn_n
(
new_op1
,
0
);
ir_node
*
mov_sft
=
get_irn_n
(
new_op1
,
1
);
ir_node
*
mov_op
=
get_irn_n
(
new_op1
,
n_arm_Mov_Rm
);
ir_node
*
mov_sft
=
get_irn_n
(
new_op1
,
n_arm_Mov_Rs
);
return
factory
[
idx
].
new_binop_reg_shift_reg
(
dbgi
,
block
,
new_op2
,
mov_op
,
mov_sft
,
attr
->
shift_modifier
);
}
...
...
@@ -1082,7 +1082,7 @@ static ir_node *gen_Not(ir_node *node)
case
ARM_SHF_LSL_IMM
:
case
ARM_SHF_LSR_IMM
:
case
ARM_SHF_ROR_IMM
:
{
ir_node
*
mov_op
=
get_irn_n
(
new_op
,
0
);
ir_node
*
mov_op
=
get_irn_n
(
new_op
,
n_arm_Mov_Rm
);
return
new_bd_arm_Mvn_reg_shift_imm
(
dbgi
,
block
,
mov_op
,
attr
->
shift_modifier
,
attr
->
shift_immediate
);
}
...
...
@@ -1091,8 +1091,8 @@ static ir_node *gen_Not(ir_node *node)
case
ARM_SHF_LSL_REG
:
case
ARM_SHF_LSR_REG
:
case
ARM_SHF_ROR_REG
:
{
ir_node
*
mov_op
=
get_irn_n
(
new_op
,
0
);
ir_node
*
mov_sft
=
get_irn_n
(
new_op
,
1
);
ir_node
*
mov_op
=
get_irn_n
(
new_op
,
n_arm_Mov_Rm
);
ir_node
*
mov_sft
=
get_irn_n
(
new_op
,
n_arm_Mov_Rs
);
return
new_bd_arm_Mvn_reg_shift_reg
(
dbgi
,
block
,
mov_op
,
mov_sft
,
attr
->
shift_modifier
);
}
...
...
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