Commit 0de7edf5 authored by Matthias Braun's avatar Matthias Braun
Browse files

remove unused complicated arm variant enums, add a new simple one

parent 41672d1a
......@@ -873,16 +873,20 @@ void arm_emit_function(ir_graph *irg)
be_gas_emit_function_epilog(entity);
}
void arm_emit_file_prologue(void)
static const char *get_variant_string(arm_variant_t variant)
{
unsigned version = arm_cg_config.version;
if (version == 5) {
be_emit_cstring("\t.arch armv5t\n");
} else if (version == 6) {
be_emit_cstring("\t.arch armv6\n");
} else {
panic("no arch string for version %u known", version);
switch (variant) {
case ARM_VARIANT_4: return "armv4";
case ARM_VARIANT_5T: return "armv5t";
case ARM_VARIANT_6: return "armv6";
case ARM_VARIANT_7: return "armv7";
}
panic("invalid arm variant");
}
void arm_emit_file_prologue(void)
{
be_emit_irprintf("\t.arch %s\n", get_variant_string(arm_cg_config.variant));
be_emit_write_line();
be_emit_cstring("\t.fpu softvfp\n");
be_emit_write_line();
......
......@@ -676,7 +676,7 @@ static ir_node *gen_Mul(ir_node *node)
}
}
assert(mode_is_data(mode));
if (arm_cg_config.version < 6) {
if (arm_cg_config.variant < ARM_VARIANT_6) {
return new_bd_arm_Mulv5(dbg, block, new_op1, new_op2);
} else {
return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
......
......@@ -261,7 +261,7 @@ static int arm_fpu = ARM_FPU_ARCH_SOFTFLOAT;
static void arm_setup_cg_config(void)
{
memset(&arm_cg_config, 0, sizeof(arm_cg_config));
arm_cg_config.version = 6;
arm_cg_config.variant = ARM_VARIANT_6;
if (arm_fpu == ARM_FPU_SOFTFLOAT) {
arm_cg_config.use_softfloat = true;
}
......
......@@ -17,59 +17,6 @@
typedef struct arm_isa_t arm_isa_t;
/** The following bitmasks control CPU extensions: */
enum arm_cpu_extensions {
ARM_EXT_V1 = 0x00000001, /**< All processors (core set). */
ARM_EXT_V2 = 0x00000002, /**< Multiply instructions. */
ARM_EXT_V2S = 0x00000004, /**< SWP instructions. */
ARM_EXT_V3 = 0x00000008, /**< MSR MRS. */
ARM_EXT_V3M = 0x00000010, /**< Allow long multiplies. */
ARM_EXT_V4 = 0x00000020, /**< Allow half word loads. */
ARM_EXT_V4T = 0x00000040, /**< Thumb v1. */
ARM_EXT_V5 = 0x00000080, /**< Allow CLZ, etc. */
ARM_EXT_V5T = 0x00000100, /**< Thumb v2. */
ARM_EXT_V5ExP = 0x00000200, /**< DSP core set. */
ARM_EXT_V5E = 0x00000400, /**< DSP Double transfers. */
ARM_EXT_V5J = 0x00000800, /**< Jazelle extension. */
/* Co-processor space extensions. */
ARM_CEXT_XSCALE = 0x00800000, /**< Allow MIA etc. */
ARM_CEXT_MAVERICK = 0x00400000, /**< Use Cirrus/DSP coprocessor. */
ARM_CEXT_IWMMXT = 0x00200000, /**< Intel Wireless MMX technology coprocessor. */
};
/**
* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
* defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
* ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
* three more to cover cores prior to ARM6. Finally, there are cores which
* implement further extensions in the co-processor space.
*/
enum arm_architectures {
ARM_ARCH_V1 = ARM_EXT_V1,
ARM_ARCH_V2 = ARM_ARCH_V1 | ARM_EXT_V2,
ARM_ARCH_V2S = ARM_ARCH_V2 | ARM_EXT_V2S,
ARM_ARCH_V3 = ARM_ARCH_V2S | ARM_EXT_V3,
ARM_ARCH_V3M = ARM_ARCH_V3 | ARM_EXT_V3M,
ARM_ARCH_V4xM = ARM_ARCH_V3 | ARM_EXT_V4,
ARM_ARCH_V4 = ARM_ARCH_V3M | ARM_EXT_V4,
ARM_ARCH_V4TxM = ARM_ARCH_V4xM | ARM_EXT_V4T,
ARM_ARCH_V4T = ARM_ARCH_V4 | ARM_EXT_V4T,
ARM_ARCH_V5xM = ARM_ARCH_V4xM| ARM_EXT_V5,
ARM_ARCH_V5 = ARM_ARCH_V4 | ARM_EXT_V5,
ARM_ARCH_V5TxM = ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T,
ARM_ARCH_V5T = ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T,
ARM_ARCH_V5TExP = ARM_ARCH_V5T | ARM_EXT_V5ExP,
ARM_ARCH_V5TE = ARM_ARCH_V5TExP | ARM_EXT_V5E,
ARM_ARCH_V5TEJ = ARM_ARCH_V5TE | ARM_EXT_V5J,
/* Processors with specific extensions in the co-processor space. */
ARM_ARCH_XSCALE = ARM_ARCH_V5TE | ARM_CEXT_XSCALE,
ARM_ARCH_IWMMXT = ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT,
ARM_ARCH_MASK = 0x00ffffff,
};
/** Floating point instruction set. */
enum arm_fp_architectures {
ARM_FPU_FPA_EXT_V1 = 0x40000000, /**< Base FPA instruction set. */
......@@ -95,31 +42,26 @@ enum arm_fp_architectures {
ARM_FPU_MASK = 0x7f000000,
};
/** Types of processor to generate code for. */
enum arm_processor_types {
ARM_1 = ARM_ARCH_V1,
ARM_2 = ARM_ARCH_V2,
ARM_2a = ARM_ARCH_V2,
ARM_3 = ARM_ARCH_V2S,
ARM_3G = ARM_ARCH_V2S,
ARM_250 = ARM_ARCH_V2S,
ARM_6 = ARM_ARCH_V3,
ARM_7 = ARM_ARCH_V3,
ARM_8 = ARM_ARCH_V4,
ARM_9 = ARM_ARCH_V4T,
ARM_STRONG = ARM_ARCH_V4,
};
/**
* ARM architecture variants (not complete yet, add variants as necessary)
*/
typedef enum {
ARM_VARIANT_4,
ARM_VARIANT_5T,
ARM_VARIANT_6,
ARM_VARIANT_7,
} arm_variant_t;
struct arm_isa_t {
arch_env_t base; /**< must be derived from arch_env_t */
};
typedef struct arm_codegen_config_t {
unsigned version; /**< arm architecture version (5,6,7) */
bool use_softfloat;
bool use_fpa;
bool use_vfp;
bool big_endian;
arm_variant_t variant;
bool use_softfloat;
bool use_fpa;
bool use_vfp;
bool big_endian;
} arm_codegen_config_t;
extern arm_codegen_config_t arm_cg_config;
......
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