fixed stack layout modelling

fixed emit

ir/be/ia32/bearch_ia32.c

@@ -356,7 +356,7 @@ static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
 	ir_node          **returns, **in, **new_in;
 	ir_node           *stack_reserve, *sched_point;
 	ir_node           *stack_free, *new_ret, *return_block;
-	int                stack_size = 0, i, n_res;
+	int                stack_size = 0, i, n_arg;
 	arch_register_t   *stack_reg;
 	tarval            *stack_size_tv;
 	dbg_info          *frame_dbg;
@@ -372,18 +372,28 @@ static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
 	/* If frame is used, then we need to reserve some stackspace. */
 	if (get_irn_n_edges(frame) > 0) {
 		/* The initial stack reservation. */
+		stack_size    = get_type_size_bytes(get_irg_frame_type(irg));
 		frame_dbg     = get_irn_dbg_info(frame);
-		stack_reserve = new_rd_ia32_Sub_i(frame_dbg, irg, get_nodes_block(frame), frame, mode_Is);
+		stack_reserve = new_rd_ia32_Sub_i(frame_dbg, irg, get_nodes_block(frame), new_NoMem(), mode_Is);
 		stack_size_tv = new_tarval_from_long(stack_size, mode_Is);
-		set_ia32_am_const(stack_reserve, stack_size_tv);
+		set_ia32_Immop_tarval(stack_reserve, stack_size_tv);
+
+		assert(stack_size && "bOrken stack layout");
+
+		/* reroute all edges from frame pointer to corrected frame pointer */
 		edges_reroute(frame, stack_reserve, irg);
+		set_irn_n(stack_reserve, 0, frame);
+
+		/* schedule frame pointer */
+		if (! sched_is_scheduled(frame)) {
+			sched_add_after(get_irg_start(irg), frame);
+		}
 
 		/* set register */
 		arch_set_irn_register(cg->arch_env, frame, stack_reg);
 		arch_set_irn_register(cg->arch_env, stack_reserve, stack_reg);
 
 		/* insert into schedule */
-		sched_add_after(get_irg_start(irg), frame);
 		sched_add_after(frame, stack_reserve);
 
 		/* Free stack for each Return node */
@@ -395,15 +405,15 @@ static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
 
 			/* free the stack */
 			stack_free = new_rd_ia32_Add_i(frame_dbg, irg, return_block, stack_reserve, mode_Is);
-			set_ia32_am_const(stack_free, stack_size_tv);
+			set_ia32_Immop_tarval(stack_free, stack_size_tv);
 			arch_set_irn_register(cg->arch_env, stack_free, stack_reg);
 
 			DBG((mod, LEVEL_1, "examining %+F, %+F created, block %+F", returns[i], stack_free, return_block));
 
 			/* get the old Return arguments */
-			n_res  = get_Return_n_ress(returns[i]);
+			n_arg  = get_Return_n_ress(returns[i]);
 			in     = get_Return_res_arr(returns[i]);
-			new_in = malloc((n_res + 1) * sizeof(new_in[0]));
+			new_in = xmalloc((n_arg + 2) * sizeof(new_in[0]));
 
 			if (!new_in) {
 				printf("\nMUAAAAHAHAHAHAHAHAHAH\n");
@@ -411,14 +421,14 @@ static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
 			}
 
 			/* copy the old to the new in's */
-			memcpy(new_in, in, n_res * sizeof(in[0]));
-			in[n_res] = stack_free;
+			memcpy(new_in, in, n_arg * sizeof(in[0]));
+			new_in[n_arg++] = stack_free;
+			new_in[n_arg++] = get_Return_mem(returns[i]);
 
 			/* create the new return node */
-//			edges_deactivate(irg);
-			new_ret     = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_res + 1, new_in);
-//			edges_activate(irg);
+			new_ret     = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
 			sched_point = sched_prev(returns[i]);
+			sched_remove(returns[i]);
 
 			/* exchange the old return with the new one */
 			exchange(returns[i], new_ret);
@@ -426,7 +436,6 @@ static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
 			DB((mod, LEVEL_1, " ... replaced with %+F\n", new_ret));
 
 			/* remove the old one from schedule and add the new nodes properly */
-			sched_remove(returns[i]);
 			sched_add_after(sched_point, new_ret);
 			sched_add_before(new_ret, stack_free);
 		}

ir/be/ia32/ia32_emitter.c

@@ -642,9 +642,10 @@ void emit_ia32_Call(ir_node *irn, emit_env_t *emit_env) {
 		ir_node **args = get_Sync_preds_arr(sync);
 
 		for (i = 0; i < get_Sync_n_preds(sync); i++) {
-			lc_efprintf(env, F, "\tpush %1D\t\t\t\t/* push %+F on stack */\n", args[i], args[i]);
+			ir_node *n = get_irn_n(args[i], 1);
+			lc_efprintf(env, F, "\tpush %1D\t\t\t\t/* push %+F(%+F) on stack */\n", n, args[i], n);
 
-			if (mode_is_int(get_irn_mode(args[i]))) {
+			if (mode_is_int(get_irn_mode(n))) {
 				args_size += 4;
 			}
 			else {
@@ -875,6 +876,9 @@ void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
 	emit_env.arch_env = cg->arch_env;
 	emit_env.cg       = cg;
 
+	/* set the global arch_env (needed by print hooks) */
+	arch_env = cg->arch_env;
+
 	ia32_emit_start(F, irg);
 	irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
 	irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);

ir/be/ia32/ia32_spec.pl

@@ -500,7 +500,7 @@ $arch = "ia32";
   "remat"    => 1,
   "comment"  => "construct Load: Load(ptr, mem) = LD ptr -> reg",
   "reg_req"  => { "in" => [ "general_purpose", "none" ], "out" => [ "general_purpose" ] },
-  "emit"     => '. movl (%S1), %D1\t\t\t/* Load((%S1)) -> %D1, (%A1) */'
+  "emit"     => '. movl %O(%S1), %D1\t\t\t/* Load((%S1)) -> %D1, (%A1) */'
 },
 
 "Store" => {
@@ -510,7 +510,7 @@ $arch = "ia32";
   "remat"    => 1,
   "comment"  => "construct Store: Store(ptr, val, mem) = ST ptr,val",
   "reg_req"  => { "in" => [ "general_purpose", "general_purpose", "none" ] },
-  "emit"     => '. movl %S2, (%S1)\t\t\t/* Store(%S2) -> (%S1), (%A1, %A2) */'
+  "emit"     => '. movl %S2, %O(%S1)\t\t\t/* Store(%S2) -> (%S1), (%A1, %A2) */'
 },
 
 "Lea" => {
@@ -682,7 +682,7 @@ $arch = "ia32";
   "remat"    => 1,
   "comment"  => "construct SSE Load: Load(ptr, mem) = LD ptr",
   "reg_req"  => { "in" => [ "general_purpose", "none" ], "out" => [ "floating_point" ] },
-  "emit"     => '. movl (%S1), %D1\t\t\t/* Load((%S1)) -> %D1 */'
+  "emit"     => '. movl O(%S1), %D1\t\t\t/* Load((%S1)) -> %D1 */'
 },
 
 "fStore" => {
@@ -692,7 +692,7 @@ $arch = "ia32";
   "remat"    => 1,
   "comment"  => "construct Store: Store(ptr, val, mem) = ST ptr,val",
   "reg_req"  => { "in" => [ "general_purpose", "floating_point", "none" ] },
-  "emit"     => '. movl %S2, (%S1)\t\t\t/* Store(%S2) -> (%S1), (%A1, %A2) */'
+  "emit"     => '. movl %S2, O(%S1)\t\t\t/* Store(%S2) -> (%S1), (%A1, %A2) */'
 },
 
 "fStackParam" => {