amd64: Replace AMD64_OP_UNOP_REG by AMD64_OP_REG.

ir/be/amd64/amd64_emitter.c

@@ -361,11 +361,9 @@ static void amd64_emit_am(const ir_node *const node, bool indirect_star)
 		amd64_emit_addr(node, &attr->addr);
 		return;
 	}
-	case AMD64_OP_UNOP_REG:
+	case AMD64_OP_REG: {
 		if (indirect_star)
 			be_emit_char('*');
-		/* FALLTHROUGH */
-	case AMD64_OP_REG: {
 		const arch_register_t *reg = arch_get_irn_register_in(node, 0);
 		emit_register_mode(reg, attr->insn_mode);
 		return;

ir/be/amd64/amd64_new_nodes.c

@@ -45,7 +45,6 @@ static const char *get_op_mode_string(amd64_op_mode_t mode)
 	case AMD64_OP_SHIFT_IMM:  return "shift_imm";
 	case AMD64_OP_SHIFT_REG:  return "shift_reg";
 	case AMD64_OP_UNOP_IMM32: return "unop_imm32";
-	case AMD64_OP_UNOP_REG:   return "unop_reg";
 	}
 	panic("invalid op_mode");
 }

ir/be/amd64/amd64_new_nodes.h

@@ -41,8 +41,7 @@ static inline bool amd64_has_addr_attr(const ir_node *node)
 	return (amd64_has_binop_attr(node)
 		|| attr->op_mode == AMD64_OP_ADDR
 		|| attr->op_mode == AMD64_OP_REG
-	    || attr->op_mode == AMD64_OP_UNOP_IMM32
-	    || attr->op_mode == AMD64_OP_UNOP_REG)
+	    || attr->op_mode == AMD64_OP_UNOP_IMM32)
 	    && !is_amd64_xor_0(node)
 	    && !is_amd64_xorpd_0(node);
 }

ir/be/amd64/amd64_nodes_attr.h

@@ -51,7 +51,6 @@ typedef enum {
 	AMD64_OP_IMM64,
 	AMD64_OP_ADDR_REG,
 	AMD64_OP_ADDR_IMM,
-	AMD64_OP_UNOP_REG,
 	AMD64_OP_UNOP_IMM32,
 	AMD64_OP_SHIFT_REG,
 	AMD64_OP_SHIFT_IMM,

ir/be/amd64/amd64_spec.pl

@@ -140,7 +140,7 @@ my $unop = {
 	outs      => [ "res", "flags" ],
 	attr_type => "amd64_addr_attr_t",
 	attr      => "amd64_insn_mode_t insn_mode",
-	fixed     => "amd64_op_mode_t op_mode = AMD64_OP_UNOP_REG;\n"
+	fixed     => "amd64_op_mode_t op_mode = AMD64_OP_REG;\n"
 	            ."amd64_addr_t addr = { { NULL, 0, X86_IMM_VALUE }, NO_INPUT, NO_INPUT, NO_INPUT, 0, AMD64_SEGMENT_DEFAULT };",
 };
 

ir/be/amd64/amd64_transform.c

@@ -1336,8 +1336,8 @@ static ir_node *gen_IJmp(ir_node *node)
 
 			op_mode = AMD64_OP_ADDR;
 		} else {
-			op_mode          = AMD64_OP_UNOP_REG;
-			assert(arity == 0); // UNOP_REG always outputs the first input
+			op_mode          = AMD64_OP_REG;
+			assert(arity == 0); // AMD64_OP_REG always outputs the first input
 			in[arity++]      = be_transform_node(op);
 			addr.base_input  = NO_INPUT;
 			addr.index_input = NO_INPUT;
@@ -1595,13 +1595,13 @@ static ir_node *gen_Call(ir_node *node)
 			op_mode = AMD64_OP_ADDR;
 		} else {
 			int input = in_arity++;
-			assert(input == 0); /* UNOP_REG is currently hardcoded to always
+			assert(input == 0); /* AMD64_OP_REG is currently hardcoded to always
 			                     * output the register of the first input. */
 			in[input]          = be_transform_node(callee);
 			in_req[input]      = &amd64_class_reg_req_gp;
 			addr.base_input    = NO_INPUT;
 			addr.index_input   = NO_INPUT;
-			op_mode            = AMD64_OP_UNOP_REG;
+			op_mode            = AMD64_OP_REG;
 		}
 	}