Commit 172985da authored by Matthias Braun's avatar Matthias Braun
Browse files

amd64: Rename insn_mode to insn_size

parent 4306bba8
......@@ -36,64 +36,61 @@ static ir_node *get_cfop_target_block(const ir_node *irn)
return (ir_node*)get_irn_link(irn);
}
static char get_gp_mode_suffix(amd64_insn_mode_t const insn_mode)
static char get_gp_size_suffix(amd64_insn_size_t const size)
{
switch (insn_mode) {
case INSN_MODE_8: return 'b';
case INSN_MODE_16: return 'w';
case INSN_MODE_32: return 'l';
case INSN_MODE_64: return 'q';
case INSN_MODE_80:
case INSN_MODE_128:
case INSN_MODE_INVALID:
switch (size) {
case INSN_SIZE_8: return 'b';
case INSN_SIZE_16: return 'w';
case INSN_SIZE_32: return 'l';
case INSN_SIZE_64: return 'q';
case INSN_SIZE_80:
case INSN_SIZE_128:
break;
}
panic("invalid insn mode");
}
static void amd64_emit_insn_mode_suffix(amd64_insn_mode_t const insn_mode)
static void amd64_emit_insn_size_suffix(amd64_insn_size_t const size)
{
be_emit_char(get_gp_mode_suffix(insn_mode));
be_emit_char(get_gp_size_suffix(size));
}
static char get_xmm_mode_suffix(amd64_insn_mode_t const insn_mode)
static char get_xmm_size_suffix(amd64_insn_size_t const size)
{
switch (insn_mode) {
case INSN_MODE_32: return 's';
case INSN_MODE_64: return 'd';
case INSN_MODE_128: return 'q';
case INSN_MODE_8:
case INSN_MODE_16:
case INSN_MODE_80:
case INSN_MODE_INVALID:
switch (size) {
case INSN_SIZE_32: return 's';
case INSN_SIZE_64: return 'd';
case INSN_SIZE_128: return 'q';
case INSN_SIZE_8:
case INSN_SIZE_16:
case INSN_SIZE_80:
break;
}
panic("invalid insn mode");
}
static void amd64_emit_xmm_mode_suffix(amd64_insn_mode_t const insn_mode)
static void amd64_emit_xmm_size_suffix(amd64_insn_size_t const size)
{
be_emit_char(get_xmm_mode_suffix(insn_mode));
be_emit_char(get_xmm_size_suffix(size));
}
static char get_x87_mode_suffix(amd64_insn_mode_t const insn_mode)
static char get_x87_size_suffix(amd64_insn_size_t const size)
{
switch (insn_mode) {
case INSN_MODE_32: return 's';
case INSN_MODE_64: return 'l';
case INSN_MODE_80: return 't';
case INSN_MODE_8:
case INSN_MODE_16:
case INSN_MODE_128:
case INSN_MODE_INVALID:
switch (size) {
case INSN_SIZE_32: return 's';
case INSN_SIZE_64: return 'l';
case INSN_SIZE_80: return 't';
case INSN_SIZE_8:
case INSN_SIZE_16:
case INSN_SIZE_128:
break;
}
panic("Invalid insn mode");
}
static void amd64_emit_x87_mode_suffix(amd64_insn_mode_t const insn_mode)
static void amd64_emit_x87_size_suffix(amd64_insn_size_t const size)
{
be_emit_char(get_x87_mode_suffix(insn_mode));
be_emit_char(get_x87_size_suffix(size));
}
static const char *get_register_name_8bit(const arch_register_t *reg)
......@@ -183,35 +180,34 @@ static void emit_register(const arch_register_t *reg)
}
static const char *get_register_name_mode(const arch_register_t *reg,
const amd64_insn_mode_t mode)
const amd64_insn_size_t size)
{
switch (mode) {
case INSN_MODE_8: return get_register_name_8bit(reg);
case INSN_MODE_16: return get_register_name_16bit(reg);
case INSN_MODE_32: return get_register_name_32bit(reg);
case INSN_MODE_64:
case INSN_MODE_80:
case INSN_MODE_128: return reg->name;
case INSN_MODE_INVALID:
switch (size) {
case INSN_SIZE_8: return get_register_name_8bit(reg);
case INSN_SIZE_16: return get_register_name_16bit(reg);
case INSN_SIZE_32: return get_register_name_32bit(reg);
case INSN_SIZE_64:
case INSN_SIZE_80:
case INSN_SIZE_128: return reg->name;
break;
}
panic("invalid mode");
}
static void emit_register_insn_mode(const arch_register_t *reg,
const amd64_insn_mode_t mode)
static void emit_register_sized(const arch_register_t *reg,
const amd64_insn_size_t size)
{
be_emit_char('%');
be_emit_string(get_register_name_mode(reg, mode));
be_emit_string(get_register_name_mode(reg, size));
}
static void emit_register_mode(const arch_register_t *reg,
amd64_insn_mode_t insn_mode)
amd64_insn_size_t size)
{
if (reg->cls == &amd64_reg_classes[CLASS_amd64_xmm]) {
emit_register(reg);
} else {
emit_register_insn_mode(reg, insn_mode);
emit_register_sized(reg, size);
}
}
......@@ -341,7 +337,7 @@ static void amd64_emit_am(const ir_node *const node, bool indirect_star)
}
case AMD64_OP_REG_REG: {
const arch_register_t *reg1 = arch_get_irn_register_in(node, 1);
emit_register_mode(reg1, attr->insn_mode);
emit_register_mode(reg1, attr->size);
be_emit_cstring(", ");
goto emit_reg_in0;
}
......@@ -352,7 +348,7 @@ static void amd64_emit_am(const ir_node *const node, bool indirect_star)
be_emit_cstring(", ");
const arch_register_t *reg
= arch_get_irn_register_in(node, binop_attr->u.reg_input);
emit_register_mode(reg, binop_attr->base.insn_mode);
emit_register_mode(reg, binop_attr->base.size);
return;
}
case AMD64_OP_ADDR_IMM: {
......@@ -370,7 +366,7 @@ static void amd64_emit_am(const ir_node *const node, bool indirect_star)
case AMD64_OP_ADDR_REG: {
amd64_binop_addr_attr_t const *const binop_attr = (amd64_binop_addr_attr_t const*)attr;
arch_register_t const *const reg = arch_get_irn_register_in(node, binop_attr->u.reg_input);
emit_register_mode(reg, binop_attr->base.insn_mode);
emit_register_mode(reg, binop_attr->base.size);
be_emit_cstring(", ");
emit_addr:
amd64_emit_addr(node, &attr->addr);
......@@ -381,7 +377,7 @@ emit_addr:
be_emit_char('*');
emit_reg_in0:;
const arch_register_t *reg = arch_get_irn_register_in(node, 0);
emit_register_mode(reg, attr->insn_mode);
emit_register_mode(reg, attr->size);
return;
}
case AMD64_OP_IMM32:
......@@ -408,15 +404,15 @@ static void emit_shiftop(const ir_node *const node)
case AMD64_OP_SHIFT_IMM: {
be_emit_irprintf("$0x%X, ", attr->immediate);
const arch_register_t *reg = arch_get_irn_register_in(node, 0);
emit_register_mode(reg, attr->insn_mode);
emit_register_mode(reg, attr->size);
return;
}
case AMD64_OP_SHIFT_REG: {
const arch_register_t *reg0 = arch_get_irn_register_in(node, 0);
const arch_register_t *reg1 = arch_get_irn_register_in(node, 1);
emit_register_mode(reg1, INSN_MODE_8);
emit_register_mode(reg1, INSN_SIZE_8);
be_emit_cstring(", ");
emit_register_mode(reg0, attr->insn_mode);
emit_register_mode(reg0, attr->size);
return;
}
default:
......@@ -519,7 +515,7 @@ end_of_mods:
++fmt;
amd64_addr_attr_t const *const attr
= get_amd64_addr_attr_const(node);
amd64_emit_x87_mode_suffix(attr->insn_mode);
amd64_emit_x87_size_suffix(attr->size);
} else if (*fmt == 'P') {
++fmt;
x87_attr_t const *const attr
......@@ -586,15 +582,15 @@ emit_R:
if (mod & EMIT_IGNORE_MODE) {
emit_register(reg);
} else if (mod & EMIT_FORCE_32) {
emit_register_mode(reg, INSN_MODE_32);
emit_register_mode(reg, INSN_SIZE_32);
} else if (mod & EMIT_CONV_DEST) {
amd64_insn_mode_t src_mode = get_amd64_insn_mode(node);
amd64_insn_mode_t dest_mode = src_mode == INSN_MODE_64
? INSN_MODE_64 : INSN_MODE_32;
emit_register_mode(reg, dest_mode);
amd64_insn_size_t src_size = get_amd64_insn_size(node);
amd64_insn_size_t dest_size = src_size == INSN_SIZE_64
? INSN_SIZE_64 : INSN_SIZE_32;
emit_register_mode(reg, dest_size);
} else {
amd64_insn_mode_t insn_mode = get_amd64_insn_mode(node);
emit_register_mode(reg, insn_mode);
amd64_insn_size_t size = get_amd64_insn_size(node);
emit_register_mode(reg, size);
}
break;
}
......@@ -604,21 +600,21 @@ emit_R:
++fmt;
const amd64_shift_attr_t *attr
= get_amd64_shift_attr_const(node);
amd64_emit_insn_mode_suffix(attr->insn_mode);
amd64_emit_insn_size_suffix(attr->size);
} else if (*fmt == 'M') {
++fmt;
const amd64_movimm_attr_t *attr
= get_amd64_movimm_attr_const(node);
amd64_emit_insn_mode_suffix(attr->insn_mode);
amd64_emit_insn_size_suffix(attr->size);
} else if (*fmt == 'X') {
++fmt;
amd64_addr_attr_t const *const attr
= get_amd64_addr_attr_const(node);
amd64_emit_xmm_mode_suffix(attr->insn_mode);
amd64_emit_xmm_size_suffix(attr->size);
} else {
amd64_addr_attr_t const *const attr
= get_amd64_addr_attr_const(node);
amd64_emit_insn_mode_suffix(attr->insn_mode);
amd64_emit_insn_size_suffix(attr->size);
}
break;
}
......@@ -877,14 +873,13 @@ static void emit_amd64_jcc(const ir_node *irn)
static void emit_amd64_mov_gp(const ir_node *node)
{
const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node);
switch (attr->insn_mode) {
case INSN_MODE_8: amd64_emitf(node, "movzbq %AM, %^D0"); return;
case INSN_MODE_16: amd64_emitf(node, "movzwq %AM, %^D0"); return;
case INSN_MODE_32: amd64_emitf(node, "movl %AM, %3D0"); return;
case INSN_MODE_64: amd64_emitf(node, "movq %AM, %^D0"); return;
case INSN_MODE_80:
case INSN_MODE_128:
case INSN_MODE_INVALID:
switch (attr->size) {
case INSN_SIZE_8: amd64_emitf(node, "movzbq %AM, %^D0"); return;
case INSN_SIZE_16: amd64_emitf(node, "movzwq %AM, %^D0"); return;
case INSN_SIZE_32: amd64_emitf(node, "movl %AM, %3D0"); return;
case INSN_SIZE_64: amd64_emitf(node, "movq %AM, %^D0"); return;
case INSN_SIZE_80:
case INSN_SIZE_128:
break;
}
panic("invalid insn mode");
......
......@@ -78,14 +78,14 @@ static void transform_sub_to_neg_add(ir_node *node,
ir_node *add;
unsigned pos;
if (is_amd64_subs(node)) {
int bits = get_insn_mode_bits(attr->base.insn_mode);
unsigned bits = get_insn_size_bits(attr->base.size);
ir_tarval *tv = get_mode_one(amd64_mode_xmm);
tv = tarval_shl_unsigned(tv, bits - 1);
ir_entity *sign_bit_const = create_float_const_entity(tv);
amd64_binop_addr_attr_t xor_attr;
memset(&xor_attr, 0, sizeof(xor_attr));
xor_attr.base.insn_mode = INSN_MODE_64;
xor_attr.base.size = INSN_SIZE_64;
xor_attr.base.base.op_mode = AMD64_OP_REG_ADDR;
init_lconst_addr(&xor_attr.base.addr, sign_bit_const);
......@@ -99,7 +99,7 @@ static void transform_sub_to_neg_add(ir_node *node,
pos = pn_amd64_adds_res;
} else {
assert(is_amd64_sub(node));
ir_node *neg = new_bd_amd64_neg(dbgi, block, in2, attr->base.insn_mode);
ir_node *neg = new_bd_amd64_neg(dbgi, block, in2, attr->base.size);
sched_add_before(node, neg);
ir_node *const neg_res = be_new_Proj_reg(neg, pn_amd64_neg_res, out_reg);
......@@ -139,7 +139,7 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
load_in[mem_input] = get_irn_n(node, attr->addr.mem_input);
assert(get_irn_mode(load_in[mem_input]) == mode_M);
ir_node *const load = new_bd_amd64_mov_gp(dbgi, block, load_arity, load_in, gp_am_reqs[load_arity - 1], attr->insn_mode, AMD64_OP_ADDR, new_addr);
ir_node *const load = new_bd_amd64_mov_gp(dbgi, block, load_arity, load_in, gp_am_reqs[load_arity - 1], attr->size, AMD64_OP_ADDR, new_addr);
ir_node *const load_res = be_new_Proj_reg(load, pn_amd64_mov_gp_res, out_reg);
/* change operation */
......
......@@ -29,22 +29,22 @@
#include "bearch_amd64_t.h"
#include "gen_amd64_regalloc_if.h"
amd64_insn_mode_t get_amd64_insn_mode(const ir_node *node)
amd64_insn_size_t get_amd64_insn_size(const ir_node *node)
{
if (is_amd64_mov_imm(node)) {
const amd64_movimm_attr_t *const attr
= get_amd64_movimm_attr_const(node);
return attr->insn_mode;
return attr->size;
}
amd64_op_mode_t const op_mode = get_amd64_attr_const(node)->op_mode;
if (amd64_has_addr_attr(op_mode)) {
amd64_addr_attr_t const *const attr = get_amd64_addr_attr_const(node);
return attr->insn_mode;
return attr->size;
} else if (op_mode == AMD64_OP_CC) {
amd64_cc_attr_t const *const attr = get_amd64_cc_attr_const(node);
return attr->insn_mode;
return attr->size;
} else {
panic("Node attributes do not contain insn_mode");
panic("Node attributes do not contain insn_size");
}
}
......@@ -68,15 +68,14 @@ x87_attr_t const *amd64_get_x87_attr_const(ir_node const *const node)
return amd64_get_x87_attr((ir_node *)node);
}
int get_insn_mode_bits(amd64_insn_mode_t insn_mode)
unsigned get_insn_size_bits(amd64_insn_size_t size)
{
switch (insn_mode) {
case INSN_MODE_8: return 8;
case INSN_MODE_16: return 16;
case INSN_MODE_32: return 32;
case INSN_MODE_64: return 64;
case INSN_MODE_128: return 128;
case INSN_MODE_INVALID:
switch (size) {
case INSN_SIZE_8: return 8;
case INSN_SIZE_16: return 16;
case INSN_SIZE_32: return 32;
case INSN_SIZE_64: return 64;
case INSN_SIZE_128: return 128;
default: panic("bad insn mode");
}
}
......@@ -103,18 +102,17 @@ static const char *get_op_mode_string(amd64_op_mode_t const op_mode)
return "invalid op_mode";
}
static const char *get_insn_mode_string(amd64_insn_mode_t mode)
static const char *get_insn_size_string(amd64_insn_size_t mode)
{
switch (mode) {
case INSN_MODE_8: return "8";
case INSN_MODE_16: return "16";
case INSN_MODE_32: return "32";
case INSN_MODE_64: return "64";
case INSN_MODE_80: return "80";
case INSN_MODE_128: return "128";
case INSN_MODE_INVALID: break;
case INSN_SIZE_8: return "8";
case INSN_SIZE_16: return "16";
case INSN_SIZE_32: return "32";
case INSN_SIZE_64: return "64";
case INSN_SIZE_80: return "80";
case INSN_SIZE_128: return "128";
}
return "invalid insn_mode";
return "invalid insn_size";
}
void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason)
......@@ -154,7 +152,7 @@ void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason)
}
if (amd64_has_addr_attr(op_mode)) {
const amd64_addr_attr_t *addr_attr = get_amd64_addr_attr_const(n);
fprintf(F, "size = %s\n", get_insn_mode_string(addr_attr->insn_mode));
fprintf(F, "size = %s\n", get_insn_size_string(addr_attr->size));
x86_addr_variant_t const variant = addr_attr->addr.variant;
fprintf(F, "am variant = %s\n", x86_get_addr_variant_str(variant));
if (x86_addr_variant_has_base(variant))
......@@ -192,18 +190,18 @@ void init_amd64_switch_attributes(ir_node *node, const ir_switch_table *table,
}
void init_amd64_cc_attributes(ir_node *node, x86_condition_code_t cc,
amd64_insn_mode_t insn_mode)
amd64_insn_size_t size)
{
amd64_cc_attr_t *attr = get_amd64_cc_attr(node);
attr->cc = cc;
attr->insn_mode = insn_mode;
attr->cc = cc;
attr->size = size;
}
void init_amd64_movimm_attributes(ir_node *node, amd64_insn_mode_t insn_mode,
void init_amd64_movimm_attributes(ir_node *node, amd64_insn_size_t size,
const amd64_imm64_t *imm)
{
amd64_movimm_attr_t *attr = get_amd64_movimm_attr(node);
attr->insn_mode = insn_mode;
attr->size = size;
attr->immediate = *imm;
}
......@@ -236,7 +234,7 @@ int amd64_addr_attrs_equal(const ir_node *a, const ir_node *b)
const amd64_addr_attr_t *attr_b = get_amd64_addr_attr_const(b);
return amd64_attrs_equal(a, b)
&& amd64_addrs_equal(&attr_a->addr, &attr_b->addr)
&& attr_a->insn_mode == attr_b->insn_mode;
&& attr_a->size == attr_b->size;
}
int amd64_binop_addr_attrs_equal(const ir_node *a, const ir_node *b)
......@@ -259,7 +257,7 @@ int amd64_movimm_attrs_equal(const ir_node *const a, const ir_node *const b)
const amd64_movimm_attr_t *const attr_b = get_amd64_movimm_attr_const(b);
return amd64_attrs_equal(a, b)
&& imm64s_equal(&attr_a->immediate, &attr_b->immediate)
&& attr_a->insn_mode == attr_b->insn_mode;
&& attr_a->size == attr_b->size;
}
int amd64_shift_attrs_equal(const ir_node *const a, const ir_node *const b)
......@@ -268,7 +266,7 @@ int amd64_shift_attrs_equal(const ir_node *const a, const ir_node *const b)
const amd64_shift_attr_t *const attr_b = get_amd64_shift_attr_const(b);
return amd64_attrs_equal(a, b)
&& attr_a->immediate == attr_b->immediate
&& attr_a->insn_mode == attr_b->insn_mode;
&& attr_a->size == attr_b->size;
}
int amd64_cc_attrs_equal(const ir_node *const a, const ir_node *const b)
......
......@@ -185,8 +185,8 @@ static inline amd64_x87_binop_addr_attr_t *get_amd64_x87_binop_addr_attr(
x87_attr_t *amd64_get_x87_attr(ir_node *node);
x87_attr_t const *amd64_get_x87_attr_const(ir_node const *node);
amd64_insn_mode_t get_amd64_insn_mode(const ir_node *node);
int get_insn_mode_bits(amd64_insn_mode_t insn_mode);
amd64_insn_size_t get_amd64_insn_size(const ir_node *node);
unsigned get_insn_size_bits(amd64_insn_size_t insn_size);
/* Include the generated headers */
#include "gen_amd64_new_nodes.h"
......
......@@ -20,9 +20,9 @@ void init_amd64_switch_attributes(ir_node *node, const ir_switch_table *table,
ir_entity *table_entity);
void init_amd64_cc_attributes(ir_node *node, x86_condition_code_t cc,
amd64_insn_mode_t insn_mode);
amd64_insn_size_t size);
void init_amd64_movimm_attributes(ir_node *node, amd64_insn_mode_t insn_mode,
void init_amd64_movimm_attributes(ir_node *node, amd64_insn_size_t size,
const amd64_imm64_t *imm);
int amd64_attrs_equal(const ir_node *a, const ir_node *b);
......
......@@ -25,14 +25,13 @@ enum amd64_arch_irn_flags_t {
/** instruction data size. Keep sorted! */
typedef enum {
INSN_MODE_INVALID = 0,
INSN_MODE_8,
INSN_MODE_16,
INSN_MODE_32,
INSN_MODE_64,
INSN_MODE_80,
INSN_MODE_128,
} amd64_insn_mode_t;
INSN_SIZE_8,
INSN_SIZE_16,
INSN_SIZE_32,
INSN_SIZE_64,
INSN_SIZE_80,
INSN_SIZE_128,
} amd64_insn_size_t;
typedef enum {
AMD64_SEGMENT_DEFAULT,
......@@ -85,7 +84,7 @@ typedef struct {
typedef struct {
amd64_attr_t base;
ENUMBF(amd64_insn_mode_t) insn_mode : 3;
ENUMBF(amd64_insn_size_t) size : 3;
amd64_addr_t addr;
} amd64_addr_attr_t;
......@@ -98,21 +97,21 @@ typedef struct {
} amd64_binop_addr_attr_t;
typedef struct {
amd64_attr_t base;
ENUMBF(amd64_insn_mode_t) insn_mode : 3;
amd64_attr_t base;
ENUMBF(amd64_insn_size_t) size : 3;
uint8_t immediate;
} amd64_shift_attr_t;
typedef struct {
amd64_attr_t base;
ENUMBF(amd64_insn_mode_t) insn_mode : 3;
amd64_attr_t base;
ENUMBF(amd64_insn_size_t) size : 3;
amd64_imm64_t immediate;
} amd64_movimm_attr_t;
typedef struct {
amd64_attr_t base;
x86_condition_code_t cc;
ENUMBF(amd64_insn_mode_t) insn_mode : 3;
amd64_attr_t base;
x86_condition_code_t cc;
ENUMBF(amd64_insn_size_t) size : 3;
} amd64_cc_attr_t;
typedef struct {
......
......@@ -70,22 +70,22 @@ $mode_x87 = "x86_mode_E";
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, op_mode);",
amd64_addr_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, op_mode);\n"
."\tattr->insn_mode = insn_mode;\n"
."\tattr->size = size;\n"
."\tattr->addr = addr;",
amd64_binop_addr_attr_t =>
"be_info_init_irn(res, irn_flags, in_reqs, n_res);\n"
."\t*attr = *attr_init;",
amd64_switch_jmp_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, op_mode);\n"
."\tattr->base.insn_mode = INSN_MODE_64;\n"
."\tattr->base.size = INSN_SIZE_64;\n"
."\tattr->base.addr = *addr;\n"
."\tinit_amd64_switch_attributes(res, table, table_entity);",
amd64_cc_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, AMD64_OP_CC);\n"
."\tinit_amd64_cc_attributes(res, cc, insn_mode);",
."\tinit_amd64_cc_attributes(res, cc, size);",
amd64_movimm_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, AMD64_OP_IMM64);\n"
."\tinit_amd64_movimm_attributes(res, insn_mode, imm);",
."\tinit_amd64_movimm_attributes(res, size, imm);",
amd64_shift_attr_t =>
"be_info_init_irn(res, irn_flags, in_reqs, n_res);\n"
."\t*attr = *attr_init;\n",
......@@ -96,8 +96,8 @@ $mode_x87 = "x86_mode_E";
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, AMD64_OP_X87);\n",
amd64_x87_addr_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, op_mode);\n"
."\tattr->base.insn_mode = insn_mode;\n"
."\tattr->base.addr = addr;\n",
."\tattr->base.size = size;\n"
."\tattr->base.addr = addr;\n",
amd64_x87_binop_addr_attr_t =>
"be_info_init_irn(res, irn_flags, in_reqs, n_res);\n"
."\tattr->base = *attr_init;\n"
......@@ -134,7 +134,7 @@ my $divop = {
attr_type => "amd64_addr_attr_t",
fixed => "amd64_addr_t addr = { { .offset = 0 }, .variant = X86_ADDR_JUST_IMM };\n"
."amd64_op_mode_t op_mode = AMD64_OP_REG;\n",
attr => "amd64_insn_mode_t insn_mode",
attr => "amd64_insn_size_t size",
};
my $mulop = {
......@@ -148,7 +148,7 @@ my $mulop = {
out_reqs => [ "rax", "flags", "mem", "rdx" ],
outs => [ "res_low", "flags", "M", "res_high" ],
attr_type => "amd64_addr_attr_t",
attr => "amd64_insn_mode_t insn_mode, amd64_op_mode_t op_mode, amd64_addr_t addr",
attr => "amd64_insn_size_t size, amd64_op_mode_t op_mode, amd64_addr_t addr",
};
my $shiftop = {
......@@ -167,7 +167,7 @@ my $unop = {
ins => [ "val" ],
outs => [ "res", "flags" ],
attr_type => "amd64_addr_attr_t",
attr => "amd64_insn_mode_t insn_mode",
attr => "amd64_insn_size_t size",
fixed => "amd64_op_mode_t op_mode = AMD64_OP_REG;\n"
."amd64_addr_t addr = { { .offset = 0 }, .variant = X86_ADDR_JUST_IMM };",
};
......@@ -178,7 +178,7 @@ my $unop_out = {
out_reqs => [ "gp", "flags", "mem" ],
outs => [ "res", "flags", "M" ],
attr_type => "amd64_addr_attr_t",
attr => "amd64_insn_mode_t insn_mode, amd64_op_mode_t op_mode, amd64_addr_t addr",
attr => "amd64_insn_size_t size, amd64_op_mode_t op_mode, amd64_addr_t addr",
};
my $binopx = {
......@@ -207,7 +207,7 @@ my $cvtop2x = {
out_reqs => [ "xmm", "none", "mem" ],
outs => [ "res", "none", "M" ],
attr_type => "amd64_addr_attr_t",
attr => "amd64_insn_mode_t insn_mode, amd64_op_mode_t op_mode, amd64_addr_t addr",
attr => "amd64_insn_size_t size, amd64_op_mode_t op_mode, amd64_addr_t addr",
};
my $cvtopx2i = {
......@@ -216,7 +216,7 @@ my $cvtopx2i = {
out_reqs => [ "gp", "none", "mem" ],
outs => [ "res", "none", "M" ],