Commit 1dfae908 authored by Matthias Braun's avatar Matthias Braun
Browse files

amd64: Replace amd64_insn_size_t with x86_insn_size_t

parent 333d6983
...@@ -45,22 +45,8 @@ pmap *amd64_constants; ...@@ -45,22 +45,8 @@ pmap *amd64_constants;
ir_mode *amd64_mode_xmm; ir_mode *amd64_mode_xmm;
static int get_insn_size_bytes(amd64_insn_size_t size)
{
switch (size) {
case INSN_SIZE_8: return 1;
case INSN_SIZE_16: return 2;
case INSN_SIZE_32: return 4;
case INSN_SIZE_64: return 8;
case INSN_SIZE_128: return 16;
case INSN_SIZE_80: break;
}
panic("bad insn mode");
}
static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp,
ir_node *mem, ir_entity *ent, ir_node *mem, ir_entity *ent, x86_insn_size_t size)
amd64_insn_size_t size)
{ {
dbg_info *dbgi = get_irn_dbg_info(node); dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node); ir_node *block = get_nodes_block(node);
...@@ -82,7 +68,7 @@ static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ...@@ -82,7 +68,7 @@ static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp,
} }
static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp,
ir_entity *ent, amd64_insn_size_t size) ir_entity *ent, x86_insn_size_t size)
{ {
dbg_info *dbgi = get_irn_dbg_info(node); dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node); ir_node *block = get_nodes_block(node);
...@@ -138,23 +124,23 @@ static void transform_MemPerm(ir_node *node) ...@@ -138,23 +124,23 @@ static void transform_MemPerm(ir_node *node)
int offset = 0; int offset = 0;
do { do {
amd64_insn_size_t size; x86_insn_size_t size;
if (entsize%2 == 1) { if (entsize%2 == 1) {
size = INSN_SIZE_8; size = X86_SIZE_8;
} else if (entsize % 4 == 2) { } else if (entsize % 4 == 2) {
size = INSN_SIZE_16; size = X86_SIZE_16;
} else if (entsize % 8 == 4) { } else if (entsize % 8 == 4) {
size = INSN_SIZE_32; size = X86_SIZE_32;
} else { } else {
assert(entsize%8 == 0); assert(entsize%8 == 0);
size = INSN_SIZE_64; size = X86_SIZE_64;
} }
ir_node *push = create_push(node, node, sp, mem, inent, size); ir_node *push = create_push(node, node, sp, mem, inent, size);
sp = create_spproj(push, pn_amd64_push_am_stack); sp = create_spproj(push, pn_amd64_push_am_stack);
get_amd64_addr_attr(push)->addr.immediate.offset = offset; get_amd64_addr_attr(push)->addr.immediate.offset = offset;
unsigned bytes = get_insn_size_bytes(size); unsigned bytes = x86_bytes_from_size(size);
offset += bytes; offset += bytes;
entsize -= bytes; entsize -= bytes;
} while(entsize > 0); } while(entsize > 0);
...@@ -177,22 +163,22 @@ static void transform_MemPerm(ir_node *node) ...@@ -177,22 +163,22 @@ static void transform_MemPerm(ir_node *node)
int offset = entsize; int offset = entsize;
ir_node *pop; ir_node *pop;
do { do {
amd64_insn_size_t size; x86_insn_size_t size;
if (entsize%2 == 1) { if (entsize%2 == 1) {
size = INSN_SIZE_8; size = X86_SIZE_8;
} else if (entsize % 4 == 2) { } else if (entsize % 4 == 2) {
size = INSN_SIZE_16; size = X86_SIZE_16;
} else if (entsize % 8 == 4) { } else if (entsize % 8 == 4) {
size = INSN_SIZE_32; size = X86_SIZE_32;
} else { } else {
assert(entsize%8 == 0); assert(entsize%8 == 0);
size = INSN_SIZE_64; size = X86_SIZE_64;
} }
pop = create_pop(node, node, sp, outent, size); pop = create_pop(node, node, sp, outent, size);
sp = create_spproj(pop, pn_amd64_pop_am_stack); sp = create_spproj(pop, pn_amd64_pop_am_stack);
unsigned bytes = get_insn_size_bytes(size); unsigned bytes = x86_bytes_from_size(size);
offset -= bytes; offset -= bytes;
entsize -= bytes; entsize -= bytes;
get_amd64_addr_attr(pop)->addr.immediate.offset = offset; get_amd64_addr_attr(pop)->addr.immediate.offset = offset;
...@@ -399,13 +385,13 @@ static void amd64_set_frame_entity(ir_node *node, ir_entity *entity, ...@@ -399,13 +385,13 @@ static void amd64_set_frame_entity(ir_node *node, ir_entity *entity,
attr->addr.immediate.entity = entity; attr->addr.immediate.entity = entity;
} }
static ir_type *get_type_for_insn_size(amd64_insn_size_t const size) static ir_type *get_type_for_insn_size(x86_insn_size_t const size)
{ {
/* TODO: do not hardcode node names here */ /* TODO: do not hardcode node names here */
switch (size) { switch (size) {
case INSN_SIZE_128: return get_type_for_mode(amd64_mode_xmm); case X86_SIZE_128: return get_type_for_mode(amd64_mode_xmm);
case INSN_SIZE_80: return x86_type_E; case X86_SIZE_80: return x86_type_E;
default: return get_type_for_mode(mode_Lu); default: return get_type_for_mode(mode_Lu);
} }
} }
...@@ -519,7 +505,7 @@ static void introduce_prologue(ir_graph *const irg, bool omit_fp) ...@@ -519,7 +505,7 @@ static void introduce_prologue(ir_graph *const irg, bool omit_fp)
/* push rbp */ /* push rbp */
ir_node *const mem = get_irg_initial_mem(irg); ir_node *const mem = get_irg_initial_mem(irg);
ir_node *const initial_bp = be_get_Start_proj(irg, bp); ir_node *const initial_bp = be_get_Start_proj(irg, bp);
ir_node *const push = new_bd_amd64_push_reg(NULL, block, initial_sp, mem, initial_bp, INSN_SIZE_64); ir_node *const push = new_bd_amd64_push_reg(NULL, block, initial_sp, mem, initial_bp, X86_SIZE_64);
sched_add_after(start, push); sched_add_after(start, push);
ir_node *const curr_mem = be_new_Proj(push, pn_amd64_push_reg_M); ir_node *const curr_mem = be_new_Proj(push, pn_amd64_push_reg_M);
edges_reroute_except(mem, curr_mem, push); edges_reroute_except(mem, curr_mem, push);
...@@ -597,14 +583,14 @@ static void amd64_sp_sim(ir_node *const node, stack_pointer_state_t *state) ...@@ -597,14 +583,14 @@ static void amd64_sp_sim(ir_node *const node, stack_pointer_state_t *state)
* address, so do this first */ * address, so do this first */
if (is_amd64_pop_am(node)) { if (is_amd64_pop_am(node)) {
const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node); const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node);
state->offset -= get_insn_size_bytes(attr->base.size); state->offset -= x86_bytes_from_size(attr->base.size);
} }
amd64_determine_frameoffset(node, state->offset); amd64_determine_frameoffset(node, state->offset);
if (is_amd64_push_am(node)) { if (is_amd64_push_am(node)) {
const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node); const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node);
state->offset += get_insn_size_bytes(attr->base.size); state->offset += x86_bytes_from_size(attr->base.size);
} else if (is_amd64_push_reg(node)) { } else if (is_amd64_push_reg(node)) {
/* 64-bit register size */ /* 64-bit register size */
state->offset += AMD64_REGISTER_SIZE; state->offset += AMD64_REGISTER_SIZE;
......
...@@ -28,59 +28,59 @@ ...@@ -28,59 +28,59 @@
#include "irgwalk.h" #include "irgwalk.h"
#include "panic.h" #include "panic.h"
static char get_gp_size_suffix(amd64_insn_size_t const size) static char get_gp_size_suffix(x86_insn_size_t const size)
{ {
switch (size) { switch (size) {
case INSN_SIZE_8: return 'b'; case X86_SIZE_8: return 'b';
case INSN_SIZE_16: return 'w'; case X86_SIZE_16: return 'w';
case INSN_SIZE_32: return 'l'; case X86_SIZE_32: return 'l';
case INSN_SIZE_64: return 'q'; case X86_SIZE_64: return 'q';
case INSN_SIZE_80: case X86_SIZE_80:
case INSN_SIZE_128: case X86_SIZE_128:
break; break;
} }
panic("invalid insn mode"); panic("invalid insn mode");
} }
static void amd64_emit_insn_size_suffix(amd64_insn_size_t const size) static void amd64_emit_insn_size_suffix(x86_insn_size_t const size)
{ {
be_emit_char(get_gp_size_suffix(size)); be_emit_char(get_gp_size_suffix(size));
} }
static char get_xmm_size_suffix(amd64_insn_size_t const size) static char get_xmm_size_suffix(x86_insn_size_t const size)
{ {
switch (size) { switch (size) {
case INSN_SIZE_32: return 's'; case X86_SIZE_32: return 's';
case INSN_SIZE_64: return 'd'; case X86_SIZE_64: return 'd';
case INSN_SIZE_128: return 'q'; case X86_SIZE_128: return 'q';
case INSN_SIZE_8: case X86_SIZE_8:
case INSN_SIZE_16: case X86_SIZE_16:
case INSN_SIZE_80: case X86_SIZE_80:
break; break;
} }
panic("invalid insn mode"); panic("invalid insn mode");
} }
static void amd64_emit_xmm_size_suffix(amd64_insn_size_t const size) static void amd64_emit_xmm_size_suffix(x86_insn_size_t const size)
{ {
be_emit_char(get_xmm_size_suffix(size)); be_emit_char(get_xmm_size_suffix(size));
} }
static char get_x87_size_suffix(amd64_insn_size_t const size) static char get_x87_size_suffix(x86_insn_size_t const size)
{ {
switch (size) { switch (size) {
case INSN_SIZE_32: return 's'; case X86_SIZE_32: return 's';
case INSN_SIZE_64: return 'l'; case X86_SIZE_64: return 'l';
case INSN_SIZE_80: return 't'; case X86_SIZE_80: return 't';
case INSN_SIZE_8: case X86_SIZE_8:
case INSN_SIZE_16: case X86_SIZE_16:
case INSN_SIZE_128: case X86_SIZE_128:
break; break;
} }
panic("Invalid insn mode"); panic("Invalid insn mode");
} }
static void amd64_emit_x87_size_suffix(amd64_insn_size_t const size) static void amd64_emit_x87_size_suffix(x86_insn_size_t const size)
{ {
be_emit_char(get_x87_size_suffix(size)); be_emit_char(get_x87_size_suffix(size));
} }
...@@ -172,29 +172,29 @@ static void emit_register(const arch_register_t *reg) ...@@ -172,29 +172,29 @@ static void emit_register(const arch_register_t *reg)
} }
static const char *get_register_name_mode(const arch_register_t *reg, static const char *get_register_name_mode(const arch_register_t *reg,
const amd64_insn_size_t size) const x86_insn_size_t size)
{ {
switch (size) { switch (size) {
case INSN_SIZE_8: return get_register_name_8bit(reg); case X86_SIZE_8: return get_register_name_8bit(reg);
case INSN_SIZE_16: return get_register_name_16bit(reg); case X86_SIZE_16: return get_register_name_16bit(reg);
case INSN_SIZE_32: return get_register_name_32bit(reg); case X86_SIZE_32: return get_register_name_32bit(reg);
case INSN_SIZE_64: case X86_SIZE_64:
case INSN_SIZE_80: case X86_SIZE_80:
case INSN_SIZE_128: return reg->name; case X86_SIZE_128: return reg->name;
break; break;
} }
panic("invalid mode"); panic("invalid mode");
} }
static void emit_register_sized(const arch_register_t *reg, static void emit_register_sized(const arch_register_t *reg,
const amd64_insn_size_t size) const x86_insn_size_t size)
{ {
be_emit_char('%'); be_emit_char('%');
be_emit_string(get_register_name_mode(reg, size)); be_emit_string(get_register_name_mode(reg, size));
} }
static void emit_register_mode(const arch_register_t *reg, static void emit_register_mode(const arch_register_t *reg,
amd64_insn_size_t size) x86_insn_size_t size)
{ {
if (reg->cls == &amd64_reg_classes[CLASS_amd64_xmm]) { if (reg->cls == &amd64_reg_classes[CLASS_amd64_xmm]) {
emit_register(reg); emit_register(reg);
...@@ -315,7 +315,7 @@ static void emit_shiftop(const ir_node *const node) ...@@ -315,7 +315,7 @@ static void emit_shiftop(const ir_node *const node)
case AMD64_OP_SHIFT_REG: { case AMD64_OP_SHIFT_REG: {
const arch_register_t *reg0 = arch_get_irn_register_in(node, 0); const arch_register_t *reg0 = arch_get_irn_register_in(node, 0);
const arch_register_t *reg1 = arch_get_irn_register_in(node, 1); const arch_register_t *reg1 = arch_get_irn_register_in(node, 1);
emit_register_mode(reg1, INSN_SIZE_8); emit_register_mode(reg1, X86_SIZE_8);
be_emit_cstring(", "); be_emit_cstring(", ");
emit_register_mode(reg0, attr->base.size); emit_register_mode(reg0, attr->base.size);
return; return;
...@@ -487,12 +487,12 @@ emit_R: ...@@ -487,12 +487,12 @@ emit_R:
if (mod & EMIT_IGNORE_MODE) { if (mod & EMIT_IGNORE_MODE) {
emit_register(reg); emit_register(reg);
} else if (mod & EMIT_FORCE_32) { } else if (mod & EMIT_FORCE_32) {
emit_register_mode(reg, INSN_SIZE_32); emit_register_mode(reg, X86_SIZE_32);
} else if (mod & EMIT_CONV_DEST) { } else if (mod & EMIT_CONV_DEST) {
amd64_attr_t const *const attr = get_amd64_attr_const(node); amd64_attr_t const *const attr = get_amd64_attr_const(node);
amd64_insn_size_t src_size = attr->size; x86_insn_size_t src_size = attr->size;
amd64_insn_size_t dest_size = src_size == INSN_SIZE_64 x86_insn_size_t dest_size = src_size == X86_SIZE_64
? INSN_SIZE_64 : INSN_SIZE_32; ? X86_SIZE_64 : X86_SIZE_32;
emit_register_mode(reg, dest_size); emit_register_mode(reg, dest_size);
} else { } else {
amd64_attr_t const *const attr = get_amd64_attr_const(node); amd64_attr_t const *const attr = get_amd64_attr_const(node);
...@@ -753,12 +753,12 @@ static void emit_amd64_mov_gp(const ir_node *node) ...@@ -753,12 +753,12 @@ static void emit_amd64_mov_gp(const ir_node *node)
{ {
amd64_attr_t const *const attr = get_amd64_attr_const(node); amd64_attr_t const *const attr = get_amd64_attr_const(node);
switch (attr->size) { switch (attr->size) {
case INSN_SIZE_8: amd64_emitf(node, "movzbq %AM, %^D0"); return; case X86_SIZE_8: amd64_emitf(node, "movzbq %AM, %^D0"); return;
case INSN_SIZE_16: amd64_emitf(node, "movzwq %AM, %^D0"); return; case X86_SIZE_16: amd64_emitf(node, "movzwq %AM, %^D0"); return;
case INSN_SIZE_32: amd64_emitf(node, "movl %AM, %3D0"); return; case X86_SIZE_32: amd64_emitf(node, "movl %AM, %3D0"); return;
case INSN_SIZE_64: amd64_emitf(node, "movq %AM, %^D0"); return; case X86_SIZE_64: amd64_emitf(node, "movq %AM, %^D0"); return;
case INSN_SIZE_80: case X86_SIZE_80:
case INSN_SIZE_128: case X86_SIZE_128:
break; break;
} }
panic("invalid insn mode"); panic("invalid insn mode");
......
...@@ -64,7 +64,7 @@ static void transform_sub_to_neg_add(ir_node *node, ...@@ -64,7 +64,7 @@ static void transform_sub_to_neg_add(ir_node *node,
ir_node *add; ir_node *add;
unsigned pos; unsigned pos;
if (is_amd64_subs(node)) { if (is_amd64_subs(node)) {
unsigned bits = amd64_get_insn_size_bits(attr->base.base.size); unsigned bits = x86_bytes_from_size(attr->base.base.size) * 8;
ir_tarval *tv = get_mode_one(amd64_mode_xmm); ir_tarval *tv = get_mode_one(amd64_mode_xmm);
tv = tarval_shl_unsigned(tv, bits - 1); tv = tarval_shl_unsigned(tv, bits - 1);
ir_entity *sign_bit_const = create_float_const_entity(tv); ir_entity *sign_bit_const = create_float_const_entity(tv);
...@@ -73,7 +73,7 @@ static void transform_sub_to_neg_add(ir_node *node, ...@@ -73,7 +73,7 @@ static void transform_sub_to_neg_add(ir_node *node,
.base = { .base = {
.base = { .base = {
.op_mode = AMD64_OP_REG_ADDR, .op_mode = AMD64_OP_REG_ADDR,
.size = INSN_SIZE_64, .size = X86_SIZE_64,
}, },
}, },
}; };
......
...@@ -49,19 +49,6 @@ x87_attr_t const *amd64_get_x87_attr_const(ir_node const *const node) ...@@ -49,19 +49,6 @@ x87_attr_t const *amd64_get_x87_attr_const(ir_node const *const node)
return amd64_get_x87_attr((ir_node *)node); return amd64_get_x87_attr((ir_node *)node);
} }
unsigned amd64_get_insn_size_bits(amd64_insn_size_t const size)
{
switch (size) {
case INSN_SIZE_8: return 8;
case INSN_SIZE_16: return 16;
case INSN_SIZE_32: return 32;
case INSN_SIZE_64: return 64;
case INSN_SIZE_80: return 80;
case INSN_SIZE_128: return 128;
}
panic("bad insn mode");
}
static const char *get_op_mode_string(amd64_op_mode_t const op_mode) static const char *get_op_mode_string(amd64_op_mode_t const op_mode)
{ {
switch (op_mode) { switch (op_mode) {
...@@ -84,19 +71,6 @@ static const char *get_op_mode_string(amd64_op_mode_t const op_mode) ...@@ -84,19 +71,6 @@ static const char *get_op_mode_string(amd64_op_mode_t const op_mode)
return "invalid op_mode"; return "invalid op_mode";
} }
static const char *get_insn_size_string(amd64_insn_size_t mode)
{
switch (mode) {
case INSN_SIZE_8: return "8";
case INSN_SIZE_16: return "16";
case INSN_SIZE_32: return "32";
case INSN_SIZE_64: return "64";
case INSN_SIZE_80: return "80";
case INSN_SIZE_128: return "128";
}
return "invalid insn_size";
}
void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason) void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason)
{ {
switch (reason) { switch (reason) {
...@@ -114,7 +88,7 @@ void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason) ...@@ -114,7 +88,7 @@ void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason)
const amd64_attr_t *attr = get_amd64_attr_const(n); const amd64_attr_t *attr = get_amd64_attr_const(n);
amd64_op_mode_t const op_mode = attr->op_mode; amd64_op_mode_t const op_mode = attr->op_mode;
fprintf(F, "mode = %s\n", get_op_mode_string(op_mode)); fprintf(F, "mode = %s\n", get_op_mode_string(op_mode));
fprintf(F, "size = %s\n", get_insn_size_string(attr->size)); fprintf(F, "size = %u\n", x86_bytes_from_size(attr->size));
switch (op_mode) { switch (op_mode) {
case AMD64_OP_ADDR_REG: case AMD64_OP_ADDR_REG:
case AMD64_OP_REG_ADDR: { case AMD64_OP_REG_ADDR: {
...@@ -152,7 +126,7 @@ void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason) ...@@ -152,7 +126,7 @@ void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason)
void init_amd64_attributes(ir_node *node, arch_irn_flags_t flags, void init_amd64_attributes(ir_node *node, arch_irn_flags_t flags,
const arch_register_req_t **in_reqs, const arch_register_req_t **in_reqs,
int n_res, amd64_op_mode_t op_mode, int n_res, amd64_op_mode_t op_mode,
amd64_insn_size_t size) x86_insn_size_t size)
{ {
be_info_init_irn(node, flags, in_reqs, n_res); be_info_init_irn(node, flags, in_reqs, n_res);
amd64_attr_t *attr = get_amd64_attr(node); amd64_attr_t *attr = get_amd64_attr(node);
......
...@@ -185,8 +185,6 @@ static inline amd64_x87_binop_addr_attr_t *get_amd64_x87_binop_addr_attr( ...@@ -185,8 +185,6 @@ static inline amd64_x87_binop_addr_attr_t *get_amd64_x87_binop_addr_attr(
x87_attr_t *amd64_get_x87_attr(ir_node *node); x87_attr_t *amd64_get_x87_attr(ir_node *node);
x87_attr_t const *amd64_get_x87_attr_const(ir_node const *node); x87_attr_t const *amd64_get_x87_attr_const(ir_node const *node);
unsigned amd64_get_insn_size_bits(amd64_insn_size_t insn_size);
/* Include the generated headers */ /* Include the generated headers */
#include "gen_amd64_new_nodes.h" #include "gen_amd64_new_nodes.h"
......
...@@ -17,7 +17,7 @@ void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason); ...@@ -17,7 +17,7 @@ void amd64_dump_node(FILE *F, const ir_node *n, dump_reason_t reason);
void init_amd64_attributes(ir_node *node, arch_irn_flags_t flags, void init_amd64_attributes(ir_node *node, arch_irn_flags_t flags,
const arch_register_req_t **in_reqs, const arch_register_req_t **in_reqs,
int n_res, amd64_op_mode_t op_mode, int n_res, amd64_op_mode_t op_mode,
amd64_insn_size_t size); x86_insn_size_t size);
void init_amd64_switch_attributes(ir_node *node, const ir_switch_table *table, void init_amd64_switch_attributes(ir_node *node, const ir_switch_table *table,
ir_entity *table_entity); ir_entity *table_entity);
......
...@@ -23,16 +23,6 @@ enum amd64_arch_irn_flags_t { ...@@ -23,16 +23,6 @@ enum amd64_arch_irn_flags_t {
amd64_arch_irn_flag_commutative_binop = arch_irn_flag_backend << 0, amd64_arch_irn_flag_commutative_binop = arch_irn_flag_backend << 0,
}; };
/** instruction data size. Keep sorted! */
typedef enum amd64_insn_size_t {
INSN_SIZE_8,
INSN_SIZE_16,
INSN_SIZE_32,
INSN_SIZE_64,
INSN_SIZE_80,
INSN_SIZE_128,
} amd64_insn_size_t;
typedef enum amd64_op_mode_t { typedef enum amd64_op_mode_t {
AMD64_OP_NONE, AMD64_OP_NONE,
AMD64_OP_ADDR, AMD64_OP_ADDR,
...@@ -59,8 +49,8 @@ typedef struct amd64_imm64_t { ...@@ -59,8 +49,8 @@ typedef struct amd64_imm64_t {
typedef struct amd64_attr_t { typedef struct amd64_attr_t {
except_attr exc; /**< the exception attribute. MUST be the first one. */ except_attr exc; /**< the exception attribute. MUST be the first one. */
ENUMBF(amd64_op_mode_t) op_mode : 5; ENUMBF(amd64_op_mode_t) op_mode : 5;
ENUMBF(amd64_insn_size_t) size : 3; ENUMBF(x86_insn_size_t) size : 3;
} amd64_attr_t; } amd64_attr_t;
typedef struct amd64_addr_attr_t { typedef struct amd64_addr_attr_t {
......
...@@ -100,7 +100,7 @@ static void peephole_amd64_mov_imm(ir_node *const node) ...@@ -100,7 +100,7 @@ static void peephole_amd64_mov_imm(ir_node *const node)
/* mov $0, %reg -> xorl %reg, %reg */ /* mov $0, %reg -> xorl %reg, %reg */
dbg_info *const dbgi = get_irn_dbg_info(node); dbg_info *const dbgi = get_irn_dbg_info(node);
ir_node *const block = get_nodes_block(node); ir_node *const block = get_nodes_block(node);
ir_node *const xor = new_bd_amd64_xor_0(dbgi, block, INSN_SIZE_32); ir_node *const xor = new_bd_amd64_xor_0(dbgi, block, X86_SIZE_32);
arch_register_t const *const reg = arch_get_irn_register_out(node, pn_amd64_mov_imm_res); arch_register_t const *const reg = arch_get_irn_register_out(node, pn_amd64_mov_imm_res);
arch_set_irn_register_out(xor, pn_amd64_xor_0_res, reg); arch_set_irn_register_out(xor, pn_amd64_xor_0_res, reg);
sched_add_before(node, xor); sched_add_before(node, xor);
......
...@@ -91,7 +91,7 @@ $mode_x87 = "x86_mode_E"; ...@@ -91,7 +91,7 @@ $mode_x87 = "x86_mode_E";
"be_info_init_irn(res, irn_flags, in_reqs, n_res);\n" "be_info_init_irn(res, irn_flags, in_reqs, n_res);\n"
."\t*attr = *attr_init;", ."\t*attr = *attr_init;",
amd64_x87_attr_t => amd64_x87_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, AMD64_OP_X87, INSN_SIZE_80);\n", "init_amd64_attributes(res, irn_flags, in_reqs, n_res, AMD64_OP_X87, X86_SIZE_80);\n",
amd64_x87_addr_attr_t => amd64_x87_addr_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, op_mode, size);\n"