Commit 2a6bdbaf authored by Matthias Braun's avatar Matthias Braun
Browse files

amd64: rename nodes to the instructions they produce

parent a3e04ad5
...@@ -359,7 +359,7 @@ static void amd64_emit_am(const ir_node *const node, bool indirect_star) ...@@ -359,7 +359,7 @@ static void amd64_emit_am(const ir_node *const node, bool indirect_star)
static amd64_insn_mode_t get_amd64_insn_mode(const ir_node *node) static amd64_insn_mode_t get_amd64_insn_mode(const ir_node *node)
{ {
if (is_amd64_MovImm(node)) { if (is_amd64_mov_imm(node)) {
const amd64_movimm_attr_t *const attr const amd64_movimm_attr_t *const attr
= get_amd64_movimm_attr_const(node); = get_amd64_movimm_attr_const(node);
return attr->insn_mode; return attr->insn_mode;
...@@ -591,7 +591,7 @@ static ir_node *sched_next_block(const ir_node *block) ...@@ -591,7 +591,7 @@ static ir_node *sched_next_block(const ir_node *block)
/** /**
* Emit a Jmp. * Emit a Jmp.
*/ */
static void emit_amd64_Jmp(const ir_node *node) static void emit_amd64_jmp(const ir_node *node)
{ {
ir_node *block, *next_block; ir_node *block, *next_block;
...@@ -607,18 +607,19 @@ static void emit_amd64_Jmp(const ir_node *node) ...@@ -607,18 +607,19 @@ static void emit_amd64_Jmp(const ir_node *node)
} }
} }
static void emit_amd64_SwitchJmp(const ir_node *node) static void emit_amd64_jmp_switch(const ir_node *node)
{ {
const amd64_switch_jmp_attr_t *attr = get_amd64_switch_jmp_attr_const(node); const amd64_switch_jmp_attr_t *attr = get_amd64_switch_jmp_attr_const(node);
amd64_emitf(node, "jmp *%E(,%^S0,8)", attr->table_entity); amd64_emitf(node, "jmp *%E(,%^S0,8)", attr->table_entity);
be_emit_jump_table(node, attr->table, attr->table_entity, get_cfop_target_block); be_emit_jump_table(node, attr->table, attr->table_entity,
get_cfop_target_block);
} }
/** /**
* Emit a Compare with conditional branch. * Emit a Compare with conditional branch.
*/ */
static void emit_amd64_Jcc(const ir_node *irn) static void emit_amd64_jcc(const ir_node *irn)
{ {
const ir_node *proj_true = NULL; const ir_node *proj_true = NULL;
const ir_node *proj_false = NULL; const ir_node *proj_false = NULL;
...@@ -673,7 +674,7 @@ static void emit_amd64_Jcc(const ir_node *irn) ...@@ -673,7 +674,7 @@ static void emit_amd64_Jcc(const ir_node *irn)
} }
} }
static void emit_amd64_Mov(const ir_node *node) static void emit_amd64_mov_gp(const ir_node *node)
{ {
const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node); const amd64_addr_attr_t *attr = get_amd64_addr_attr_const(node);
switch (attr->insn_mode) { switch (attr->insn_mode) {
...@@ -756,10 +757,10 @@ static void amd64_register_emitters(void) ...@@ -756,10 +757,10 @@ static void amd64_register_emitters(void)
/* register all emitter functions defined in spec */ /* register all emitter functions defined in spec */
amd64_register_spec_emitters(); amd64_register_spec_emitters();
be_set_emitter(op_amd64_Jcc, emit_amd64_Jcc); be_set_emitter(op_amd64_jcc, emit_amd64_jcc);
be_set_emitter(op_amd64_Jmp, emit_amd64_Jmp); be_set_emitter(op_amd64_jmp, emit_amd64_jmp);
be_set_emitter(op_amd64_Mov, emit_amd64_Mov); be_set_emitter(op_amd64_mov_gp, emit_amd64_mov_gp);
be_set_emitter(op_amd64_SwitchJmp, emit_amd64_SwitchJmp); be_set_emitter(op_amd64_jmp_switch, emit_amd64_jmp_switch);
be_set_emitter(op_be_Copy, emit_be_Copy); be_set_emitter(op_be_Copy, emit_be_Copy);
be_set_emitter(op_be_CopyKeep, emit_be_Copy); be_set_emitter(op_be_CopyKeep, emit_be_Copy);
be_set_emitter(op_be_IncSP, emit_be_IncSP); be_set_emitter(op_be_IncSP, emit_be_IncSP);
......
...@@ -77,7 +77,7 @@ static void transform_sub_to_neg_add(ir_node *node, ...@@ -77,7 +77,7 @@ static void transform_sub_to_neg_add(ir_node *node,
const amd64_binop_addr_attr_t *attr = get_amd64_binop_addr_attr(node); const amd64_binop_addr_attr_t *attr = get_amd64_binop_addr_attr(node);
ir_node *add, *add_res; ir_node *add, *add_res;
if (is_amd64_xSubs(node)) { if (is_amd64_subs(node)) {
ir_tarval *tv = create_sign_tv(amd64_mode_xmm); ir_tarval *tv = create_sign_tv(amd64_mode_xmm);
ir_entity *sign_bit_const = create_float_const_entity(irg, tv); ir_entity *sign_bit_const = create_float_const_entity(irg, tv);
...@@ -90,28 +90,28 @@ static void transform_sub_to_neg_add(ir_node *node, ...@@ -90,28 +90,28 @@ static void transform_sub_to_neg_add(ir_node *node,
xor_attr.base.addr.immediate.entity = sign_bit_const; xor_attr.base.addr.immediate.entity = sign_bit_const;
ir_node *xor_in[] = { in2 }; ir_node *xor_in[] = { in2 };
ir_node *xor = new_bd_amd64_xXorp(dbgi, block, ARRAY_SIZE(xor_in), ir_node *xor = new_bd_amd64_xorp(dbgi, block, ARRAY_SIZE(xor_in),
xor_in, &xor_attr); xor_in, &xor_attr);
ir_node *neg = new_r_Proj(xor, amd64_mode_xmm, pn_amd64_xXorp_res); ir_node *neg = new_r_Proj(xor, amd64_mode_xmm, pn_amd64_xorp_res);
sched_add_before(node, xor); sched_add_before(node, xor);
arch_set_irn_register(neg, in2_reg); arch_set_irn_register(neg, in2_reg);
ir_node *in[] = { neg, in1 }; ir_node *in[] = { neg, in1 };
add = new_bd_amd64_xAdds(dbgi, block, ARRAY_SIZE(in), in, attr); add = new_bd_amd64_adds(dbgi, block, ARRAY_SIZE(in), in, attr);
add_res = new_r_Proj(add, amd64_mode_xmm, pn_amd64_xAdds_res); add_res = new_r_Proj(add, amd64_mode_xmm, pn_amd64_adds_res);
} else { } else {
assert(is_amd64_Sub(node)); assert(is_amd64_sub(node));
ir_node *neg = new_bd_amd64_Neg(dbgi, block, in2, attr->base.insn_mode); ir_node *neg = new_bd_amd64_neg(dbgi, block, in2, attr->base.insn_mode);
arch_set_irn_register_out(neg, pn_amd64_Neg_res, out_reg); arch_set_irn_register_out(neg, pn_amd64_neg_res, out_reg);
sched_add_before(node, neg); sched_add_before(node, neg);
ir_node *neg_res ir_node *neg_res
= new_r_Proj(neg, amd64_reg_classes[CLASS_amd64_gp].mode, = new_r_Proj(neg, amd64_reg_classes[CLASS_amd64_gp].mode,
pn_amd64_Neg_res); pn_amd64_neg_res);
ir_node *in[] = { neg_res, in1 }; ir_node *in[] = { neg_res, in1 };
add = new_bd_amd64_Add(dbgi, block, ARRAY_SIZE(in), in, attr); add = new_bd_amd64_add(dbgi, block, ARRAY_SIZE(in), in, attr);
add_res = new_r_Proj(add, mode_Lu, pn_amd64_Add_res); add_res = new_r_Proj(add, mode_Lu, pn_amd64_add_res);
} }
arch_set_irn_register(add_res, out_reg); arch_set_irn_register(add_res, out_reg);
...@@ -144,9 +144,10 @@ static ir_node *amd64_turn_back_am(ir_node *node) ...@@ -144,9 +144,10 @@ static ir_node *amd64_turn_back_am(ir_node *node)
new_addr.mem_input = load_arity; new_addr.mem_input = load_arity;
load_in[load_arity++] = get_irn_n(node, attr->addr.mem_input); load_in[load_arity++] = get_irn_n(node, attr->addr.mem_input);
ir_node *load = new_bd_amd64_Mov(dbgi, block, load_arity, load_in, ir_node *load = new_bd_amd64_mov_gp(dbgi, block, load_arity, load_in,
attr->insn_mode, AMD64_OP_ADDR, new_addr); attr->insn_mode, AMD64_OP_ADDR,
ir_node *load_res = new_r_Proj(load, mode_Lu, pn_amd64_Mov_res); new_addr);
ir_node *load_res = new_r_Proj(load, mode_Lu, pn_amd64_mov_gp_res);
/* change operation */ /* change operation */
const amd64_binop_addr_attr_t *binop_attr const amd64_binop_addr_attr_t *binop_attr
...@@ -164,7 +165,7 @@ static ir_node *amd64_turn_back_am(ir_node *node) ...@@ -164,7 +165,7 @@ static ir_node *amd64_turn_back_am(ir_node *node)
ir_node *out = get_edge_src_irn(edge); ir_node *out = get_edge_src_irn(edge);
if (get_irn_mode(out) == mode_M) { if (get_irn_mode(out) == mode_M) {
set_Proj_pred(out, load); set_Proj_pred(out, load);
set_Proj_num(out, pn_amd64_Mov_M); set_Proj_num(out, pn_amd64_mov_gp_M);
break; break;
} }
} }
...@@ -212,7 +213,7 @@ swap:; ...@@ -212,7 +213,7 @@ swap:;
if (res) if (res)
return; return;
if (is_amd64_Sub(node) || is_amd64_xSubs(node)) { if (is_amd64_sub(node) || is_amd64_subs(node)) {
transform_sub_to_neg_add(node, out_reg); transform_sub_to_neg_add(node, out_reg);
return; return;
} }
......
...@@ -57,8 +57,8 @@ static inline bool amd64_has_addr_attr(const ir_node *node) ...@@ -57,8 +57,8 @@ static inline bool amd64_has_addr_attr(const ir_node *node)
|| attr->op_mode == AMD64_OP_UNOP_REG || attr->op_mode == AMD64_OP_UNOP_REG
|| attr->op_mode == AMD64_OP_RAX_ADDR || attr->op_mode == AMD64_OP_RAX_ADDR
|| attr->op_mode == AMD64_OP_RAX_REG) || attr->op_mode == AMD64_OP_RAX_REG)
&& (get_irn_op(node) != op_amd64_Xor0) && (get_irn_op(node) != op_amd64_xor_0)
&& (get_irn_op(node) != op_amd64_xXorp0); && (get_irn_op(node) != op_amd64_xorpd_0);
} }
static inline amd64_addr_attr_t *get_amd64_addr_attr(ir_node *node) static inline amd64_addr_attr_t *get_amd64_addr_attr(ir_node *node)
...@@ -110,39 +110,39 @@ static inline amd64_shift_attr_t *get_amd64_shift_attr(ir_node *node) ...@@ -110,39 +110,39 @@ static inline amd64_shift_attr_t *get_amd64_shift_attr(ir_node *node)
static inline const amd64_switch_jmp_attr_t *get_amd64_switch_jmp_attr_const( static inline const amd64_switch_jmp_attr_t *get_amd64_switch_jmp_attr_const(
const ir_node *node) const ir_node *node)
{ {
assert(is_amd64_SwitchJmp(node)); assert(is_amd64_jmp_switch(node));
return (const amd64_switch_jmp_attr_t*)get_irn_generic_attr_const(node); return (const amd64_switch_jmp_attr_t*)get_irn_generic_attr_const(node);
} }
static inline amd64_switch_jmp_attr_t *get_amd64_switch_jmp_attr(ir_node *node) static inline amd64_switch_jmp_attr_t *get_amd64_switch_jmp_attr(ir_node *node)
{ {
assert(is_amd64_SwitchJmp(node)); assert(is_amd64_jmp_switch(node));
return (amd64_switch_jmp_attr_t*)get_irn_generic_attr(node); return (amd64_switch_jmp_attr_t*)get_irn_generic_attr(node);
} }
static inline const amd64_cc_attr_t *get_amd64_cc_attr_const( static inline const amd64_cc_attr_t *get_amd64_cc_attr_const(
const ir_node *node) const ir_node *node)
{ {
assert(is_amd64_Jcc(node)); assert(is_amd64_jcc(node));
return (const amd64_cc_attr_t*)get_irn_generic_attr_const(node); return (const amd64_cc_attr_t*)get_irn_generic_attr_const(node);
} }
static inline amd64_cc_attr_t *get_amd64_cc_attr(ir_node *node) static inline amd64_cc_attr_t *get_amd64_cc_attr(ir_node *node)
{ {
assert(is_amd64_Jcc(node)); assert(is_amd64_jcc(node));
return (amd64_cc_attr_t*)get_irn_generic_attr(node); return (amd64_cc_attr_t*)get_irn_generic_attr(node);
} }
static inline const amd64_movimm_attr_t *get_amd64_movimm_attr_const( static inline const amd64_movimm_attr_t *get_amd64_movimm_attr_const(
const ir_node *node) const ir_node *node)
{ {
assert(is_amd64_MovImm(node)); assert(is_amd64_mov_imm(node));
return (const amd64_movimm_attr_t*)get_irn_generic_attr_const(node); return (const amd64_movimm_attr_t*)get_irn_generic_attr_const(node);
} }
static inline amd64_movimm_attr_t *get_amd64_movimm_attr(ir_node *node) static inline amd64_movimm_attr_t *get_amd64_movimm_attr(ir_node *node)
{ {
assert(is_amd64_MovImm(node)); assert(is_amd64_mov_imm(node));
return (amd64_movimm_attr_t*)get_irn_generic_attr(node); return (amd64_movimm_attr_t*)get_irn_generic_attr(node);
} }
......
...@@ -87,7 +87,7 @@ $default_copy_attr = "amd64_copy_attr"; ...@@ -87,7 +87,7 @@ $default_copy_attr = "amd64_copy_attr";
); );
%nodes = ( %nodes = (
PushAM => { push_am => {
op_flags => [ "uses_memory" ], op_flags => [ "uses_memory" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "rsp:I|S", "none" ] }, reg_req => { out => [ "rsp:I|S", "none" ] },
...@@ -99,7 +99,7 @@ PushAM => { ...@@ -99,7 +99,7 @@ PushAM => {
emit => "push%M %A", emit => "push%M %A",
}, },
PushRbp => { push_rbp => {
op_flags => [ "uses_memory" ], op_flags => [ "uses_memory" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { in => [ "rsp" ], out => [ "rsp:I|S" ] }, reg_req => { in => [ "rsp" ], out => [ "rsp:I|S" ] },
...@@ -109,7 +109,7 @@ PushRbp => { ...@@ -109,7 +109,7 @@ PushRbp => {
emit => "pushq %%rbp", emit => "pushq %%rbp",
}, },
PopAM => { pop_am => {
op_flags => [ "uses_memory" ], op_flags => [ "uses_memory" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "rsp:I|S", "none" ] }, reg_req => { out => [ "rsp:I|S", "none" ] },
...@@ -121,7 +121,7 @@ PopAM => { ...@@ -121,7 +121,7 @@ PopAM => {
emit => "pop%M %A", emit => "pop%M %A",
}, },
SubSP => { sub_sp => {
state => "pinned", state => "pinned",
reg_req => { out => [ "rsp:I|S", "gp", "none" ] }, reg_req => { out => [ "rsp:I|S", "gp", "none" ] },
outs => [ "stack", "addr", "M" ], outs => [ "stack", "addr", "M" ],
...@@ -133,7 +133,7 @@ SubSP => { ...@@ -133,7 +133,7 @@ SubSP => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
Leave => { leave => {
op_flags => [ "uses_memory" ], op_flags => [ "uses_memory" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { in => [ "rbp" ], out => [ "rbp:I", "rbp:I|S" ] }, reg_req => { in => [ "rbp" ], out => [ "rbp:I", "rbp:I|S" ] },
...@@ -142,7 +142,7 @@ Leave => { ...@@ -142,7 +142,7 @@ Leave => {
emit => "leave", emit => "leave",
}, },
Add => { add => {
irn_flags => [ "rematerializable", "commutative" ], irn_flags => [ "rematerializable", "commutative" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "flags", "none" ] }, reg_req => { out => [ "gp", "flags", "none" ] },
...@@ -154,7 +154,7 @@ Add => { ...@@ -154,7 +154,7 @@ Add => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
And => { and => {
irn_flags => [ "rematerializable", "commutative" ], irn_flags => [ "rematerializable", "commutative" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "flags", "none" ] }, reg_req => { out => [ "gp", "flags", "none" ] },
...@@ -167,7 +167,7 @@ And => { ...@@ -167,7 +167,7 @@ And => {
}, },
Div => { div => {
state => "pinned", state => "pinned",
reg_req => { out => [ "rax", "flags", "none", "rdx" ] }, reg_req => { out => [ "rax", "flags", "none", "rdx" ] },
arity => "variable", arity => "variable",
...@@ -180,7 +180,7 @@ Div => { ...@@ -180,7 +180,7 @@ Div => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
IDiv => { idiv => {
state => "pinned", state => "pinned",
reg_req => { out => [ "rax", "flags", "none", "rdx" ] }, reg_req => { out => [ "rax", "flags", "none", "rdx" ] },
arity => "variable", arity => "variable",
...@@ -193,7 +193,7 @@ IDiv => { ...@@ -193,7 +193,7 @@ IDiv => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
IMul => { imul => {
irn_flags => [ "rematerializable", "commutative" ], irn_flags => [ "rematerializable", "commutative" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "flags", "none" ] }, reg_req => { out => [ "gp", "flags", "none" ] },
...@@ -205,7 +205,7 @@ IMul => { ...@@ -205,7 +205,7 @@ IMul => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
IMul1Op => { imul_1op => {
# Do not rematerialize this node # Do not rematerialize this node
# TODO: should mark this commutative as soon as the backend code # TODO: should mark this commutative as soon as the backend code
# can handle this special case # can handle this special case
...@@ -220,7 +220,7 @@ IMul1Op => { ...@@ -220,7 +220,7 @@ IMul1Op => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
Mul => { mul => {
# Do not rematerialize this node # Do not rematerialize this node
# It produces 2 results and has strict constraints # It produces 2 results and has strict constraints
state => "exc_pinned", state => "exc_pinned",
...@@ -233,7 +233,7 @@ Mul => { ...@@ -233,7 +233,7 @@ Mul => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
Or => { or => {
irn_flags => [ "rematerializable", "commutative" ], irn_flags => [ "rematerializable", "commutative" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "flags", "none" ] }, reg_req => { out => [ "gp", "flags", "none" ] },
...@@ -245,7 +245,7 @@ Or => { ...@@ -245,7 +245,7 @@ Or => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
Shl => { shl => {
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
reg_req => { out => [ "gp", "flags" ] }, reg_req => { out => [ "gp", "flags" ] },
outs => [ "res", "flags" ], outs => [ "res", "flags" ],
...@@ -256,7 +256,7 @@ Shl => { ...@@ -256,7 +256,7 @@ Shl => {
modified_flags => $status_flags modified_flags => $status_flags
}, },
Shr => { shr => {
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
reg_req => { out => [ "gp", "flags" ] }, reg_req => { out => [ "gp", "flags" ] },
outs => [ "res", "flags" ], outs => [ "res", "flags" ],
...@@ -267,7 +267,7 @@ Shr => { ...@@ -267,7 +267,7 @@ Shr => {
modified_flags => $status_flags modified_flags => $status_flags
}, },
Sar => { sar => {
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
reg_req => { out => [ "gp", "flags" ] }, reg_req => { out => [ "gp", "flags" ] },
outs => [ "res", "flags" ], outs => [ "res", "flags" ],
...@@ -278,7 +278,7 @@ Sar => { ...@@ -278,7 +278,7 @@ Sar => {
modified_flags => $status_flags modified_flags => $status_flags
}, },
Sub => { sub => {
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "flags", "none" ] }, reg_req => { out => [ "gp", "flags", "none" ] },
...@@ -290,7 +290,7 @@ Sub => { ...@@ -290,7 +290,7 @@ Sub => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
Sbb => { sbb => {
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "flags", "none" ] }, reg_req => { out => [ "gp", "flags", "none" ] },
outs => [ "res", "flags", "M" ], outs => [ "res", "flags", "M" ],
...@@ -301,7 +301,7 @@ Sbb => { ...@@ -301,7 +301,7 @@ Sbb => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
Neg => { neg => {
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
reg_req => { in => [ "gp" ], out => [ "in_r1", "flags" ] }, reg_req => { in => [ "gp" ], out => [ "in_r1", "flags" ] },
ins => [ "val" ], ins => [ "val" ],
...@@ -314,7 +314,7 @@ Neg => { ...@@ -314,7 +314,7 @@ Neg => {
modified_flags => $status_flags modified_flags => $status_flags
}, },
Not => { not => {
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
attr => "amd64_insn_mode_t insn_mode", attr => "amd64_insn_mode_t insn_mode",
init_attr => "attr->insn_mode = insn_mode;", init_attr => "attr->insn_mode = insn_mode;",
...@@ -328,7 +328,7 @@ Not => { ...@@ -328,7 +328,7 @@ Not => {
modified_flags => $status_flags modified_flags => $status_flags
}, },
Xor => { xor => {
irn_flags => [ "rematerializable", "commutative" ], irn_flags => [ "rematerializable", "commutative" ],
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "flags", "none" ] }, reg_req => { out => [ "gp", "flags", "none" ] },
...@@ -340,7 +340,7 @@ Xor => { ...@@ -340,7 +340,7 @@ Xor => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
Xor0 => { xor_0 => {
op_flags => [ "constlike" ], op_flags => [ "constlike" ],
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
reg_req => { out => [ "gp", "flags" ] }, reg_req => { out => [ "gp", "flags" ] },
...@@ -350,7 +350,7 @@ Xor0 => { ...@@ -350,7 +350,7 @@ Xor0 => {
modified_flags => $status_flags, modified_flags => $status_flags,
}, },
MovImm => { mov_imm => {
op_flags => [ "constlike" ], op_flags => [ "constlike" ],
irn_flags => [ "rematerializable" ], irn_flags => [ "rematerializable" ],
reg_req => { out => [ "gp" ] }, reg_req => { out => [ "gp" ] },
...@@ -361,7 +361,7 @@ MovImm => { ...@@ -361,7 +361,7 @@ MovImm => {
mode => $mode_gp, mode => $mode_gp,
}, },
Movs => { movs => {
state => "exc_pinned", state => "exc_pinned",
reg_req => { out => [ "gp", "none", "none" ] }, reg_req => { out => [ "gp", "none", "none" ] },
outs => [ "res", "unused", "M" ], outs => [ "res", "unused", "M" ],
...@@ -371,7 +371,7 @@ Movs => { ...@@ -371,7 +371,7 @@ Movs => {
emit => "movs%Mq %AM, %^D0", emit => "movs%Mq %AM, %^D0",
},