Commit 2e291eab authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Remove the unused parameter const arch_env_t *env from arch_set_irn_register().

[r22699]
parent 64403cb6
......@@ -39,7 +39,6 @@
#include "gen_arm_regalloc_if.h"
#include "gen_arm_new_nodes.h"
static const arch_env_t *arch_env;
static arm_code_gen_t *cg;
/** Execute ARM ROL. */
......@@ -159,13 +158,13 @@ static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
ir_node *ptr;
ptr = new_rd_arm_Add_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
arch_set_irn_register(arch_env, ptr, &arm_gp_regs[REG_R12]);
arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
sched_add_before(node, ptr);
for (cnt = 1; cnt < v->ops; ++cnt) {
long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
ir_node *next = new_rd_arm_Add_i(dbg, irg, block, ptr, mode_Iu, value);
arch_set_irn_register(arch_env, next, &arm_gp_regs[REG_R12]);
arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
sched_add_before(node, next);
ptr = next;
}
......@@ -184,13 +183,13 @@ static ir_node *gen_ptr_sub(ir_node *node, ir_node *frame, arm_vals *v)
ir_node *ptr;
ptr = new_rd_arm_Sub_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
arch_set_irn_register(arch_env, ptr, &arm_gp_regs[REG_R12]);
arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
sched_add_before(node, ptr);
for (cnt = 1; cnt < v->ops; ++cnt) {
long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
ir_node *next = new_rd_arm_Sub_i(dbg, irg, block, ptr, mode_Iu, value);
arch_set_irn_register(arch_env, next, &arm_gp_regs[REG_R12]);
arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
sched_add_before(node, next);
ptr = next;
}
......@@ -288,7 +287,7 @@ static void peephole_be_Reload(ir_node *node) {
load = new_rd_arm_fpaLdf(dbg, irg, block, ptr, mem, mode);
sched_add_before(node, load);
proj = new_rd_Proj(dbg, irg, block, load, mode, pn_arm_fpaLdf_res);
arch_set_irn_register(arch_env, proj, reg);
arch_set_irn_register(proj, reg);
} else {
panic("peephole_be_Spill: spill not supported for this mode");
}
......@@ -297,7 +296,7 @@ static void peephole_be_Reload(ir_node *node) {
load = new_rd_arm_Load(dbg, irg, block, ptr, mem);
sched_add_before(node, load);
proj = new_rd_Proj(dbg, irg, block, load, mode_Iu, pn_arm_Load_res);
arch_set_irn_register(arch_env, proj, reg);
arch_set_irn_register(proj, reg);
} else {
panic("peephole_be_Spill: spill not supported for this mode");
}
......@@ -316,8 +315,7 @@ static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
/* Perform peephole-optimizations. */
void arm_peephole_optimization(arm_code_gen_t *new_cg)
{
cg = new_cg;
arch_env = cg->arch_env;
cg = new_cg;
/* register peephole optimizations */
clear_irp_opcodes_generic_func();
......
......@@ -1400,7 +1400,7 @@ static ir_node *gen_Proj_be_AddSP(ir_node *node) {
if (proj == pn_be_AddSP_sp) {
ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
pn_arm_SubSPandCopy_stack);
arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
return res;
} else if(proj == pn_be_AddSP_res) {
return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
......@@ -1425,7 +1425,7 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) {
if (proj == pn_be_SubSP_sp) {
ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
pn_arm_AddSP_stack);
arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
return res;
} else if (proj == pn_be_SubSP_M) {
return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M);
......@@ -1523,7 +1523,7 @@ static INLINE ir_node *create_const(ir_node **place,
block = get_irg_start_block(env_cg->irg);
res = func(NULL, env_cg->irg, block);
arch_set_irn_register(env_cg->arch_env, res, reg);
arch_set_irn_register(res, reg);
*place = res;
add_irn_dep(get_irg_end(env_cg->irg), res);
......
......@@ -937,24 +937,24 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
block = get_irg_start_block(irg);
ip = be_new_Copy(gp, irg, block, sp);
arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
arch_set_irn_register(ip, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
arch_set_irn_register(env->arch_env, sp, env->arch_env->sp);
arch_set_irn_register(sp, env->arch_env->sp);
*mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
be_node_set_reg_class(keep, 1, gp);
arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
arch_set_irn_register(keep, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
arch_set_irn_register(fp, env->arch_env->bp);
fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
arch_set_irn_register(fp, env->arch_env->bp);
be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
......@@ -982,11 +982,11 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
arch_set_irn_register(curr_lr, &arm_gp_regs[REG_LR]);
be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
} else {
......@@ -995,7 +995,7 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
// FIXME
//set_arm_req_out_all(sub12_node, sub12_req);
arch_set_irn_register(env->arch_env, sub12_node, env->arch_env->sp);
arch_set_irn_register(sub12_node, env->arch_env->sp);
load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
// FIXME
//set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
......@@ -1005,9 +1005,9 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
*mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
arch_set_irn_register(env->arch_env, curr_bp, env->arch_env->bp);
arch_set_irn_register(env->arch_env, curr_sp, env->arch_env->sp);
arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
arch_set_irn_register(curr_bp, env->arch_env->bp);
arch_set_irn_register(curr_sp, env->arch_env->sp);
arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
}
be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
......
......@@ -669,7 +669,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
curr_sp = new_r_Proj(irg, bl, low_call, get_irn_mode(curr_sp),
pn_be_Call_sp);
be_set_constr_single_reg(low_call, BE_OUT_POS(pn_be_Call_sp), sp);
arch_set_irn_register(arch_env, curr_sp, sp);
arch_set_irn_register(curr_sp, sp);
be_node_set_flags(low_call, BE_OUT_POS(pn_be_Call_sp),
arch_irn_flags_ignore | arch_irn_flags_modify_sp);
......@@ -728,7 +728,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
assert(arg->in_reg);
be_set_constr_single_reg(low_call, BE_OUT_POS(pn), arg->reg);
arch_set_irn_register(arch_env, proj, arg->reg);
arch_set_irn_register(proj, arg->reg);
}
obstack_free(obst, in);
exchange(irn, low_call);
......@@ -759,7 +759,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
/* memorize the register in the link field. we need afterwards to set the register class of the keep correctly. */
be_set_constr_single_reg(low_call, BE_OUT_POS(curr_res_proj), reg);
arch_set_irn_register(arch_env, proj, reg);
arch_set_irn_register(proj, reg);
/* a call can produce ignore registers, in this case set the flag and register for the Proj */
if (arch_register_type_is(reg, ignore)) {
......@@ -1364,7 +1364,7 @@ static ir_node *create_barrier(be_abi_irg_t *env, ir_node *bl, ir_node **mem, pm
be_set_constr_single_reg(irn, n, reg);
be_set_constr_single_reg(irn, pos, reg);
be_node_set_reg_class(irn, pos, reg->reg_class);
arch_set_irn_register(env->birg->main_env->arch_env, proj, reg);
arch_set_irn_register(proj, reg);
/* if the proj projects a ignore register or a node which is set to ignore, propagate this property. */
if (arch_register_type_is(reg, ignore) || arch_irn_is(env->birg->main_env->arch_env, in[n], ignore))
......@@ -1840,7 +1840,7 @@ static void modify_irg(be_abi_irg_t *env)
proj = new_r_Proj(irg, reg_params_bl, env->reg_params, mode, nr);
pmap_insert(env->regs, (void *) reg, proj);
be_set_constr_single_reg(env->reg_params, pos, reg);
arch_set_irn_register(env->birg->main_env->arch_env, proj, reg);
arch_set_irn_register(proj, reg);
/*
* If the register is an ignore register,
......@@ -1878,7 +1878,7 @@ static void modify_irg(be_abi_irg_t *env)
create_barrier(env, start_bl, &mem, env->regs, 0);
env->init_sp = be_abi_reg_map_get(env->regs, sp);
arch_set_irn_register(env->birg->main_env->arch_env, env->init_sp, sp);
arch_set_irn_register(env->init_sp, sp);
frame_pointer = be_abi_reg_map_get(env->regs, fp_reg);
set_irg_frame(irg, frame_pointer);
......@@ -2368,7 +2368,7 @@ void be_abi_fix_stack_nodes(be_abi_irg_t *env)
ir_node *phi = phis[i];
be_set_phi_reg_req(walker_env.arch_env, phi, &env->sp_req);
be_set_phi_flags(walker_env.arch_env, phi, arch_irn_flags_ignore | arch_irn_flags_modify_sp);
arch_set_irn_register(walker_env.arch_env, phi, env->arch_env->sp);
arch_set_irn_register(phi, env->arch_env->sp);
}
be_ssa_construction_destroy(&senv);
......
......@@ -226,11 +226,9 @@ const arch_register_t *arch_get_irn_register(const ir_node *irn)
return ops->get_irn_reg(irn);
}
extern void arch_set_irn_register(const arch_env_t *env,
ir_node *irn, const arch_register_t *reg)
void arch_set_irn_register(ir_node *irn, const arch_register_t *reg)
{
const arch_irn_ops_t *ops = get_irn_ops(irn);
(void)env; // TODO remove parameter
ops->set_irn_reg(irn, reg);
}
......
......@@ -210,12 +210,10 @@ const arch_register_t *arch_get_irn_register(const ir_node *irn);
/**
* Set the register for a certain output operand.
* @param env The architecture environment.
* @param irn The node.
* @param reg The register.
*/
extern void arch_set_irn_register(const arch_env_t *env, ir_node *irn,
const arch_register_t *reg);
void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
/**
* Classify a node.
......
......@@ -428,7 +428,6 @@ static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env,
be_insn_t **the_insn)
{
be_chordal_env_t *env = alloc_env->chordal_env;
const arch_env_t *aenv = env->birg->main_env->arch_env;
be_insn_t *insn = *the_insn;
ir_node *perm = NULL;
bitset_t *out_constr = bitset_alloca(env->cls->n_regs);
......@@ -462,7 +461,7 @@ static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env,
be_stat_ev("constr_perm", get_irn_arity(perm));
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
arch_set_irn_register(aenv, proj, NULL);
arch_set_irn_register(proj, NULL);
}
/*
......@@ -495,7 +494,6 @@ static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env,
static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
ir_node *irn, int *silent)
{
const arch_env_t *aenv;
int n_regs;
bitset_t *bs;
ir_node **alloc_nodes;
......@@ -541,7 +539,6 @@ static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
if(!insn->has_constraints)
goto end;
aenv = env->birg->main_env->arch_env;
n_regs = env->cls->n_regs;
bs = bitset_alloca(n_regs);
alloc_nodes = alloca(n_regs * sizeof(alloc_nodes[0]));
......@@ -671,14 +668,14 @@ static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
irn = alloc_nodes[i];
if (irn != NULL) {
arch_set_irn_register(aenv, irn, reg);
arch_set_irn_register(irn, reg);
(void) pset_hinsert_ptr(alloc_env->pre_colored, irn);
DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", irn, reg->name));
}
irn = pmap_get(partners, alloc_nodes[i]);
if (irn != NULL) {
arch_set_irn_register(aenv, irn, reg);
arch_set_irn_register(irn, reg);
(void) pset_hinsert_ptr(alloc_env->pre_colored, irn);
DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", irn, reg->name));
}
......@@ -708,7 +705,7 @@ static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
col = get_next_free_reg(alloc_env, bs);
reg = arch_register_for_index(env->cls, col);
bitset_set(bs, reg->index);
arch_set_irn_register(aenv, proj, reg);
arch_set_irn_register(proj, reg);
pset_insert_ptr(alloc_env->pre_colored, proj);
DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", proj, reg->name));
}
......@@ -954,7 +951,7 @@ static void assign(ir_node *block, void *env_ptr)
}
bitset_set(colors, col);
arch_set_irn_register(arch_env, irn, reg);
arch_set_irn_register(irn, reg);
DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n", arch_register_get_name(reg), col, irn));
......
......@@ -1096,12 +1096,11 @@ static void process(co2_t *env)
static void writeback_colors(co2_t *env)
{
const arch_env_t *aenv = env->co->aenv;
co2_irn_t *irn;
for(irn = env->touched; irn; irn = irn->touched_next) {
const arch_register_t *reg = arch_register_for_index(env->co->cls, irn->orig_col);
arch_set_irn_register(aenv, (ir_node *) irn->irn, reg);
arch_set_irn_register((ir_node*)irn->irn, reg);
}
}
......
......@@ -1463,7 +1463,7 @@ int co_solve_heuristic_mst(copy_opt_t *co) {
continue;
reg = arch_register_for_index(co->cls, mirn->col);
arch_set_irn_register(co->aenv, irn, reg);
arch_set_irn_register(irn, reg);
DB((dbg, LEVEL_1, "%+F set color from %d to %d\n", irn, mirn->init_col, mirn->col));
}
......
......@@ -60,7 +60,7 @@ struct _copy_opt_t {
#define ASSERT_GS_AVAIL(co) assert((co)->nodes && "Representation as graph not build")
#define get_irn_col(irn) arch_register_get_index(arch_get_irn_register(irn))
#define set_irn_col(co, irn, col) arch_set_irn_register((co)->aenv, irn, arch_register_for_index((co)->cls, col))
#define set_irn_col(co, irn, col) arch_set_irn_register(irn, arch_register_for_index((co)->cls, col))
#define is_curr_reg_class(co, irn) (arch_get_irn_reg_class(irn, -1) == (co)->cls)
#define list_entry_units(lh) list_entry(lh, unit_t, units)
......
......@@ -455,7 +455,7 @@ static void save_load(ir_node *irn, void *env) {
pmap_insert(saver->saved_colors, irn, (void *) reg);
} else { /*load */
arch_register_t *reg = pmap_get(saver->saved_colors, irn);
arch_set_irn_register(saver->arch_env, irn, reg);
arch_set_irn_register(irn, reg);
}
}
}
......
......@@ -261,7 +261,7 @@ static void fix_flags_walker(ir_node *block, void *env)
}
flags_needed = new_flags_needed;
arch_set_irn_register(arch_env, flags_needed, flags_reg);
arch_set_irn_register(flags_needed, flags_reg);
if(is_Proj(flags_needed)) {
pn = get_Proj_proj(flags_needed);
flags_needed = get_Proj_pred(flags_needed);
......
......@@ -105,7 +105,7 @@ static void restore_irn_color(ir_node *irn, void *c)
coloring_t *coloring = c;
const arch_register_t *reg = phase_get_irn_data(&coloring->ph, irn);
if(reg)
arch_set_irn_register(coloring->arch_env, irn, reg);
arch_set_irn_register(irn, reg);
}
void coloring_save(coloring_t *c)
......
......@@ -85,7 +85,6 @@ ir_node *insert_Perm_after(be_irg_t *birg,
const arch_register_class_t *cls,
ir_node *pos)
{
const arch_env_t *arch_env = birg->main_env->arch_env;
be_lv_t *lv = birg->lv;
ir_node *bl = is_Block(pos) ? pos : get_nodes_block(pos);
ir_graph *irg = get_irn_irg(bl);
......@@ -98,7 +97,7 @@ ir_node *insert_Perm_after(be_irg_t *birg,
DBG((dbg, LEVEL_1, "Insert Perm after: %+F\n", pos));
ir_nodeset_init(&live);
be_liveness_nodes_live_at(lv, arch_env, cls, pos, &live);
be_liveness_nodes_live_at(lv, birg->main_env->arch_env, cls, pos, &live);
n = ir_nodeset_size(&live);
if(n == 0) {
......@@ -129,7 +128,7 @@ ir_node *insert_Perm_after(be_irg_t *birg,
ir_mode *mode = get_irn_mode(perm_op);
ir_node *proj = new_r_Proj(irg, bl, perm, mode, i);
arch_set_irn_register(arch_env, proj, reg);
arch_set_irn_register(proj, reg);
curr = proj;
......
......@@ -283,7 +283,6 @@ static perm_cycle_t *get_perm_cycle(perm_cycle_t *cycle, reg_pair_t *pairs, int
static void lower_perm_node(ir_node *irn, void *walk_env) {
ir_graph *irg = get_irn_irg(irn);
const arch_register_class_t *reg_class;
const arch_env_t *arch_env;
lower_env_t *env = walk_env;
int real_size = 0;
int keep_perm = 0;
......@@ -295,7 +294,6 @@ static void lower_perm_node(ir_node *irn, void *walk_env) {
ir_node *cpyxchg = NULL;
DEBUG_ONLY(firm_dbg_module_t *mod;)
arch_env = env->arch_env;
do_copy = env->do_copy;
DEBUG_ONLY(mod = env->dbg_module;)
block = get_nodes_block(irn);
......@@ -465,8 +463,8 @@ static void lower_perm_node(ir_node *irn, void *walk_env) {
set_Proj_pred(res1, cpyxchg);
set_Proj_proj(res1, 1);
arch_set_irn_register(arch_env, res2, cycle->elems[i + 1]);
arch_set_irn_register(arch_env, res1, cycle->elems[i]);
arch_set_irn_register(res2, cycle->elems[i + 1]);
arch_set_irn_register(res1, cycle->elems[i]);
/* insert the copy/exchange node in schedule after the magic schedule node (see above) */
sched_add_after(sched_point, cpyxchg);
......@@ -481,7 +479,7 @@ static void lower_perm_node(ir_node *irn, void *walk_env) {
irn, arg1, cycle->elems[i]->name, res2, cycle->elems[i + 1]->name));
cpyxchg = be_new_Copy(reg_class, irg, block, arg1);
arch_set_irn_register(arch_env, cpyxchg, cycle->elems[i + 1]);
arch_set_irn_register(cpyxchg, cycle->elems[i + 1]);
n_ops++;
/* exchange copy node and proj */
......@@ -974,7 +972,7 @@ found_front:
sched_add_after(perm, node);
/* give it the proj's register */
arch_set_irn_register(aenv, node, arch_get_irn_register(proj));
arch_set_irn_register(node, arch_get_irn_register(proj));
/* reroute all users of the proj to the moved node. */
edges_reroute(proj, node, irg);
......
......@@ -773,12 +773,13 @@ ir_node *be_RegParams_append_out_reg(ir_node *regparams,
ir_mode *mode = arch_register_class_mode(cls);
int n = ARR_LEN(attr->reg_data);
ir_node *proj;
(void)arch_env; // TODO remove parameter
assert(be_is_RegParams(regparams));
proj = new_r_Proj(irg, block, regparams, mode, n);
add_register_req(regparams);
be_set_constr_single_reg(regparams, BE_OUT_POS(n), reg);
arch_set_irn_register(arch_env, proj, reg);
arch_set_irn_register(proj, reg);
/* TODO decide, whether we need to set ignore/modify sp flags here? */
......
......@@ -52,9 +52,8 @@
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
#define get_chordal_arch(ce) ((ce)->birg->main_env->arch_env)
#define get_reg(irn) arch_get_irn_register(irn)
#define set_reg(irn, reg) arch_set_irn_register(get_chordal_arch(chordal_env), irn, reg)
#define set_reg(irn, reg) arch_set_irn_register(irn, reg)
#define is_Perm(irn) (arch_irn_class_is(arch_env, irn, perm))
#define get_reg_cls(irn) (arch_get_irn_reg_class(arch_env, irn, -1))
......
......@@ -601,7 +601,7 @@ void be_assure_state(be_irg_t *birg, const arch_register_t *reg, void *func_env,
for(i = 0; i < len; ++i) {
ir_node *phi = phis[i];
be_set_phi_flags(env.arch_env, phi, arch_irn_flags_ignore);
arch_set_irn_register(env.arch_env, phi, env.reg);
arch_set_irn_register(phi, env.reg);
}
be_ssa_construction_destroy(&senv);
......
......@@ -132,7 +132,7 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
block = get_irg_start_block(cg->irg);
res = func(NULL, cg->irg, block);
arch_set_irn_register(cg->arch_env, res, reg);
arch_set_irn_register(res, reg);
*place = res;
add_irn_dep(get_irg_end(cg->irg), res);
......@@ -447,7 +447,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
*mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
/* the push must have SP out register */
arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
arch_set_irn_register(curr_sp, arch_env->sp);
set_ia32_flags(push, arch_irn_flags_ignore);
/* this modifies the stack bias, because we pushed 32bit */
......@@ -456,13 +456,13 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
/* move esp to ebp */
curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
arch_set_irn_register(curr_bp, arch_env->bp);
be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
/* beware: the copy must be done before any other sp use */
curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
arch_set_irn_register(curr_sp, arch_env->sp);
be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
......@@ -515,7 +515,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
/* copy ebp to esp */
curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
arch_set_irn_register(curr_sp, arch_env->sp);
be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
/* pop ebp */
......@@ -526,8 +526,8 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
*mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
}
arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
arch_set_irn_register(curr_sp, arch_env->sp);
arch_set_irn_register(curr_bp, arch_env->bp);
}
be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
......@@ -1195,7 +1195,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
/* copy the register from the old node to the new Load */
reg = arch_get_irn_register(node);
arch_set_irn_register(cg->arch_env, new_op, reg);
arch_set_irn_register(new_op, reg);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
......@@ -1304,7 +1304,8 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi
return pop;
}
static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
{
ir_graph *irg = get_irn_irg(node);
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
......@@ -1313,7 +1314,7 @@ static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred,
ir_node *sp;
sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
arch_set_irn_register(cg->arch_env, sp, spreg);
arch_set_irn_register(sp, spreg);
return sp;
}
......@@ -1353,12 +1354,12 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
push = create_push(cg, node, node, sp, mem, inent);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
sp = create_spproj(node, push, pn_ia32_Push_stack);
if(entsize == 8) {
/* add another push after the first one */
push = create_push(cg, node, node, sp, mem, inent);
add_ia32_am_offs_int(push, 4);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
sp = create_spproj(node, push, pn_ia32_Push_stack);
}
set_irn_n(node, i, new_Bad());
......@@ -1379,13 +1380,13 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
sp = create_spproj(node, pop, pn_ia32_Pop_stack);
if(entsize == 8) {
add_ia32_am_offs_int(pop, 4);
/* add another pop after the first one */
pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
sp = create_spproj(node, pop, pn_ia32_Pop_stack);
}
pops[i] = pop;
......
......@@ -174,7 +174,7 @@ ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
ir_node *start_block = get_irg_start_block(irg);
ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
symconst, symconst_sign, val);
arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);