Commit 2fb66e6e authored by Christoph Mallon's avatar Christoph Mallon
Browse files

be: Pass the input requirements directly to the constructors of nodes, which...

be: Pass the input requirements directly to the constructors of nodes, which have a variable number of arguments.
parent d0d34f47
......@@ -263,9 +263,7 @@ static ir_node *gen_Return(ir_node *node)
dbg_info *const dbgi = get_irn_dbg_info(node);
ir_node *const block = be_transform_nodes_block(node);
ir_node *const ret = new_bd_TEMPLATE_Return(dbgi, block, n_ins, in);
arch_set_irn_register_reqs_in(ret, reqs);
ir_node *const ret = new_bd_TEMPLATE_Return(dbgi, block, n_ins, in, reqs);
return ret;
}
......
......@@ -102,14 +102,12 @@ static void transform_sub_to_neg_add(ir_node *node,
init_lconst_addr(&xor_attr.base.addr, sign_bit_const);
ir_node *xor_in[] = { in2 };
ir_node *xor = new_bd_amd64_xorp(dbgi, block, ARRAY_SIZE(xor_in),
xor_in, &xor_attr);
arch_set_irn_register_reqs_in(xor, amd64_xmm_reqs);
ir_node *const xor = new_bd_amd64_xorp(dbgi, block, ARRAY_SIZE(xor_in), xor_in, amd64_xmm_reqs, &xor_attr);
sched_add_before(node, xor);
ir_node *const neg = be_new_Proj_reg(xor, pn_amd64_xorp_res, in2_reg);
ir_node *in[] = { neg, in1 };
add = new_bd_amd64_adds(dbgi, block, ARRAY_SIZE(in), in, attr);
add = new_bd_amd64_adds(dbgi, block, ARRAY_SIZE(in), in, amd64_xmm_xmm_reqs, attr);
pos = pn_amd64_adds_res;
} else {
assert(is_amd64_sub(node));
......@@ -118,10 +116,9 @@ static void transform_sub_to_neg_add(ir_node *node,
ir_node *const neg_res = be_new_Proj_reg(neg, pn_amd64_neg_res, out_reg);
ir_node *in[] = { neg_res, in1 };
add = new_bd_amd64_add(dbgi, block, ARRAY_SIZE(in), in, attr);
add = new_bd_amd64_add(dbgi, block, ARRAY_SIZE(in), in, amd64_reg_reg_reqs, attr);
pos = pn_amd64_add_res;
}
arch_set_irn_register_reqs_in(add, arch_get_irn_register_reqs_in(node));
arch_set_irn_register_out(add, pos, out_reg);
/* exchange the add and the sub */
......@@ -151,10 +148,7 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
new_addr.mem_input = load_arity;
load_in[load_arity++] = get_irn_n(node, attr->addr.mem_input);
ir_node *load = new_bd_amd64_mov_gp(dbgi, block, load_arity, load_in,
attr->insn_mode, AMD64_OP_ADDR,
new_addr);
arch_set_irn_register_reqs_in(load, gp_am_reqs[load_arity - 1]);
ir_node *const load = new_bd_amd64_mov_gp(dbgi, block, load_arity, load_in, gp_am_reqs[load_arity - 1], attr->insn_mode, AMD64_OP_ADDR, new_addr);
ir_node *const load_res = be_new_Proj_reg(load, pn_amd64_mov_gp_res, out_reg);
/* change operation */
......
This diff is collapsed.
......@@ -21,6 +21,8 @@ extern arch_register_req_t const **const gp_am_reqs[];
extern arch_register_req_t const *reg_reqs[];
extern arch_register_req_t const *rsp_reg_mem_reqs[];
extern arch_register_req_t const *xmm_reg_mem_reqs[];
extern arch_register_req_t const *amd64_reg_reg_reqs[];
extern arch_register_req_t const *amd64_xmm_xmm_reqs[];
void amd64_init_transform(void);
......
......@@ -308,9 +308,7 @@ static ir_node *make_mov_imm32_to_offset_mem(dbg_info *dbgi, ir_node *block, ir_
},
},
};
ir_node *result = new_bd_amd64_mov_store(dbgi, block, ARRAY_SIZE(mov_in), mov_in, &mov_attr);
arch_set_irn_register_reqs_in(result, gp_am_reqs[1]);
return result;
return new_bd_amd64_mov_store(dbgi, block, ARRAY_SIZE(mov_in), mov_in, gp_am_reqs[1], &mov_attr);
}
/*
......@@ -342,9 +340,7 @@ static ir_node *make_mov_val64_to_offset_mem(dbg_info *dbgi, ir_node *block, ir_
.reg_input = 0,
},
};
ir_node *result = new_bd_amd64_mov_store(dbgi, block, ARRAY_SIZE(mov_in), mov_in, &mov_attr);
arch_set_irn_register_reqs_in(result, gp_am_reqs[2]);
return result;
return new_bd_amd64_mov_store(dbgi, block, ARRAY_SIZE(mov_in), mov_in, gp_am_reqs[2], &mov_attr);
}
/*
......@@ -376,9 +372,7 @@ static ir_node *make_mov_xmmval64_to_offset_mem(dbg_info *dbgi, ir_node *block,
.reg_input = 0,
},
};
ir_node *result = new_bd_amd64_movs_store_xmm(dbgi, block, ARRAY_SIZE(mov_in), mov_in, &mov_attr);
arch_set_irn_register_reqs_in(result, xmm_reg_mem_reqs);
return result;
return new_bd_amd64_movs_store_xmm(dbgi, block, ARRAY_SIZE(mov_in), mov_in, xmm_reg_mem_reqs, &mov_attr);
}
/*
......@@ -397,9 +391,7 @@ static ir_node *make_lea_with_offset_entity(dbg_info *dbgi, ir_node *block,
.kind = X86_IMM_VALUE,
},
};
ir_node *result = new_bd_amd64_lea(dbgi, block, ARRAY_SIZE(lea_in), lea_in, INSN_MODE_64, lea_addr);
arch_set_irn_register_reqs_in(result, reg_reqs);
return result;
return new_bd_amd64_lea(dbgi, block, ARRAY_SIZE(lea_in), lea_in, reg_reqs, INSN_MODE_64, lea_addr);
}
ir_node *amd64_initialize_va_list(dbg_info *dbgi, ir_node *block, x86_cconv_t *cconv,
......
......@@ -131,9 +131,7 @@ static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp,
addr.index_input = NO_INPUT;
addr.immediate.entity = ent;
ir_node *in[] = { sp, frame, mem };
ir_node *push = new_bd_amd64_push_am(dbgi, block, ARRAY_SIZE(in), in,
insn_mode, addr);
arch_set_irn_register_reqs_in(push, rsp_reg_mem_reqs);
ir_node *const push = new_bd_amd64_push_am(dbgi, block, ARRAY_SIZE(in), in, rsp_reg_mem_reqs, insn_mode, addr);
sched_add_before(schedpoint, push);
return push;
}
......@@ -153,9 +151,7 @@ static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp,
addr.immediate.entity = ent;
ir_node *in[] = { sp, frame, get_irg_no_mem(irg) };
ir_node *pop = new_bd_amd64_pop_am(dbgi, block, ARRAY_SIZE(in), in,
insn_mode, addr);
arch_set_irn_register_reqs_in(pop, rsp_reg_mem_reqs);
ir_node *const pop = new_bd_amd64_pop_am(dbgi, block, ARRAY_SIZE(in), in, rsp_reg_mem_reqs, insn_mode, addr);
sched_add_before(schedpoint, pop);
return pop;
......
......@@ -1787,8 +1787,7 @@ static ir_node *gen_Return(ir_node *node)
}
assert(p == n_ins);
ir_node *ret = new_bd_arm_Return(dbgi, new_block, n_ins, in);
arch_set_irn_register_reqs_in(ret, reqs);
ir_node *const ret = new_bd_arm_Return(dbgi, new_block, n_ins, in, reqs);
return ret;
}
......@@ -1913,18 +1912,15 @@ static ir_node *gen_Call(ir_node *node)
if (entity != NULL) {
/* TODO: use a generic address matcher here
* so we can also handle entity+offset, etc. */
res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, in_req, out_arity, entity, 0);
} else {
/* TODO:
* - use a proper shifter_operand matcher
* - we could also use LinkLdrPC
*/
res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
shiftop_input, ARM_SHF_REG, 0, 0);
res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, in_req, out_arity, shiftop_input, ARM_SHF_REG, 0, 0);
}
arch_set_irn_register_reqs_in(res, in_req);
/* create output register reqs */
arch_set_irn_register_req_out(res, pn_arm_Bl_M, arch_memory_req);
arch_copy_irn_out_info(res, pn_arm_Bl_stack, incsp);
......
......@@ -264,11 +264,12 @@ ir_node *be_make_asm(ir_node const *const node, ir_node **in, arch_register_req_
ARR_APP1(arch_register_req_t const*, in_reqs, arch_memory_req);
ARR_APP1(arch_register_req_t const*, out_reqs, arch_memory_req);
dbg_info *const dbgi = get_irn_dbg_info(node);
unsigned const n_ins = ARR_LEN(in);
unsigned const n_outs = ARR_LEN(out_reqs);
ident *const text = get_ASM_text(node);
ir_node *const new_node = be_new_Asm(dbgi, block, n_ins, in, n_outs, text, operands);
dbg_info *const dbgi = get_irn_dbg_info(node);
unsigned const n_ins = ARR_LEN(in);
unsigned const n_outs = ARR_LEN(out_reqs);
ident *const text = get_ASM_text(node);
arch_register_req_t const **const dup_in_reqs = DUP_ARR_D(arch_register_req_t const*, obst, in_reqs);
ir_node *const new_node = be_new_Asm(dbgi, block, n_ins, in, dup_in_reqs, n_outs, text, operands);
for (unsigned i = 0, n = isa_if->n_register_classes; i < n; ++i) {
if (add_pressure[i] == 0)
continue;
......@@ -280,8 +281,6 @@ ir_node *be_make_asm(ir_node const *const node, ir_node **in, arch_register_req_
for (size_t o = 0; o < n_outs; ++o) {
info->out_infos[o].req = out_reqs[o];
}
arch_register_req_t const **const dup_in_reqs = DUP_ARR_D(arch_register_req_t const*, obst, in_reqs);
arch_set_irn_register_reqs_in(new_node, dup_in_reqs);
DEL_ARR_F(in);
DEL_ARR_F(in_reqs);
......
......@@ -466,11 +466,11 @@ void be_set_phi_reg_req(ir_node *node, const arch_register_req_t *req)
}
}
ir_node *be_new_Asm(dbg_info *const dbgi, ir_node *const block, int const n_ins, ir_node **const ins, int const n_outs, ident *const text, void *const operands)
ir_node *be_new_Asm(dbg_info *const dbgi, ir_node *const block, int const n_ins, ir_node **const ins, arch_register_req_t const **const in_reqs, int const n_outs, ident *const text, void *const operands)
{
ir_graph *const irg = get_irn_irg(block);
ir_node *const asmn = new_ir_node(dbgi, irg, block, op_be_Asm, mode_T, n_ins, ins);
be_info_init_irn(asmn, arch_irn_flags_none, NULL, n_outs);
be_info_init_irn(asmn, arch_irn_flags_none, in_reqs, n_outs);
be_asm_attr_t *const attr = (be_asm_attr_t*)get_irn_generic_attr(asmn);
attr->text = text;
......
......@@ -186,7 +186,7 @@ ir_node *be_new_Phi0(ir_node *block, ir_mode *mode, arch_register_req_t const *r
*/
ir_node *be_complete_Phi(ir_node *phi, unsigned n_ins, ir_node **ins);
ir_node *be_new_Asm(dbg_info *dbgi, ir_node *block, int n_ins, ir_node **ins, int n_outs, ident *text, void *operands);
ir_node *be_new_Asm(dbg_info *dbgi, ir_node *block, int n_ins, ir_node **ins, arch_register_req_t const **in_reqs, int n_outs, ident *text, void *operands);
/**
* Create a new Relocation node. The node returns the reference to an entity
......
......@@ -4329,11 +4329,8 @@ static ir_node *gen_Return(ir_node *node)
}
assert(p == n_ins);
ir_node *returnn = new_bd_ia32_Return(dbgi, new_block, n_ins, in,
current_cconv->sp_delta);
arch_set_irn_register_reqs_in(returnn, reqs);
return returnn;
ir_node *const ret = new_bd_ia32_Return(dbgi, new_block, n_ins, in, reqs, current_cconv->sp_delta);
return ret;
}
static ir_node *gen_Alloc(ir_node *node)
......@@ -5063,8 +5060,7 @@ static ir_node *gen_Call(ir_node *node)
unsigned const n_out = o + n_reg_results + n_caller_saves;
/* Create node. */
ir_node *const call = new_bd_ia32_Call(dbgi, block, in_arity, in, n_out, cconv->sp_delta, type);
arch_set_irn_register_reqs_in(call, in_req);
ir_node *const call = new_bd_ia32_Call(dbgi, block, in_arity, in, in_req, n_out, cconv->sp_delta, type);
arch_set_additional_pressure(call, &ia32_reg_classes[CLASS_ia32_gp],
add_pressure);
......
......@@ -166,7 +166,7 @@ sub create_constructor
# create constructor head
my $complete_args = "";
if ($arity == $ARITY_VARIABLE) {
$complete_args = ", int arity, ir_node *const in[]";
$complete_args = ", int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs";
} else {
for (my $i = 0; $i < $arity; $i++) {
my $opname = $ins ? $$ins[$i] : "op$i";
......@@ -216,7 +216,7 @@ EOF
$temp .= "\t\t&$reqstruct,\n";
}
$temp .= "\t};\n";
} else {
} elsif ($arity == 0) {
$temp .= "\tarch_register_req_t const **const in_reqs = NULL;\n";
}
......@@ -288,7 +288,7 @@ EOF
$temp .= "\tint const n_res = $out_arity;\n"
}
my $attr_init_code = "(void)irn_flags;(void)in_reqs;(void)n_res;";
my $attr_init_code = "(void)irn_flags, (void)n_res;";
if ((my $attr_type = $on->{attr_type}) ne "") {
$attr_init_code = $init_attr{$attr_type};
if (!defined($attr_init_code)) {
......@@ -606,6 +606,7 @@ print $out_h <<EOF;
#ifndef FIRM_BE_${uarch}_GEN_${uarch}_NEW_NODES_H
#define FIRM_BE_${uarch}_GEN_${uarch}_NEW_NODES_H
#include "be_types.h"
#include "irnode_t.h"
$obst_enum_op
......
......@@ -1645,10 +1645,8 @@ static ir_node *gen_Return(ir_node *node)
}
assert(p == n_ins);
ir_node *bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
arch_set_irn_register_reqs_in(bereturn, reqs);
return bereturn;
ir_node *const ret = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in, reqs);
return ret;
}
static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
......@@ -1862,15 +1860,9 @@ static ir_node *gen_Call(ir_node *node)
unsigned const out_arity = o + cconv->n_reg_results + n_caller_saves;
/* create call node */
ir_node *res;
if (entity != NULL) {
res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
type, entity, 0, aggregate_return);
} else {
res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
type, aggregate_return);
}
arch_set_irn_register_reqs_in(res, in_req);
ir_node *const res = entity ?
new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, in_req, out_arity, type, entity, 0, aggregate_return) :
new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, in_req, out_arity, type, aggregate_return);
/* create output register reqs */
arch_set_irn_register_req_out(res, pn_sparc_Call_M, arch_memory_req);
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment