Commit 308688bf authored by Michael Beck's avatar Michael Beck
Browse files

added x87 opcodes for pop operations and load/store integer

parent 3205597c
......@@ -746,6 +746,21 @@ $additional_opcodes = 0;
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
},
# Conversions
"vfild" => {
"irn_flags" => "R",
"comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
},
"vfist" => {
"comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
},
# constants
"vfldz" => {
......@@ -814,7 +829,15 @@ $additional_opcodes = 0;
"comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { },
# "emit" => '. fadd %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */'
"emit" => '. fadd %X1,%X3 /* x87 fadd(%X1, %X2) -> %X3 */'
"emit" => '. fadd %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 */'
},
"faddp" => {
"rd_constructor" => "NONE",
"comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { },
# "emit" => '. faddp %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */'
"emit" => '. faddp %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 and pop */'
},
"fmul" => {
......@@ -822,14 +845,31 @@ $additional_opcodes = 0;
"comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"reg_req" => { },
# "emit" => '. fmul %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */'
"emit" => '. fmul %X1,%X3 /* x87 fmul(%X1, %X2) -> %X3 */'
"emit" => '. fmul %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 */'
},
"fmulp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"reg_req" => { },
# "emit" => '. fmulp %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */'
"emit" => '. fmulp %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 and pop */'
},
"fsub" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sub: Sub(a, b) = a - b",
"reg_req" => { },
"emit" => '. fsub %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */'
# "emit" => '. fsub %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */'
"emit" => '. fsub %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 */'
},
"fsubp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sub: Sub(a, b) = a - b",
"reg_req" => { },
# "emit" => '. fsubp %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */'
"emit" => '. fsubp %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 and pop */'
},
"fsubr" => {
......@@ -837,59 +877,87 @@ $additional_opcodes = 0;
"irn_flags" => "R",
"comment" => "x87 fp SubR: SubR(a, b) = b - a",
"reg_req" => { },
"emit" => '. fsubr %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
# "emit" => '. fsubr %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
"emit" => '. fsubr %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 */'
},
"fsubrp" => {
"rd_constructor" => "NONE",
"irn_flags" => "R",
"comment" => "x87 fp SubR: SubR(a, b) = b - a",
"reg_req" => { },
# "emit" => '. fsubrp %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
"emit" => '. fsubrp %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 and pop */'
},
"fdiv" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Div: Div(a, b) = a / b",
"reg_req" => { },
"emit" => '. fdiv %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
# "emit" => '. fdiv %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
"emit" => '. fdiv %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 */'
},
"fdivp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Div: Div(a, b) = a / b",
"reg_req" => { },
# "emit" => '. fdivp %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
"emit" => '. fdivp %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 and pop */'
},
"fdivr" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp DivR: DivR(a, b) = b / a",
"reg_req" => { },
"emit" => '. fdivr %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
# "emit" => '. fdivr %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
"emit" => '. fdivr %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 */'
},
"fdivrp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp DivR: DivR(a, b) = b / a",
"reg_req" => { },
# "emit" => '. fdivrp %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
"emit" => '. fdivrp %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 and pop */'
},
"fabs" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Abs: Abs(a) = |a|",
"reg_req" => { },
"emit" => '. fabs %D1, %S1 $ /* x87 fabs(%A1) -> %D1 */'
"emit" => '. fabs %X1 /* x87 fabs(%X1) -> %X3 */'
},
"fchs" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Chs: Chs(a) = -a",
"reg_req" => { },
"emit" => '. fchs %D1, %S1 $ /* x87 fchs(%A1) -> %D1 */'
"emit" => '. fchs %X1 /* x87 fchs(%X1) -> %X3 */'
},
"fsin" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sin: Sin(a) = sin(a)",
"reg_req" => { },
"emit" => '. fsin %D1, %S1 $ /* x87 sin(%A1) -> %D1 */'
"emit" => '. fsin %X1 /* x87 sin(%X1) -> %X3 */'
},
"fcos" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Cos: Cos(a) = cos(a)",
"reg_req" => { },
"emit" => '. fcos %D1, %S1 $ /* x87 cos(%A1) -> %D1 */'
"emit" => '. fcos %X1 /* x87 cos(%X1) -> %X3 */'
},
"fsqrt" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
"reg_req" => { },
"emit" => '. fsqrt %X3, %X1 $ /* x87 sqrt(%A1) -> %D1 */'
"emit" => '. fsqrt %X1 $ /* x87 sqrt(%X1) -> %X3 */'
},
# virtual Load and Store
# x87 Load and Store
"fld" => {
"rd_constructor" => "NONE",
......@@ -897,7 +965,7 @@ $additional_opcodes = 0;
"state" => "exc_pinned",
"comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { },
"emit" => '. fld %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
"emit" => '. fld %X3, %ia32_emit_am /* Load((%A1)) -> %X3 */'
},
"fst" => {
......@@ -906,7 +974,39 @@ $additional_opcodes = 0;
"state" => "exc_pinned",
"comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { },
"emit" => '. fst %ia32_emit_binop /* Store(%A3) -> (%A1) */'
"emit" => '. fst %ia32_emit_binop /* Store(%X3) -> (%A1) */'
},
"fstp" => {
"rd_constructor" => "NONE",
"op_flags" => "L|F",
"state" => "exc_pinned",
"comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { },
"emit" => '. fstp %ia32_emit_binop /* Store(%X3) -> (%A1) and pop */'
},
# Conversions
"fild" => {
"irn_flags" => "R",
"comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
"reg_req" => { },
"emit" => '. fild %X3, %ia32_emit_am /* integer Load((%A1)) -> %X3 */'
},
"fist" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"reg_req" => { },
"emit" => '. fist %ia32_emit_binop /* integer Store(%X3) -> (%A1) */'
},
"fistp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"reg_req" => { },
"emit" => '. fistp %ia32_emit_binop /* integer Store(%X3) -> (%A1) and pop */'
},
# constants
......@@ -969,7 +1069,7 @@ $additional_opcodes = 0;
"emit" => '. fld%M %C /* Load fConst into register -> %X3 */',
},
# fxch and fpush
# fxch, fpush
"fxch" => {
"comment" => "x87 stack exchange",
......@@ -983,5 +1083,4 @@ $additional_opcodes = 0;
"emit" => '. fld %X1 /* x87 push %X1 */',
},
); # end of %nodes
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