Commit 31cc6d4f authored by Matthias Braun's avatar Matthias Braun
Browse files

amd64: Introduce x86_addr_variant_t instead of using NO_INPUT/RIP_INPUT

parent b6bb56c0
......@@ -259,10 +259,10 @@ static bool is_fp_relative(const ir_entity *entity)
static void amd64_emit_addr(const ir_node *const node,
const amd64_addr_t *const addr)
{
int32_t const offset = addr->immediate.offset;
ir_entity *const entity = addr->immediate.entity;
uint8_t const base_input = addr->base_input;
uint8_t const index_input = addr->index_input;
int32_t const offset = addr->immediate.offset;
ir_entity *const entity = addr->immediate.entity;
x86_addr_variant_t const variant = addr->variant;
assert(variant != X86_ADDR_INVALID);
if (entity != NULL) {
assert(addr->immediate.kind != X86_IMM_VALUE);
......@@ -270,32 +270,33 @@ static void amd64_emit_addr(const ir_node *const node,
emit_relocation_no_offset(addr->immediate.kind, entity);
if (offset != 0)
be_emit_irprintf("%+" PRId32, offset);
} else if (offset != 0
|| (base_input == NO_INPUT && index_input == NO_INPUT)) {
} else if (offset != 0 || variant == X86_ADDR_JUST_IMM) {
assert(addr->immediate.kind == X86_IMM_VALUE);
be_emit_irprintf("%" PRId32, offset);
}
if (base_input != NO_INPUT || index_input != NO_INPUT) {
if (variant != X86_ADDR_JUST_IMM) {
be_emit_char('(');
if (base_input == RIP_INPUT) {
if (variant == X86_ADDR_RIP) {
be_emit_cstring("%rip");
} else if (base_input != NO_INPUT) {
const arch_register_t *reg
= arch_get_irn_register_in(node, base_input);
emit_register(reg);
}
} else {
if (variant == X86_ADDR_BASE || variant == X86_ADDR_BASE_INDEX) {
arch_register_t const *const reg
= arch_get_irn_register_in(node, addr->base_input);
emit_register(reg);
}
if (index_input != NO_INPUT) {
be_emit_char(',');
const arch_register_t *reg
= arch_get_irn_register_in(node, index_input);
emit_register(reg);
if (variant == X86_ADDR_BASE_INDEX || variant == X86_ADDR_INDEX) {
be_emit_char(',');
arch_register_t const *const reg
= arch_get_irn_register_in(node, addr->index_input);
emit_register(reg);
unsigned scale = addr->log_scale;
if (scale > 0)
be_emit_irprintf(",%u", 1 << scale);
unsigned scale = addr->log_scale;
if (scale > 0)
be_emit_irprintf(",%u", 1 << scale);
}
}
be_emit_char(')');
}
......
......@@ -123,18 +123,21 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
amd64_addr_t new_addr = attr->addr;
ir_node *load_in[3];
int load_arity = 0;
if (attr->addr.base_input != NO_INPUT &&
attr->addr.base_input != RIP_INPUT) {
new_addr.base_input = load_arity;
load_in[load_arity++] = get_irn_n(node, attr->addr.base_input);
x86_addr_variant_t variant = attr->addr.variant;
if (variant == X86_ADDR_BASE || variant == X86_ADDR_BASE_INDEX) {
int base_input = load_arity++;
new_addr.base_input = base_input;
load_in[base_input] = get_irn_n(node, attr->addr.base_input);
}
if (attr->addr.index_input != NO_INPUT) {
new_addr.index_input = load_arity;
load_in[load_arity++] = get_irn_n(node, attr->addr.index_input);
if (variant == X86_ADDR_INDEX || variant == X86_ADDR_BASE_INDEX) {
int index_input = load_arity++;
new_addr.index_input = index_input;
load_in[index_input] = get_irn_n(node, attr->addr.index_input);
}
assert(attr->addr.mem_input != NO_INPUT);
new_addr.mem_input = load_arity;
load_in[load_arity++] = get_irn_n(node, attr->addr.mem_input);
int mem_input = load_arity++;
new_addr.mem_input = mem_input;
load_in[mem_input] = get_irn_n(node, attr->addr.mem_input);
assert(get_irn_mode(load_in[mem_input]) == mode_M);
ir_node *const load = new_bd_amd64_mov_gp(dbgi, block, load_arity, load_in, gp_am_reqs[load_arity - 1], attr->insn_mode, AMD64_OP_ADDR, new_addr);
ir_node *const load_res = be_new_Proj_reg(load, pn_amd64_mov_gp_res, out_reg);
......@@ -146,9 +149,10 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
new_in[0] = get_irn_n(node, binop_attr->u.reg_input);
new_in[1] = load_res;
set_irn_in(node, ARRAY_SIZE(new_in), new_in);
attr->base.op_mode = AMD64_OP_REG_REG;
attr->addr.base_input = NO_INPUT;
attr->addr.index_input = NO_INPUT;
attr->base.op_mode = AMD64_OP_REG_REG;
#ifndef NDEBUG
memset(&attr->addr, 0, sizeof(attr->addr));
#endif
/* rewire mem-proj */
foreach_out_edge(node, edge) {
......
......@@ -15,6 +15,7 @@
#include "../ia32/x86_asm.h"
#include "../ia32/x86_cc.h"
#include "../ia32/x86_x87.h"
#include "../ia32/x86_address_mode.h"
#include "compiler.h"
#include "irnode_t.h"
......@@ -60,11 +61,6 @@ typedef enum {
AMD64_OP_X87_ADDR_REG,
} amd64_op_mode_t;
enum {
NO_INPUT = 0xFF,
RIP_INPUT = 0xFE, /* can be used as base_input for PIC code */
};
typedef struct {
ir_entity *entity;
int64_t offset;
......@@ -77,7 +73,8 @@ typedef struct {
uint8_t index_input;
uint8_t mem_input;
unsigned log_scale : 2; /* 0, 1, 2, 3 (giving scale 1, 2, 4, 8) */
ENUMBF(amd64_segment_selector_t) segment : 4;
ENUMBF(amd64_segment_selector_t) segment : 3;
ENUMBF(x86_addr_variant_t) variant : 3;
} amd64_addr_t;
typedef struct {
......
......@@ -132,7 +132,7 @@ my $divop = {
out_reqs => [ "rax", "flags", "mem", "rdx" ],
outs => [ "res_div", "flags", "M", "res_mod" ],
attr_type => "amd64_addr_attr_t",
fixed => "amd64_addr_t addr = { { NULL, 0, X86_IMM_VALUE }, NO_INPUT, NO_INPUT, NO_INPUT, 0, AMD64_SEGMENT_DEFAULT };\n"
fixed => "amd64_addr_t addr = { { .offset = 0 }, .variant = X86_ADDR_JUST_IMM };\n"
."amd64_op_mode_t op_mode = AMD64_OP_REG;\n",
attr => "amd64_insn_mode_t insn_mode",
};
......@@ -169,7 +169,7 @@ my $unop = {
attr_type => "amd64_addr_attr_t",
attr => "amd64_insn_mode_t insn_mode",
fixed => "amd64_op_mode_t op_mode = AMD64_OP_REG;\n"
."amd64_addr_t addr = { { NULL, 0, X86_IMM_VALUE }, NO_INPUT, NO_INPUT, NO_INPUT, 0, AMD64_SEGMENT_DEFAULT };",
."amd64_addr_t addr = { { .offset = 0 }, .variant = X86_ADDR_JUST_IMM };",
};
my $unop_out = {
......
......@@ -363,12 +363,14 @@ void init_lconst_addr(amd64_addr_t *addr, ir_entity *entity)
assert(entity_has_definition(entity));
assert(get_entity_linkage(entity) == IR_LINKAGE_CONSTANT);
assert(get_entity_visibility(entity) == ir_visibility_private);
memset(addr, 0, sizeof(*addr));
x86_immediate_kind_t kind = be_options.pic ? X86_IMM_PCREL : X86_IMM_ADDR;
addr->immediate.entity = entity;
addr->immediate.kind = kind;
addr->index_input = NO_INPUT;
addr->base_input = kind == X86_IMM_PCREL ? RIP_INPUT : NO_INPUT;
*addr = (amd64_addr_t) {
.immediate = {
.entity = entity,
.kind = kind,
},
.variant = kind == X86_IMM_PCREL ? X86_ADDR_RIP : X86_ADDR_JUST_IMM,
};
}
static ir_node *create_float_const(dbg_info *dbgi, ir_node *block,
......@@ -491,9 +493,7 @@ static ir_node *create_picaddr_lea(ir_node *const block,
.kind = kind,
.entity = entity,
},
.base_input = RIP_INPUT,
.index_input = NO_INPUT,
.mem_input = NO_INPUT,
.variant = X86_ADDR_RIP,
};
return new_bd_amd64_lea(NULL, block, 0, NULL, NULL, INSN_MODE_64, addr);
}
......@@ -708,19 +708,21 @@ static void perform_address_matching(ir_node *ptr, int *arity,
memset(&maddr, 0, sizeof(maddr));
x86_create_address_mode(&maddr, ptr, x86_create_am_normal);
if (maddr.base != NULL) {
x86_addr_variant_t variant = maddr.variant;
assert(variant != X86_ADDR_INVALID);
if (variant == X86_ADDR_BASE || variant == X86_ADDR_BASE_INDEX) {
int base_input = (*arity)++;
addr->base_input = base_input;
in[base_input] = be_transform_node(maddr.base);
} else {
addr->base_input = maddr.ip_base ? RIP_INPUT : NO_INPUT;
assert(maddr.base == NULL);
}
if (maddr.index != NULL) {
int index_input = (*arity)++;
if (variant == X86_ADDR_INDEX || variant == X86_ADDR_BASE_INDEX) {
int index_input = (*arity)++;
addr->index_input = index_input;
in[index_input] = be_transform_node(maddr.index);
in[index_input] = be_transform_node(maddr.index);
} else {
addr->index_input = NO_INPUT;
assert(maddr.index == NULL);
}
ir_entity *entity = maddr.imm.entity;
if (entity != NULL && is_parameter_entity(entity) &&
......@@ -729,6 +731,7 @@ static void perform_address_matching(ir_node *ptr, int *arity,
addr->immediate = maddr.imm;
addr->log_scale = maddr.scale;
addr->variant = variant;
}
static void match_binop(amd64_args_t *args, ir_node *block,
......@@ -1016,6 +1019,7 @@ static ir_node *create_add_lea(dbg_info *dbgi, ir_node *new_block,
{
ir_node *in[] = { op1, op2 };
amd64_addr_t addr = {
.variant = X86_ADDR_BASE_INDEX,
.base_input = 0,
.index_input = 1,
};
......@@ -1034,10 +1038,8 @@ static ir_node *match_simple_lea(dbg_info *dbgi, ir_node *new_block,
be_transform_node(op1)
};
amd64_addr_t addr = {
.immediate = immediate,
.base_input = 0,
.index_input = NO_INPUT,
.mem_input = NO_INPUT,
.immediate = immediate,
.variant = X86_ADDR_BASE,
};
return new_bd_amd64_lea(dbgi, new_block, ARRAY_SIZE(in), in, reg_reqs,
insn_mode, addr);
......@@ -1447,8 +1449,8 @@ static ir_node *gen_Member(ir_node *const node)
.entity = entity,
.kind = X86_IMM_FRAMEOFFSET,
},
.base_input = 0,
.index_input = NO_INPUT,
.variant = X86_ADDR_BASE,
.base_input = 0,
};
ir_node *in[] = { base };
return new_bd_amd64_lea(dbgi, new_block, ARRAY_SIZE(in), in, reg_reqs, INSN_MODE_64, addr);
......@@ -1493,12 +1495,10 @@ static ir_node *gen_IJmp(ir_node *const node)
op_mode = AMD64_OP_ADDR;
} else {
op_mode = AMD64_OP_REG;
assert(arity == 0); // AMD64_OP_REG always outputs the first input
in[arity++] = be_transform_node(op);
addr.base_input = NO_INPUT;
addr.index_input = NO_INPUT;
reqs = reg_reqs;
op_mode = AMD64_OP_REG;
in[arity++] = be_transform_node(op);
reqs = reg_reqs;
}
}
......@@ -1548,9 +1548,9 @@ static ir_node *gen_Switch(ir_node *const node)
load_in[load_base] = base;
load_in[load_index] = new_sel;
addr = (amd64_addr_t) {
.variant = X86_ADDR_BASE_INDEX,
.base_input = load_base,
.index_input = load_index,
.mem_input = NO_INPUT,
.log_scale = 2,
};
ir_node *const load
......@@ -1575,7 +1575,7 @@ static ir_node *gen_Switch(ir_node *const node)
.kind = X86_IMM_ADDR,
.entity = entity,
},
.base_input = NO_INPUT,
.variant = X86_ADDR_INDEX,
.index_input = index_in,
.log_scale = 3,
};
......@@ -1719,7 +1719,6 @@ static ir_node *gen_Call(ir_node *const node)
/* match callee */
amd64_addr_t addr;
memset(&addr, 0, sizeof(addr));
addr.mem_input = NO_INPUT;
amd64_op_mode_t op_mode;
ir_node *mem_proj = NULL;
......@@ -1759,13 +1758,11 @@ static ir_node *gen_Call(ir_node *const node)
perform_address_matching(load_ptr, &in_arity, in, &addr);
if (addr.base_input != NO_INPUT) {
x86_addr_variant_t variant = addr.variant;
if (variant == X86_ADDR_BASE || variant == X86_ADDR_BASE_INDEX)
in_req[addr.base_input] = &amd64_class_reg_req_gp;
}
if (addr.index_input != NO_INPUT) {
if (variant == X86_ADDR_BASE_INDEX || variant == X86_ADDR_INDEX)
in_req[addr.index_input] = &amd64_class_reg_req_gp;
}
ir_node *load_mem = get_Load_mem(load);
ir_node *new_load_mem = be_transform_node(load_mem);
......@@ -1778,11 +1775,9 @@ static ir_node *gen_Call(ir_node *const node)
int input = in_arity++;
assert(input == 0); /* AMD64_OP_REG is currently hardcoded to always
* output the register of the first input. */
in[input] = be_transform_node(callee);
in_req[input] = &amd64_class_reg_req_gp;
addr.base_input = NO_INPUT;
addr.index_input = NO_INPUT;
op_mode = AMD64_OP_REG;
in[input] = be_transform_node(callee);
in_req[input] = &amd64_class_reg_req_gp;
op_mode = AMD64_OP_REG;
}
}
sync_ins[sync_arity++] = be_transform_node(mem);
......@@ -1825,13 +1820,15 @@ no_call_mem:
insn_mode = INSN_MODE_32;
/* we need a store if we're here */
amd64_binop_addr_attr_t attr;
memset(&attr, 0, sizeof(attr));
attr.base.base.op_mode = AMD64_OP_ADDR_REG;
attr.base.addr.immediate.offset = param->offset;
attr.base.addr.base_input = 1;
attr.base.addr.index_input = NO_INPUT;
attr.base.insn_mode = insn_mode;
amd64_binop_addr_attr_t attr = {
.base.base.op_mode = AMD64_OP_ADDR_REG,
.base.addr = {
.immediate.offset = param->offset,
.variant = X86_ADDR_BASE,
.base_input = 1,
},
.base.insn_mode = insn_mode,
};
ir_node *const nomem = get_irg_no_mem(irg);
ir_node *const in[] = { new_value, callframe, nomem };
ir_node *const store = mode_is_float(mode) ?
......@@ -2173,16 +2170,17 @@ static void store_to_temp(new_store_func new_store,
ir_node *const new_op = be_transform_node(op);
ir_node *const sin[] = { new_op, frame, nomem };
amd64_binop_addr_attr_t attr;
memset(&attr, 0, sizeof(attr));
attr.base.base.op_mode = AMD64_OP_ADDR_REG;
attr.base.insn_mode = get_insn_mode_from_mode(mode);
attr.u.reg_input = 0;
amd64_addr_t *const daddr = &attr.base.addr;
daddr->base_input = 1;
daddr->index_input = NO_INPUT;
daddr->mem_input = 2;
daddr->immediate.kind = X86_IMM_FRAMEOFFSET;
amd64_binop_addr_attr_t const attr = {
.base.base.op_mode = AMD64_OP_ADDR_REG,
.base.insn_mode = get_insn_mode_from_mode(mode),
.base.addr = {
.immediate.kind = X86_IMM_FRAMEOFFSET,
.variant = X86_ADDR_BASE,
.base_input = 1,
.mem_input = 2,
},
.u.reg_input = 0,
};
ir_node *const store
= new_store(dbgi, block, ARRAY_SIZE(sin), sin, in_reqs, &attr);
......@@ -2192,10 +2190,9 @@ static void store_to_temp(new_store_func new_store,
in[base_input] = frame;
int mem_input = (*n_in)++;
in[mem_input] = store;
memcpy(addr, daddr, sizeof(*addr));
addr->base_input = base_input;
addr->index_input = NO_INPUT;
addr->mem_input = mem_input;
*addr = attr.base.addr;
addr->base_input = base_input;
addr->mem_input = mem_input;
}
static ir_node *conv_sse_to_x87(dbg_info *dbgi, ir_node *block, ir_node *op)
......@@ -2257,11 +2254,7 @@ static ir_node *gen_Conv(ir_node *const node)
// sign-/zero-extending mov has done that
// already.
ir_node *in[] = { op_ext };
amd64_addr_t addr = {
.base_input = NO_INPUT,
.index_input = NO_INPUT,
.mem_input = NO_INPUT,
};
amd64_addr_t addr = { .variant = X86_ADDR_JUST_IMM };
ir_node *const movq = new_bd_amd64_movq(dbgi, block, 1, in, reg_reqs, AMD64_OP_REG, addr);
return be_new_Proj(movq, pn_amd64_movq_res);
} else if (src_bits == 64) {
......@@ -2457,15 +2450,16 @@ ir_node *amd64_new_spill(ir_node *value, ir_node *after)
ir_node *const mem = get_irg_no_mem(irg);
ir_mode *const mode = get_irn_mode(value);
amd64_binop_addr_attr_t attr;
memset(&attr, 0, sizeof(attr));
attr.base.base.op_mode = AMD64_OP_ADDR_REG;
amd64_addr_t *addr = &attr.base.addr;
addr->immediate.kind = X86_IMM_FRAMEOFFSET;
addr->base_input = 1;
addr->index_input = NO_INPUT;
ir_node *in[] = { value, frame, mem };
amd64_binop_addr_attr_t attr = {
.base.base.op_mode = AMD64_OP_ADDR_REG,
.base.addr = {
.immediate.kind = X86_IMM_FRAMEOFFSET,
.variant = X86_ADDR_BASE,
.base_input = 1,
},
.u.reg_input = 0,
};
ir_node *in[] = { value, frame, mem };
amd64_insn_mode_t insn_mode;
new_store_func cons;
......@@ -2512,11 +2506,12 @@ ir_node *amd64_new_reload(ir_node *value, ir_node *spill, ir_node *before)
ir_node *const frame = get_irg_frame(irg);
ir_mode *const mode = get_irn_mode(value);
amd64_addr_t addr;
memset(&addr, 0, sizeof(addr));
addr.base_input = 0;
addr.index_input = NO_INPUT;
amd64_addr_t addr = {
.immediate.kind = X86_IMM_FRAMEOFFSET,
.variant = X86_ADDR_BASE,
.base_input = 0,
.mem_input = 1,
};
ir_node *in[] = { frame, spill };
unsigned pn_res;
......@@ -2998,16 +2993,7 @@ static ir_node *gen_Bitcast(ir_node *const node)
ir_node *const be_op = be_transform_node(op);
ir_node *const be_block = get_nodes_block(be_op);
amd64_addr_t const no_addr = {
.immediate = {
.entity = NULL,
.offset = 0,
},
.base_input = NO_INPUT,
.index_input = NO_INPUT,
.mem_input = NO_INPUT,
.log_scale = AMD64_SEGMENT_DEFAULT
};
amd64_addr_t const no_addr = { .variant = X86_ADDR_JUST_IMM };
if (src_float && !dst_float) {
return new_bd_amd64_movd_xmm_gp(dbgi, be_block, be_op, INSN_MODE_64, AMD64_OP_REG, no_addr);
......
......@@ -295,9 +295,9 @@ static ir_node *make_mov_imm32_to_offset_mem(dbg_info *dbgi, ir_node *block, ir_
.offset = offset,
.kind = X86_IMM_VALUE,
},
.base_input = 0,
.mem_input = 1,
.index_input = NO_INPUT,
.variant = X86_ADDR_BASE,
.base_input = 0,
.mem_input = 1,
},
},
.u = {
......@@ -328,9 +328,9 @@ static ir_node *make_mov_val64_to_offset_mem(dbg_info *dbgi, ir_node *block, ir_
.offset = offset,
.kind = X86_IMM_FRAMEOFFSET,
},
.base_input = 1,
.mem_input = 2,
.index_input = NO_INPUT,
.variant = X86_ADDR_BASE,
.base_input = 1,
.mem_input = 2,
},
},
.u = {
......@@ -358,9 +358,9 @@ static ir_node *make_mov_xmmval64_to_offset_mem(dbg_info *dbgi, ir_node *block,
.offset = offset,
.kind = X86_IMM_FRAMEOFFSET,
},
.base_input = 1,
.mem_input = 2,
.index_input = NO_INPUT,
.variant = X86_ADDR_BASE,
.base_input = 1,
.mem_input = 2,
},
},
.u = {
......@@ -379,12 +379,12 @@ static ir_node *make_lea_with_offset_entity(dbg_info *dbgi, ir_node *block,
{
ir_node *lea_in[] = { base };
amd64_addr_t lea_addr = {
.base_input = 0,
.index_input = NO_INPUT,
.immediate = {
.entity = offset,
.kind = X86_IMM_VALUE,
},
.variant = X86_ADDR_BASE,
.base_input = 0,
};
return new_bd_amd64_lea(dbgi, block, ARRAY_SIZE(lea_in), lea_in, reg_reqs, INSN_MODE_64, lea_addr);
}
......
......@@ -122,8 +122,8 @@ static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp,
.kind = X86_IMM_FRAMEOFFSET,
.entity = ent,
},
.base_input = 1,
.index_input = NO_INPUT,
.variant = X86_ADDR_BASE,
.base_input = 1,
};
ir_node *in[] = { sp, frame, mem };
ir_node *const push = new_bd_amd64_push_am(dbgi, block, ARRAY_SIZE(in), in, rsp_reg_mem_reqs, insn_mode, addr);
......@@ -144,8 +144,8 @@ static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp,
.kind = X86_IMM_FRAMEOFFSET,
.entity = ent,
},
.variant = X86_ADDR_BASE,
.base_input = 1,
.index_input = NO_INPUT,
};
ir_node *in[] = { sp, frame, get_irg_no_mem(irg) };
......
......@@ -210,25 +210,28 @@ void x86_create_address_mode(x86_address_t *addr, ir_node *node,
x86_create_am_flags_t flags)
{
addr->imm.kind = X86_IMM_VALUE;
if (eat_immediate(addr, node, true))
if (eat_immediate(addr, node, true)) {
addr->variant = addr->ip_base ? X86_ADDR_RIP : X86_ADDR_JUST_IMM;
return;
}
assert(!addr->ip_base);
if (!(flags & x86_create_am_force) && x86_is_non_address_mode_node(node)
&& (!(flags & x86_create_am_double_use) || get_irn_n_edges(node) > 2)) {
addr->base = node;
addr->variant = X86_ADDR_BASE;
addr->base = node;
return;
}
ir_node *eat_imms = eat_immediates(addr, node, flags, false);
if (eat_imms != node) {
if (flags & x86_create_am_force) {
if (flags & x86_create_am_force)
eat_imms = be_skip_downconv(eat_imms, true);
}
node = eat_imms;
if (x86_is_non_address_mode_node(node)) {
addr->base = node;
addr->variant = X86_ADDR_BASE;
addr->base = node;
return;
}
}
......@@ -237,10 +240,13 @@ void x86_create_address_mode(x86_address_t *addr, ir_node *node,
if (is_Shl(node)) {
/* We don't want to eat add x, x as shl here, so only test for real Shl
* instructions, because we want the former as Lea x, x, not Shl x, 1 */
if (eat_shl(addr, node))
if (eat_shl(addr, node)) {
addr->variant = X86_ADDR_INDEX;
return;
}
} else if (eat_immediate(addr, node, true)) {
/* we can hit this case in x86_create_am_force mode */
addr->variant = addr->ip_base ? X86_ADDR_RIP : X86_ADDR_JUST_IMM;
return;
} else if (is_Add(node)) {
ir_node *left = get_Add_left(node);
......@@ -286,9 +292,10 @@ tryit:
long val = get_tarval_long(shift_amount);
if (and_mask == shift_mask && val >= 0 && val <= 3) {
addr->base = shr;
addr->index = shr;
addr->scale = val;
addr->variant = X86_ADDR_BASE_INDEX;
addr->base = shr;
addr->index = shr;
addr->scale = val;
return;
}
}
......@@ -299,8 +306,11 @@ tryit:
if (left != NULL) {
ir_node *base = addr