Skip to content
GitLab
Menu
Projects
Groups
Snippets
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Sign in
Toggle navigation
Menu
Open sidebar
Zwinkau
libfirm
Commits
31cc6d4f
Commit
31cc6d4f
authored
Sep 24, 2015
by
Matthias Braun
Browse files
amd64: Introduce x86_addr_variant_t instead of using NO_INPUT/RIP_INPUT
parent
b6bb56c0
Changes
9
Show whitespace changes
Inline
Side-by-side
ir/be/amd64/amd64_emitter.c
View file @
31cc6d4f
...
@@ -261,8 +261,8 @@ static void amd64_emit_addr(const ir_node *const node,
...
@@ -261,8 +261,8 @@ static void amd64_emit_addr(const ir_node *const node,
{
{
int32_t
const
offset
=
addr
->
immediate
.
offset
;
int32_t
const
offset
=
addr
->
immediate
.
offset
;
ir_entity
*
const
entity
=
addr
->
immediate
.
entity
;
ir_entity
*
const
entity
=
addr
->
immediate
.
entity
;
ui
nt
8
_t
const
base_input
=
addr
->
base_inpu
t
;
x86_addr_varia
nt_t
const
variant
=
addr
->
varian
t
;
uint8_t
const
index_inpu
t
=
addr
->
index_input
;
assert
(
varian
t
!
=
X86_ADDR_INVALID
)
;
if
(
entity
!=
NULL
)
{
if
(
entity
!=
NULL
)
{
assert
(
addr
->
immediate
.
kind
!=
X86_IMM_VALUE
);
assert
(
addr
->
immediate
.
kind
!=
X86_IMM_VALUE
);
...
@@ -270,33 +270,34 @@ static void amd64_emit_addr(const ir_node *const node,
...
@@ -270,33 +270,34 @@ static void amd64_emit_addr(const ir_node *const node,
emit_relocation_no_offset
(
addr
->
immediate
.
kind
,
entity
);
emit_relocation_no_offset
(
addr
->
immediate
.
kind
,
entity
);
if
(
offset
!=
0
)
if
(
offset
!=
0
)
be_emit_irprintf
(
"%+"
PRId32
,
offset
);
be_emit_irprintf
(
"%+"
PRId32
,
offset
);
}
else
if
(
offset
!=
0
}
else
if
(
offset
!=
0
||
variant
==
X86_ADDR_JUST_IMM
)
{
||
(
base_input
==
NO_INPUT
&&
index_input
==
NO_INPUT
))
{
assert
(
addr
->
immediate
.
kind
==
X86_IMM_VALUE
);
assert
(
addr
->
immediate
.
kind
==
X86_IMM_VALUE
);
be_emit_irprintf
(
"%"
PRId32
,
offset
);
be_emit_irprintf
(
"%"
PRId32
,
offset
);
}
}
if
(
base_input
!=
NO_INPUT
||
index_input
!=
NO_INPUT
)
{
if
(
variant
!=
X86_ADDR_JUST_IMM
)
{
be_emit_char
(
'('
);
be_emit_char
(
'('
);
if
(
base_input
==
RIP_INPUT
)
{
if
(
variant
==
X86_ADDR_RIP
)
{
be_emit_cstring
(
"%rip"
);
be_emit_cstring
(
"%rip"
);
}
else
if
(
base_input
!=
NO_INPUT
)
{
}
else
{
const
arch_register_t
*
reg
if
(
variant
==
X86_ADDR_BASE
||
variant
==
X86_ADDR_BASE_INDEX
)
{
=
arch_get_irn_register_in
(
node
,
base_input
);
arch_register_t
const
*
const
reg
=
arch_get_irn_register_in
(
node
,
addr
->
base_input
);
emit_register
(
reg
);
emit_register
(
reg
);
}
}
if
(
index_inpu
t
!
=
NO_INPUT
)
{
if
(
variant
==
X86_ADDR_BASE_INDEX
||
varian
t
=
=
X86_ADDR_INDEX
)
{
be_emit_char
(
','
);
be_emit_char
(
','
);
const
arch_register_t
*
reg
arch_register_t
const
*
const
reg
=
arch_get_irn_register_in
(
node
,
index_input
);
=
arch_get_irn_register_in
(
node
,
addr
->
index_input
);
emit_register
(
reg
);
emit_register
(
reg
);
unsigned
scale
=
addr
->
log_scale
;
unsigned
scale
=
addr
->
log_scale
;
if
(
scale
>
0
)
if
(
scale
>
0
)
be_emit_irprintf
(
",%u"
,
1
<<
scale
);
be_emit_irprintf
(
",%u"
,
1
<<
scale
);
}
}
}
be_emit_char
(
')'
);
be_emit_char
(
')'
);
}
}
}
}
...
...
ir/be/amd64/amd64_finish.c
View file @
31cc6d4f
...
@@ -123,18 +123,21 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
...
@@ -123,18 +123,21 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
amd64_addr_t
new_addr
=
attr
->
addr
;
amd64_addr_t
new_addr
=
attr
->
addr
;
ir_node
*
load_in
[
3
];
ir_node
*
load_in
[
3
];
int
load_arity
=
0
;
int
load_arity
=
0
;
if
(
attr
->
addr
.
base_input
!=
NO_INPUT
&&
x86_addr_variant_t
variant
=
attr
->
addr
.
variant
;
attr
->
addr
.
base_input
!=
RIP_INPUT
)
{
if
(
variant
==
X86_ADDR_BASE
||
variant
==
X86_ADDR_BASE_INDEX
)
{
new_addr
.
base_input
=
load_arity
;
int
base_input
=
load_arity
++
;
load_in
[
load_arity
++
]
=
get_irn_n
(
node
,
attr
->
addr
.
base_input
);
new_addr
.
base_input
=
base_input
;
load_in
[
base_input
]
=
get_irn_n
(
node
,
attr
->
addr
.
base_input
);
}
}
if
(
attr
->
addr
.
index_input
!=
NO_INPUT
)
{
if
(
variant
==
X86_ADDR_INDEX
||
variant
==
X86_ADDR_BASE_INDEX
)
{
new_addr
.
index_input
=
load_arity
;
int
index_input
=
load_arity
++
;
load_in
[
load_arity
++
]
=
get_irn_n
(
node
,
attr
->
addr
.
index_input
);
new_addr
.
index_input
=
index_input
;
load_in
[
index_input
]
=
get_irn_n
(
node
,
attr
->
addr
.
index_input
);
}
}
assert
(
attr
->
addr
.
mem_input
!=
NO_INPUT
);
int
mem_input
=
load_arity
++
;
new_addr
.
mem_input
=
load_arity
;
new_addr
.
mem_input
=
mem_input
;
load_in
[
load_arity
++
]
=
get_irn_n
(
node
,
attr
->
addr
.
mem_input
);
load_in
[
mem_input
]
=
get_irn_n
(
node
,
attr
->
addr
.
mem_input
);
assert
(
get_irn_mode
(
load_in
[
mem_input
])
==
mode_M
);
ir_node
*
const
load
=
new_bd_amd64_mov_gp
(
dbgi
,
block
,
load_arity
,
load_in
,
gp_am_reqs
[
load_arity
-
1
],
attr
->
insn_mode
,
AMD64_OP_ADDR
,
new_addr
);
ir_node
*
const
load
=
new_bd_amd64_mov_gp
(
dbgi
,
block
,
load_arity
,
load_in
,
gp_am_reqs
[
load_arity
-
1
],
attr
->
insn_mode
,
AMD64_OP_ADDR
,
new_addr
);
ir_node
*
const
load_res
=
be_new_Proj_reg
(
load
,
pn_amd64_mov_gp_res
,
out_reg
);
ir_node
*
const
load_res
=
be_new_Proj_reg
(
load
,
pn_amd64_mov_gp_res
,
out_reg
);
...
@@ -147,8 +150,9 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
...
@@ -147,8 +150,9 @@ static void amd64_turn_back_am(ir_node *const node, arch_register_t const *const
new_in
[
1
]
=
load_res
;
new_in
[
1
]
=
load_res
;
set_irn_in
(
node
,
ARRAY_SIZE
(
new_in
),
new_in
);
set_irn_in
(
node
,
ARRAY_SIZE
(
new_in
),
new_in
);
attr
->
base
.
op_mode
=
AMD64_OP_REG_REG
;
attr
->
base
.
op_mode
=
AMD64_OP_REG_REG
;
attr
->
addr
.
base_input
=
NO_INPUT
;
#ifndef NDEBUG
attr
->
addr
.
index_input
=
NO_INPUT
;
memset
(
&
attr
->
addr
,
0
,
sizeof
(
attr
->
addr
));
#endif
/* rewire mem-proj */
/* rewire mem-proj */
foreach_out_edge
(
node
,
edge
)
{
foreach_out_edge
(
node
,
edge
)
{
...
...
ir/be/amd64/amd64_nodes_attr.h
View file @
31cc6d4f
...
@@ -15,6 +15,7 @@
...
@@ -15,6 +15,7 @@
#include "../ia32/x86_asm.h"
#include "../ia32/x86_asm.h"
#include "../ia32/x86_cc.h"
#include "../ia32/x86_cc.h"
#include "../ia32/x86_x87.h"
#include "../ia32/x86_x87.h"
#include "../ia32/x86_address_mode.h"
#include "compiler.h"
#include "compiler.h"
#include "irnode_t.h"
#include "irnode_t.h"
...
@@ -60,11 +61,6 @@ typedef enum {
...
@@ -60,11 +61,6 @@ typedef enum {
AMD64_OP_X87_ADDR_REG
,
AMD64_OP_X87_ADDR_REG
,
}
amd64_op_mode_t
;
}
amd64_op_mode_t
;
enum
{
NO_INPUT
=
0xFF
,
RIP_INPUT
=
0xFE
,
/* can be used as base_input for PIC code */
};
typedef
struct
{
typedef
struct
{
ir_entity
*
entity
;
ir_entity
*
entity
;
int64_t
offset
;
int64_t
offset
;
...
@@ -77,7 +73,8 @@ typedef struct {
...
@@ -77,7 +73,8 @@ typedef struct {
uint8_t
index_input
;
uint8_t
index_input
;
uint8_t
mem_input
;
uint8_t
mem_input
;
unsigned
log_scale
:
2
;
/* 0, 1, 2, 3 (giving scale 1, 2, 4, 8) */
unsigned
log_scale
:
2
;
/* 0, 1, 2, 3 (giving scale 1, 2, 4, 8) */
ENUMBF
(
amd64_segment_selector_t
)
segment
:
4
;
ENUMBF
(
amd64_segment_selector_t
)
segment
:
3
;
ENUMBF
(
x86_addr_variant_t
)
variant
:
3
;
}
amd64_addr_t
;
}
amd64_addr_t
;
typedef
struct
{
typedef
struct
{
...
...
ir/be/amd64/amd64_spec.pl
View file @
31cc6d4f
...
@@ -132,7 +132,7 @@ my $divop = {
...
@@ -132,7 +132,7 @@ my $divop = {
out_reqs
=>
[
"
rax
",
"
flags
",
"
mem
",
"
rdx
"
],
out_reqs
=>
[
"
rax
",
"
flags
",
"
mem
",
"
rdx
"
],
outs
=>
[
"
res_div
",
"
flags
",
"
M
",
"
res_mod
"
],
outs
=>
[
"
res_div
",
"
flags
",
"
M
",
"
res_mod
"
],
attr_type
=>
"
amd64_addr_attr_t
",
attr_type
=>
"
amd64_addr_attr_t
",
fixed
=>
"
amd64_addr_t addr = { {
NULL, 0, X86_IMM_VALUE }, NO_INPUT, NO_INPUT, NO_INPUT, 0, AMD64_SEGMENT_DEFAULT
};
\n
"
fixed
=>
"
amd64_addr_t addr = { {
.offset = 0 }, .variant = X86_ADDR_JUST_IMM
};
\n
"
.
"
amd64_op_mode_t op_mode = AMD64_OP_REG;
\n
",
.
"
amd64_op_mode_t op_mode = AMD64_OP_REG;
\n
",
attr
=>
"
amd64_insn_mode_t insn_mode
",
attr
=>
"
amd64_insn_mode_t insn_mode
",
};
};
...
@@ -169,7 +169,7 @@ my $unop = {
...
@@ -169,7 +169,7 @@ my $unop = {
attr_type
=>
"
amd64_addr_attr_t
",
attr_type
=>
"
amd64_addr_attr_t
",
attr
=>
"
amd64_insn_mode_t insn_mode
",
attr
=>
"
amd64_insn_mode_t insn_mode
",
fixed
=>
"
amd64_op_mode_t op_mode = AMD64_OP_REG;
\n
"
fixed
=>
"
amd64_op_mode_t op_mode = AMD64_OP_REG;
\n
"
.
"
amd64_addr_t addr = { {
NULL, 0, X86_IMM_VALUE }, NO_INPUT, NO_INPUT, NO_INPUT, 0, AMD64_SEGMENT_DEFAULT
};
",
.
"
amd64_addr_t addr = { {
.offset = 0 }, .variant = X86_ADDR_JUST_IMM
};
",
};
};
my
$unop_out
=
{
my
$unop_out
=
{
...
...
ir/be/amd64/amd64_transform.c
View file @
31cc6d4f
...
@@ -363,12 +363,14 @@ void init_lconst_addr(amd64_addr_t *addr, ir_entity *entity)
...
@@ -363,12 +363,14 @@ void init_lconst_addr(amd64_addr_t *addr, ir_entity *entity)
assert
(
entity_has_definition
(
entity
));
assert
(
entity_has_definition
(
entity
));
assert
(
get_entity_linkage
(
entity
)
==
IR_LINKAGE_CONSTANT
);
assert
(
get_entity_linkage
(
entity
)
==
IR_LINKAGE_CONSTANT
);
assert
(
get_entity_visibility
(
entity
)
==
ir_visibility_private
);
assert
(
get_entity_visibility
(
entity
)
==
ir_visibility_private
);
memset
(
addr
,
0
,
sizeof
(
*
addr
));
x86_immediate_kind_t
kind
=
be_options
.
pic
?
X86_IMM_PCREL
:
X86_IMM_ADDR
;
x86_immediate_kind_t
kind
=
be_options
.
pic
?
X86_IMM_PCREL
:
X86_IMM_ADDR
;
addr
->
immediate
.
entity
=
entity
;
*
addr
=
(
amd64_addr_t
)
{
addr
->
immediate
.
kind
=
kind
;
.
immediate
=
{
addr
->
index_input
=
NO_INPUT
;
.
entity
=
entity
,
addr
->
base_input
=
kind
==
X86_IMM_PCREL
?
RIP_INPUT
:
NO_INPUT
;
.
kind
=
kind
,
},
.
variant
=
kind
==
X86_IMM_PCREL
?
X86_ADDR_RIP
:
X86_ADDR_JUST_IMM
,
};
}
}
static
ir_node
*
create_float_const
(
dbg_info
*
dbgi
,
ir_node
*
block
,
static
ir_node
*
create_float_const
(
dbg_info
*
dbgi
,
ir_node
*
block
,
...
@@ -491,9 +493,7 @@ static ir_node *create_picaddr_lea(ir_node *const block,
...
@@ -491,9 +493,7 @@ static ir_node *create_picaddr_lea(ir_node *const block,
.
kind
=
kind
,
.
kind
=
kind
,
.
entity
=
entity
,
.
entity
=
entity
,
},
},
.
base_input
=
RIP_INPUT
,
.
variant
=
X86_ADDR_RIP
,
.
index_input
=
NO_INPUT
,
.
mem_input
=
NO_INPUT
,
};
};
return
new_bd_amd64_lea
(
NULL
,
block
,
0
,
NULL
,
NULL
,
INSN_MODE_64
,
addr
);
return
new_bd_amd64_lea
(
NULL
,
block
,
0
,
NULL
,
NULL
,
INSN_MODE_64
,
addr
);
}
}
...
@@ -708,19 +708,21 @@ static void perform_address_matching(ir_node *ptr, int *arity,
...
@@ -708,19 +708,21 @@ static void perform_address_matching(ir_node *ptr, int *arity,
memset
(
&
maddr
,
0
,
sizeof
(
maddr
));
memset
(
&
maddr
,
0
,
sizeof
(
maddr
));
x86_create_address_mode
(
&
maddr
,
ptr
,
x86_create_am_normal
);
x86_create_address_mode
(
&
maddr
,
ptr
,
x86_create_am_normal
);
if
(
maddr
.
base
!=
NULL
)
{
x86_addr_variant_t
variant
=
maddr
.
variant
;
assert
(
variant
!=
X86_ADDR_INVALID
);
if
(
variant
==
X86_ADDR_BASE
||
variant
==
X86_ADDR_BASE_INDEX
)
{
int
base_input
=
(
*
arity
)
++
;
int
base_input
=
(
*
arity
)
++
;
addr
->
base_input
=
base_input
;
addr
->
base_input
=
base_input
;
in
[
base_input
]
=
be_transform_node
(
maddr
.
base
);
in
[
base_input
]
=
be_transform_node
(
maddr
.
base
);
}
else
{
}
else
{
a
ddr
->
base_input
=
maddr
.
ip_
base
?
RIP_INPUT
:
NO_INPUT
;
a
ssert
(
maddr
.
base
==
NULL
)
;
}
}
if
(
maddr
.
index
!=
NULL
)
{
if
(
variant
==
X86_ADDR_INDEX
||
variant
==
X86_ADDR_BASE_INDEX
)
{
int
index_input
=
(
*
arity
)
++
;
int
index_input
=
(
*
arity
)
++
;
addr
->
index_input
=
index_input
;
addr
->
index_input
=
index_input
;
in
[
index_input
]
=
be_transform_node
(
maddr
.
index
);
in
[
index_input
]
=
be_transform_node
(
maddr
.
index
);
}
else
{
}
else
{
addr
->
index
_input
=
NO_INPUT
;
assert
(
m
addr
.
index
==
NULL
)
;
}
}
ir_entity
*
entity
=
maddr
.
imm
.
entity
;
ir_entity
*
entity
=
maddr
.
imm
.
entity
;
if
(
entity
!=
NULL
&&
is_parameter_entity
(
entity
)
&&
if
(
entity
!=
NULL
&&
is_parameter_entity
(
entity
)
&&
...
@@ -729,6 +731,7 @@ static void perform_address_matching(ir_node *ptr, int *arity,
...
@@ -729,6 +731,7 @@ static void perform_address_matching(ir_node *ptr, int *arity,
addr
->
immediate
=
maddr
.
imm
;
addr
->
immediate
=
maddr
.
imm
;
addr
->
log_scale
=
maddr
.
scale
;
addr
->
log_scale
=
maddr
.
scale
;
addr
->
variant
=
variant
;
}
}
static
void
match_binop
(
amd64_args_t
*
args
,
ir_node
*
block
,
static
void
match_binop
(
amd64_args_t
*
args
,
ir_node
*
block
,
...
@@ -1016,6 +1019,7 @@ static ir_node *create_add_lea(dbg_info *dbgi, ir_node *new_block,
...
@@ -1016,6 +1019,7 @@ static ir_node *create_add_lea(dbg_info *dbgi, ir_node *new_block,
{
{
ir_node
*
in
[]
=
{
op1
,
op2
};
ir_node
*
in
[]
=
{
op1
,
op2
};
amd64_addr_t
addr
=
{
amd64_addr_t
addr
=
{
.
variant
=
X86_ADDR_BASE_INDEX
,
.
base_input
=
0
,
.
base_input
=
0
,
.
index_input
=
1
,
.
index_input
=
1
,
};
};
...
@@ -1035,9 +1039,7 @@ static ir_node *match_simple_lea(dbg_info *dbgi, ir_node *new_block,
...
@@ -1035,9 +1039,7 @@ static ir_node *match_simple_lea(dbg_info *dbgi, ir_node *new_block,
};
};
amd64_addr_t
addr
=
{
amd64_addr_t
addr
=
{
.
immediate
=
immediate
,
.
immediate
=
immediate
,
.
base_input
=
0
,
.
variant
=
X86_ADDR_BASE
,
.
index_input
=
NO_INPUT
,
.
mem_input
=
NO_INPUT
,
};
};
return
new_bd_amd64_lea
(
dbgi
,
new_block
,
ARRAY_SIZE
(
in
),
in
,
reg_reqs
,
return
new_bd_amd64_lea
(
dbgi
,
new_block
,
ARRAY_SIZE
(
in
),
in
,
reg_reqs
,
insn_mode
,
addr
);
insn_mode
,
addr
);
...
@@ -1447,8 +1449,8 @@ static ir_node *gen_Member(ir_node *const node)
...
@@ -1447,8 +1449,8 @@ static ir_node *gen_Member(ir_node *const node)
.
entity
=
entity
,
.
entity
=
entity
,
.
kind
=
X86_IMM_FRAMEOFFSET
,
.
kind
=
X86_IMM_FRAMEOFFSET
,
},
},
.
variant
=
X86_ADDR_BASE
,
.
base_input
=
0
,
.
base_input
=
0
,
.
index_input
=
NO_INPUT
,
};
};
ir_node
*
in
[]
=
{
base
};
ir_node
*
in
[]
=
{
base
};
return
new_bd_amd64_lea
(
dbgi
,
new_block
,
ARRAY_SIZE
(
in
),
in
,
reg_reqs
,
INSN_MODE_64
,
addr
);
return
new_bd_amd64_lea
(
dbgi
,
new_block
,
ARRAY_SIZE
(
in
),
in
,
reg_reqs
,
INSN_MODE_64
,
addr
);
...
@@ -1493,11 +1495,9 @@ static ir_node *gen_IJmp(ir_node *const node)
...
@@ -1493,11 +1495,9 @@ static ir_node *gen_IJmp(ir_node *const node)
op_mode
=
AMD64_OP_ADDR
;
op_mode
=
AMD64_OP_ADDR
;
}
else
{
}
else
{
op_mode
=
AMD64_OP_REG
;
assert
(
arity
==
0
);
// AMD64_OP_REG always outputs the first input
assert
(
arity
==
0
);
// AMD64_OP_REG always outputs the first input
op_mode
=
AMD64_OP_REG
;
in
[
arity
++
]
=
be_transform_node
(
op
);
in
[
arity
++
]
=
be_transform_node
(
op
);
addr
.
base_input
=
NO_INPUT
;
addr
.
index_input
=
NO_INPUT
;
reqs
=
reg_reqs
;
reqs
=
reg_reqs
;
}
}
}
}
...
@@ -1548,9 +1548,9 @@ static ir_node *gen_Switch(ir_node *const node)
...
@@ -1548,9 +1548,9 @@ static ir_node *gen_Switch(ir_node *const node)
load_in
[
load_base
]
=
base
;
load_in
[
load_base
]
=
base
;
load_in
[
load_index
]
=
new_sel
;
load_in
[
load_index
]
=
new_sel
;
addr
=
(
amd64_addr_t
)
{
addr
=
(
amd64_addr_t
)
{
.
variant
=
X86_ADDR_BASE_INDEX
,
.
base_input
=
load_base
,
.
base_input
=
load_base
,
.
index_input
=
load_index
,
.
index_input
=
load_index
,
.
mem_input
=
NO_INPUT
,
.
log_scale
=
2
,
.
log_scale
=
2
,
};
};
ir_node
*
const
load
ir_node
*
const
load
...
@@ -1575,7 +1575,7 @@ static ir_node *gen_Switch(ir_node *const node)
...
@@ -1575,7 +1575,7 @@ static ir_node *gen_Switch(ir_node *const node)
.
kind
=
X86_IMM_ADDR
,
.
kind
=
X86_IMM_ADDR
,
.
entity
=
entity
,
.
entity
=
entity
,
},
},
.
base_input
=
NO_INPUT
,
.
variant
=
X86_ADDR_INDEX
,
.
index_input
=
index_in
,
.
index_input
=
index_in
,
.
log_scale
=
3
,
.
log_scale
=
3
,
};
};
...
@@ -1719,7 +1719,6 @@ static ir_node *gen_Call(ir_node *const node)
...
@@ -1719,7 +1719,6 @@ static ir_node *gen_Call(ir_node *const node)
/* match callee */
/* match callee */
amd64_addr_t
addr
;
amd64_addr_t
addr
;
memset
(
&
addr
,
0
,
sizeof
(
addr
));
memset
(
&
addr
,
0
,
sizeof
(
addr
));
addr
.
mem_input
=
NO_INPUT
;
amd64_op_mode_t
op_mode
;
amd64_op_mode_t
op_mode
;
ir_node
*
mem_proj
=
NULL
;
ir_node
*
mem_proj
=
NULL
;
...
@@ -1759,13 +1758,11 @@ static ir_node *gen_Call(ir_node *const node)
...
@@ -1759,13 +1758,11 @@ static ir_node *gen_Call(ir_node *const node)
perform_address_matching
(
load_ptr
,
&
in_arity
,
in
,
&
addr
);
perform_address_matching
(
load_ptr
,
&
in_arity
,
in
,
&
addr
);
if
(
addr
.
base_input
!=
NO_INPUT
)
{
x86_addr_variant_t
variant
=
addr
.
variant
;
if
(
variant
==
X86_ADDR_BASE
||
variant
==
X86_ADDR_BASE_INDEX
)
in_req
[
addr
.
base_input
]
=
&
amd64_class_reg_req_gp
;
in_req
[
addr
.
base_input
]
=
&
amd64_class_reg_req_gp
;
}
if
(
variant
==
X86_ADDR_BASE_INDEX
||
variant
==
X86_ADDR_INDEX
)
if
(
addr
.
index_input
!=
NO_INPUT
)
{
in_req
[
addr
.
index_input
]
=
&
amd64_class_reg_req_gp
;
in_req
[
addr
.
index_input
]
=
&
amd64_class_reg_req_gp
;
}
ir_node
*
load_mem
=
get_Load_mem
(
load
);
ir_node
*
load_mem
=
get_Load_mem
(
load
);
ir_node
*
new_load_mem
=
be_transform_node
(
load_mem
);
ir_node
*
new_load_mem
=
be_transform_node
(
load_mem
);
...
@@ -1780,8 +1777,6 @@ static ir_node *gen_Call(ir_node *const node)
...
@@ -1780,8 +1777,6 @@ static ir_node *gen_Call(ir_node *const node)
* output the register of the first input. */
* output the register of the first input. */
in
[
input
]
=
be_transform_node
(
callee
);
in
[
input
]
=
be_transform_node
(
callee
);
in_req
[
input
]
=
&
amd64_class_reg_req_gp
;
in_req
[
input
]
=
&
amd64_class_reg_req_gp
;
addr
.
base_input
=
NO_INPUT
;
addr
.
index_input
=
NO_INPUT
;
op_mode
=
AMD64_OP_REG
;
op_mode
=
AMD64_OP_REG
;
}
}
}
}
...
@@ -1825,13 +1820,15 @@ no_call_mem:
...
@@ -1825,13 +1820,15 @@ no_call_mem:
insn_mode
=
INSN_MODE_32
;
insn_mode
=
INSN_MODE_32
;
/* we need a store if we're here */
/* we need a store if we're here */
amd64_binop_addr_attr_t
attr
;
amd64_binop_addr_attr_t
attr
=
{
memset
(
&
attr
,
0
,
sizeof
(
attr
));
.
base
.
base
.
op_mode
=
AMD64_OP_ADDR_REG
,
attr
.
base
.
base
.
op_mode
=
AMD64_OP_ADDR_REG
;
.
base
.
addr
=
{
attr
.
base
.
addr
.
immediate
.
offset
=
param
->
offset
;
.
immediate
.
offset
=
param
->
offset
,
attr
.
base
.
addr
.
base_input
=
1
;
.
variant
=
X86_ADDR_BASE
,
attr
.
base
.
addr
.
index_input
=
NO_INPUT
;
.
base_input
=
1
,
attr
.
base
.
insn_mode
=
insn_mode
;
},
.
base
.
insn_mode
=
insn_mode
,
};
ir_node
*
const
nomem
=
get_irg_no_mem
(
irg
);
ir_node
*
const
nomem
=
get_irg_no_mem
(
irg
);
ir_node
*
const
in
[]
=
{
new_value
,
callframe
,
nomem
};
ir_node
*
const
in
[]
=
{
new_value
,
callframe
,
nomem
};
ir_node
*
const
store
=
mode_is_float
(
mode
)
?
ir_node
*
const
store
=
mode_is_float
(
mode
)
?
...
@@ -2173,16 +2170,17 @@ static void store_to_temp(new_store_func new_store,
...
@@ -2173,16 +2170,17 @@ static void store_to_temp(new_store_func new_store,
ir_node
*
const
new_op
=
be_transform_node
(
op
);
ir_node
*
const
new_op
=
be_transform_node
(
op
);
ir_node
*
const
sin
[]
=
{
new_op
,
frame
,
nomem
};
ir_node
*
const
sin
[]
=
{
new_op
,
frame
,
nomem
};
amd64_binop_addr_attr_t
attr
;
amd64_binop_addr_attr_t
const
attr
=
{
memset
(
&
attr
,
0
,
sizeof
(
attr
));
.
base
.
base
.
op_mode
=
AMD64_OP_ADDR_REG
,
attr
.
base
.
base
.
op_mode
=
AMD64_OP_ADDR_REG
;
.
base
.
insn_mode
=
get_insn_mode_from_mode
(
mode
),
attr
.
base
.
insn_mode
=
get_insn_mode_from_mode
(
mode
);
.
base
.
addr
=
{
attr
.
u
.
reg_input
=
0
;
.
immediate
.
kind
=
X86_IMM_FRAMEOFFSET
,
amd64_addr_t
*
const
daddr
=
&
attr
.
base
.
addr
;
.
variant
=
X86_ADDR_BASE
,
daddr
->
base_input
=
1
;
.
base_input
=
1
,
daddr
->
index_input
=
NO_INPUT
;
.
mem_input
=
2
,
daddr
->
mem_input
=
2
;
},
daddr
->
immediate
.
kind
=
X86_IMM_FRAMEOFFSET
;
.
u
.
reg_input
=
0
,
};
ir_node
*
const
store
ir_node
*
const
store
=
new_store
(
dbgi
,
block
,
ARRAY_SIZE
(
sin
),
sin
,
in_reqs
,
&
attr
);
=
new_store
(
dbgi
,
block
,
ARRAY_SIZE
(
sin
),
sin
,
in_reqs
,
&
attr
);
...
@@ -2192,9 +2190,8 @@ static void store_to_temp(new_store_func new_store,
...
@@ -2192,9 +2190,8 @@ static void store_to_temp(new_store_func new_store,
in
[
base_input
]
=
frame
;
in
[
base_input
]
=
frame
;
int
mem_input
=
(
*
n_in
)
++
;
int
mem_input
=
(
*
n_in
)
++
;
in
[
mem_input
]
=
store
;
in
[
mem_input
]
=
store
;
memcpy
(
addr
,
daddr
,
sizeof
(
*
addr
))
;
*
addr
=
attr
.
base
.
addr
;
addr
->
base_input
=
base_input
;
addr
->
base_input
=
base_input
;
addr
->
index_input
=
NO_INPUT
;
addr
->
mem_input
=
mem_input
;
addr
->
mem_input
=
mem_input
;
}
}
...
@@ -2257,11 +2254,7 @@ static ir_node *gen_Conv(ir_node *const node)
...
@@ -2257,11 +2254,7 @@ static ir_node *gen_Conv(ir_node *const node)
// sign-/zero-extending mov has done that
// sign-/zero-extending mov has done that
// already.
// already.
ir_node
*
in
[]
=
{
op_ext
};
ir_node
*
in
[]
=
{
op_ext
};
amd64_addr_t
addr
=
{
amd64_addr_t
addr
=
{
.
variant
=
X86_ADDR_JUST_IMM
};
.
base_input
=
NO_INPUT
,
.
index_input
=
NO_INPUT
,
.
mem_input
=
NO_INPUT
,
};
ir_node
*
const
movq
=
new_bd_amd64_movq
(
dbgi
,
block
,
1
,
in
,
reg_reqs
,
AMD64_OP_REG
,
addr
);
ir_node
*
const
movq
=
new_bd_amd64_movq
(
dbgi
,
block
,
1
,
in
,
reg_reqs
,
AMD64_OP_REG
,
addr
);
return
be_new_Proj
(
movq
,
pn_amd64_movq_res
);
return
be_new_Proj
(
movq
,
pn_amd64_movq_res
);
}
else
if
(
src_bits
==
64
)
{
}
else
if
(
src_bits
==
64
)
{
...
@@ -2457,14 +2450,15 @@ ir_node *amd64_new_spill(ir_node *value, ir_node *after)
...
@@ -2457,14 +2450,15 @@ ir_node *amd64_new_spill(ir_node *value, ir_node *after)
ir_node
*
const
mem
=
get_irg_no_mem
(
irg
);
ir_node
*
const
mem
=
get_irg_no_mem
(
irg
);
ir_mode
*
const
mode
=
get_irn_mode
(
value
);
ir_mode
*
const
mode
=
get_irn_mode
(
value
);
amd64_binop_addr_attr_t
attr
;
amd64_binop_addr_attr_t
attr
=
{
memset
(
&
attr
,
0
,
sizeof
(
attr
));
.
base
.
base
.
op_mode
=
AMD64_OP_ADDR_REG
,
attr
.
base
.
base
.
op_mode
=
AMD64_OP_ADDR_REG
;
.
base
.
addr
=
{
.
immediate
.
kind
=
X86_IMM_FRAMEOFFSET
,
amd64_addr_t
*
addr
=
&
attr
.
base
.
addr
;
.
variant
=
X86_ADDR_BASE
,
addr
->
immediate
.
kind
=
X86_IMM_FRAMEOFFSET
;
.
base_input
=
1
,
addr
->
base_input
=
1
;
},
addr
->
index_input
=
NO_INPUT
;
.
u
.
reg_input
=
0
,
};
ir_node
*
in
[]
=
{
value
,
frame
,
mem
};
ir_node
*
in
[]
=
{
value
,
frame
,
mem
};
amd64_insn_mode_t
insn_mode
;
amd64_insn_mode_t
insn_mode
;
...
@@ -2512,11 +2506,12 @@ ir_node *amd64_new_reload(ir_node *value, ir_node *spill, ir_node *before)
...
@@ -2512,11 +2506,12 @@ ir_node *amd64_new_reload(ir_node *value, ir_node *spill, ir_node *before)
ir_node
*
const
frame
=
get_irg_frame
(
irg
);
ir_node
*
const
frame
=
get_irg_frame
(
irg
);
ir_mode
*
const
mode
=
get_irn_mode
(
value
);
ir_mode
*
const
mode
=
get_irn_mode
(
value
);
amd64_addr_t
addr
;
amd64_addr_t
addr
=
{
memset
(
&
addr
,
0
,
sizeof
(
addr
));
.
immediate
.
kind
=
X86_IMM_FRAMEOFFSET
,
addr
.
base_input
=
0
;
.
variant
=
X86_ADDR_BASE
,
addr
.
index_input
=
NO_INPUT
;
.
base_input
=
0
,
.
mem_input
=
1
,
};
ir_node
*
in
[]
=
{
frame
,
spill
};
ir_node
*
in
[]
=
{
frame
,
spill
};
unsigned
pn_res
;
unsigned
pn_res
;
...
@@ -2998,16 +2993,7 @@ static ir_node *gen_Bitcast(ir_node *const node)
...
@@ -2998,16 +2993,7 @@ static ir_node *gen_Bitcast(ir_node *const node)
ir_node
*
const
be_op
=
be_transform_node
(
op
);
ir_node
*
const
be_op
=
be_transform_node
(
op
);
ir_node
*
const
be_block
=
get_nodes_block
(
be_op
);
ir_node
*
const
be_block
=
get_nodes_block
(
be_op
);
amd64_addr_t
const
no_addr
=
{
amd64_addr_t
const
no_addr
=
{
.
variant
=
X86_ADDR_JUST_IMM
};
.
immediate
=
{
.
entity
=
NULL
,
.
offset
=
0
,
},
.
base_input
=
NO_INPUT
,
.
index_input
=
NO_INPUT
,
.
mem_input
=
NO_INPUT
,
.
log_scale
=
AMD64_SEGMENT_DEFAULT
};
if
(
src_float
&&
!
dst_float
)
{
if
(
src_float
&&
!
dst_float
)
{
return
new_bd_amd64_movd_xmm_gp
(
dbgi
,
be_block
,
be_op
,
INSN_MODE_64
,
AMD64_OP_REG
,
no_addr
);
return
new_bd_amd64_movd_xmm_gp
(
dbgi
,
be_block
,
be_op
,
INSN_MODE_64
,
AMD64_OP_REG
,
no_addr
);
...
...
ir/be/amd64/amd64_varargs.c
View file @
31cc6d4f
...
@@ -295,9 +295,9 @@ static ir_node *make_mov_imm32_to_offset_mem(dbg_info *dbgi, ir_node *block, ir_
...
@@ -295,9 +295,9 @@ static ir_node *make_mov_imm32_to_offset_mem(dbg_info *dbgi, ir_node *block, ir_
.
offset
=
offset
,
.
offset
=
offset
,