Commit 44dd4365 authored by Matthias Braun's avatar Matthias Braun
Browse files

- further refactoring and finally eliminated the callback for get_out_reg_reqs

- Introduced be_Start which is now used instead of iro_Start+be_RegParams
- further cleanups and fixes along the way

[r26549]
parent 15769c9f
......@@ -116,7 +116,7 @@ typedef enum {
beo_AddSP,
beo_SubSP,
beo_IncSP,
beo_RegParams,
beo_Start,
beo_FrameAddr,
beo_Barrier,
/* last backend node number */
......
......@@ -140,15 +140,6 @@ const arch_register_req_t *get_TEMPLATE_in_req(const ir_node *node, int pos)
return attr->in_req[pos];
}
/**
* Returns the result register requirement at position pos of an TEMPLATE node.
*/
const arch_register_req_t *get_TEMPLATE_out_req(const ir_node *node, int pos)
{
const backend_info_t *info = be_get_info(node);
return info->out_infos[pos].req;
}
/**
* Sets the IN register requirements at position pos.
*/
......
......@@ -55,11 +55,6 @@ const arch_register_req_t **get_TEMPLATE_in_req_all(const ir_node *node);
*/
const arch_register_req_t *get_TEMPLATE_in_req(const ir_node *node, int pos);
/**
* Returns the result register requirements of an TEMPLATE node.
*/
const arch_register_req_t *get_TEMPLATE_out_req(const ir_node *node, int pos);
/**
* Sets the IN register requirements at position pos.
*/
......
......@@ -367,6 +367,13 @@ Const => {
'
},
Jmp => {
state => "pinned",
op_flags => "X",
reg_req => { out => [ "none" ] },
mode => "mode_X",
},
# Load / Store
Load => {
......
......@@ -281,7 +281,10 @@ static ir_node *gen_Store(TEMPLATE_transform_env_t *env)
return new_bd_TEMPLATE_Store(env->dbg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
}
static ir_node *gen_Jmp(TEMPLATE_transform_env_t *env)
{
return new_bd_TEMPLATE_Jmp(env->dbg, env->block);
}
/*********************************************************
* _ _ _
......@@ -344,6 +347,7 @@ void TEMPLATE_transform_node(ir_node *node, void *env)
GEN(Load);
GEN(Store);
GEN(Jmp);
/* TODO: implement these nodes */
IGN(Shrs);
......@@ -373,7 +377,6 @@ void TEMPLATE_transform_node(ir_node *node, void *env)
IGN(NoMem);
IGN(Phi);
IGN(IJmp);
IGN(Jmp);
IGN(Break);
IGN(Sync);
......
......@@ -105,7 +105,6 @@ static int TEMPLATE_get_sp_bias(const ir_node *irn)
static const arch_irn_ops_t TEMPLATE_irn_ops = {
get_TEMPLATE_in_req,
get_TEMPLATE_out_req,
TEMPLATE_classify,
TEMPLATE_get_frame_entity,
TEMPLATE_set_frame_entity,
......
......@@ -1037,12 +1037,11 @@ static void arm_register_emitters(void) {
/* noisy stuff */
#ifdef SILENCER
SILENCE(Start);
SILENCE(Proj);
SILENCE(Phi);
SILENCE(be_Keep);
SILENCE(be_CopyKeep);
SILENCE(be_RegParams);
SILENCE(be_Start);
SILENCE(be_Barrier);
SILENCE(be_Return);
#endif
......
......@@ -247,15 +247,6 @@ const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos) {
return attr->in_req[pos];
}
/**
* Returns the result register requirement at position pos of an arm node.
*/
const arch_register_req_t *get_arm_out_req(const ir_node *node, int pos)
{
const backend_info_t *info = be_get_info(node);
return info->out_infos[pos].req;
}
/**
* Sets the IN register requirements at position pos.
*/
......
......@@ -74,11 +74,6 @@ const arch_register_req_t **get_arm_in_req_all(const ir_node *node);
*/
const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos);
/**
* Returns the result register requirements of an arm node.
*/
const arch_register_req_t *get_arm_out_req(const ir_node *node, int pos);
/**
* Sets the IN register requirements at position pos.
*/
......
......@@ -123,7 +123,6 @@ static int arm_get_sp_bias(const ir_node *irn)
static const arch_irn_ops_t arm_irn_ops = {
get_arm_in_req,
get_arm_out_req,
arm_classify,
arm_get_frame_entity,
arm_set_frame_entity,
......
......@@ -46,7 +46,7 @@ typedef enum arch_irn_flags_t {
arch_irn_flags_none = 0, /**< Node flags. */
arch_irn_flags_dont_spill = 1U << 0, /**< This must not be spilled. */
arch_irn_flags_rematerializable = 1U << 1, /**< This can be replicated instead of spilled/reloaded. */
arch_irn_flags_modify_flags = 1U << 2 /**< I modify flags. */
arch_irn_flags_modify_flags = 1U << 2, /**< I modify flags. */
} arch_irn_flags_t;
typedef struct _be_lv_t be_lv_t;
......
......@@ -93,7 +93,7 @@ struct _be_abi_irg_t {
ir_node *init_sp; /**< The node representing the stack pointer
at the start of the function. */
ir_node *reg_params; /**< The reg params node. */
ir_node *start; /**< The be_Start params node. */
pmap *regs; /**< A map of all callee-save and ignore regs to
their Projs to the RegParams node. */
......@@ -1357,10 +1357,12 @@ static ir_node *create_barrier(be_abi_irg_t *env, ir_node *bl, ir_node **mem, pm
const arch_register_t *reg = rm[n].reg;
arch_register_type_t add_type = 0;
ir_node *proj;
const backend_info_t *info;
/* stupid workaround for now... as not all nodes report register
* requirements. */
if (!is_Phi(pred)) {
info = be_get_info(skip_Proj(pred));
if (info != NULL && info->out_infos != NULL) {
const arch_register_req_t *ireq = arch_get_register_req_out(pred);
if (ireq->type & arch_register_req_type_ignore)
add_type |= arch_register_req_type_ignore;
......@@ -1742,8 +1744,8 @@ static void fix_start_block(ir_graph *irg)
continue;
if (block != start_block) {
ir_node *jmp = new_r_Jmp(start_block);
set_Block_cfgpred(block, get_edge_src_pos(edge), jmp);
set_irg_initial_exec(irg, jmp);
return;
}
}
......@@ -1826,7 +1828,6 @@ static void modify_irg(be_abi_irg_t *env)
const arch_env_t *arch_env= env->birg->main_env->arch_env;
const arch_register_t *sp = arch_env->sp;
ir_graph *irg = env->birg->irg;
ir_node *start_bl;
ir_node *end;
ir_node *old_mem;
ir_node *new_mem_proj;
......@@ -1841,7 +1842,7 @@ static void modify_irg(be_abi_irg_t *env)
reg_node_map_t *rm;
const arch_register_t *fp_reg;
ir_node *frame_pointer;
ir_node *reg_params_bl;
ir_node *start_bl;
ir_node **args;
ir_node *arg_tuple;
const ir_edge_t *edge;
......@@ -1959,11 +1960,13 @@ static void modify_irg(be_abi_irg_t *env)
}
}
/* handle start block here (place a jump in the block) */
fix_start_block(irg);
pmap_insert(env->regs, (void *) sp, NULL);
pmap_insert(env->regs, (void *) arch_env->bp, NULL);
reg_params_bl = get_irg_start_block(irg);
env->reg_params = be_new_RegParams(reg_params_bl, pmap_count(env->regs));
add_irn_dep(env->reg_params, get_irg_start(irg));
start_bl = get_irg_start_block(irg);
env->start = be_new_Start(start_bl, pmap_count(env->regs) + 1);
/*
* make proj nodes for the callee save registers.
......@@ -1985,9 +1988,9 @@ static void modify_irg(be_abi_irg_t *env)
add_type |= arch_register_req_type_produces_sp | arch_register_req_type_ignore;
assert(nr >= 0);
proj = new_r_Proj(reg_params_bl, env->reg_params, mode, nr);
proj = new_r_Proj(start_bl, env->start, mode, nr + 1);
pmap_insert(env->regs, (void *) reg, proj);
be_set_constr_single_reg_out(env->reg_params, nr, reg, add_type);
be_set_constr_single_reg_out(env->start, nr + 1, reg, add_type);
arch_set_irn_register(proj, reg);
DBG((dbg, LEVEL_2, "\tregister save proj #%d -> reg %s\n", nr, reg->name));
......@@ -1996,10 +1999,10 @@ static void modify_irg(be_abi_irg_t *env)
/* create a new initial memory proj */
assert(is_Proj(old_mem));
new_mem_proj = new_r_Proj(get_nodes_block(old_mem),
new_r_Unknown(irg, mode_T), mode_M,
get_Proj_proj(old_mem));
arch_set_out_register_req(env->start, 0, arch_no_register_req);
new_mem_proj = new_r_Proj(start_bl, env->start, mode_M, 0);
mem = new_mem_proj;
set_irg_initial_mem(irg, mem);
/* Generate the Prologue */
fp_reg = call->cb->prologue(env->cb, &mem, env->regs, &env->frame.initial_bias);
......@@ -2007,7 +2010,6 @@ static void modify_irg(be_abi_irg_t *env)
/* do the stack allocation BEFORE the barrier, or spill code
might be added before it */
env->init_sp = be_abi_reg_map_get(env->regs, sp);
start_bl = get_irg_start_block(irg);
env->init_sp = be_new_IncSP(sp, start_bl, env->init_sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
be_abi_reg_map_set(env->regs, sp, env->init_sp);
......@@ -2021,7 +2023,6 @@ static void modify_irg(be_abi_irg_t *env)
pset_insert_ptr(env->ignore_regs, fp_reg);
/* rewire old mem users to new mem */
set_Proj_pred(new_mem_proj, get_Proj_pred(old_mem));
exchange(old_mem, mem);
set_irg_initial_mem(irg, mem);
......@@ -2044,18 +2045,18 @@ static void modify_irg(be_abi_irg_t *env)
if (arg->in_reg) {
repl = pmap_get(env->regs, (void *) arg->reg);
} else if (arg->on_stack) {
ir_node *addr = be_new_FrameAddr(sp->reg_class, reg_params_bl, frame_pointer, arg->stack_ent);
ir_node *addr = be_new_FrameAddr(sp->reg_class, start_bl, frame_pointer, arg->stack_ent);
/* For atomic parameters which are actually used, we create a Load node. */
if (is_atomic_type(param_type) && get_irn_n_edges(args[i]) > 0) {
ir_mode *mode = get_type_mode(param_type);
ir_mode *load_mode = arg->load_mode;
ir_node *load = new_r_Load(reg_params_bl, new_NoMem(), addr, load_mode, cons_floats);
repl = new_r_Proj(reg_params_bl, load, load_mode, pn_Load_res);
ir_node *load = new_r_Load(start_bl, new_NoMem(), addr, load_mode, cons_floats);
repl = new_r_Proj(start_bl, load, load_mode, pn_Load_res);
if (mode != load_mode) {
repl = new_r_Conv(reg_params_bl, repl, mode);
repl = new_r_Conv(start_bl, repl, mode);
}
} else {
/* The stack parameter is not primitive (it is a struct or array),
......@@ -2098,9 +2099,6 @@ static void modify_irg(be_abi_irg_t *env)
the code is dead and will never be executed. */
obstack_free(&env->obst, args);
/* handle start block here (place a jump in the block) */
fix_start_block(irg);
}
/** Fix the state inputs of calls that still hang on unknowns */
......@@ -2453,10 +2451,15 @@ typedef struct fix_stack_walker_env_t {
*/
static void collect_stack_nodes_walker(ir_node *node, void *data)
{
ir_node *insn = node;
fix_stack_walker_env_t *env = data;
const arch_register_req_t *req;
if (get_irn_mode(node) == mode_T)
if (is_Proj(node)) {
insn = get_Proj_pred(node);
}
if (arch_irn_get_n_outs(insn) == 0)
return;
req = arch_get_register_req_out(node);
......
......@@ -71,17 +71,16 @@ static inline const arch_irn_ops_t *get_irn_ops(const ir_node *irn)
const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos)
{
const arch_irn_ops_t *ops;
if (is_Proj(irn)) {
assert(pos == -1);
pos = -1-get_Proj_proj(irn);
irn = get_Proj_pred(irn);
}
ops = get_irn_ops_simple(irn);
if (pos < 0) {
return ops->get_irn_reg_req_out(irn, -pos-1);
return arch_get_out_register_req(irn, -pos-1);
} else {
const arch_irn_ops_t *ops = get_irn_ops_simple(irn);
return ops->get_irn_reg_req_in(irn, pos);
}
}
......
......@@ -368,16 +368,6 @@ struct arch_irn_ops_t {
*/
const arch_register_req_t *(*get_irn_reg_req_in)(const ir_node *irn, int pos);
/**
* Get the register requirements for values produced by a node
* @param irn The node.
* @param pos The operand's position (0 for most nodes,
* 0..n for mode_T nodes)
* @return The register requirements for the selected operand.
* The pointer returned is never NULL.
*/
const arch_register_req_t *(*get_irn_reg_req_out)(const ir_node *irn, int pos);
/**
* Classify the node.
* @param irn The node.
......@@ -748,16 +738,20 @@ static inline const arch_register_req_t *arch_get_register_req_out(
const ir_node *irn)
{
int pos = 0;
const arch_irn_ops_t *ops;
backend_info_t *info;
if (is_Proj(irn)) {
pos = get_Proj_proj(irn);
irn = get_Proj_pred(irn);
} else if (get_irn_mode(irn) == mode_T) {
/* TODO: find out who does this and fix the caller! */
return arch_no_register_req;
}
ops = get_irn_ops_simple(irn);
return ops->get_irn_reg_req_out(irn, pos);
info = be_get_info(irn);
if (info->out_infos == NULL)
return arch_no_register_req;
return info->out_infos[pos].req;
}
static inline bool arch_irn_is_ignore(const ir_node *irn)
......@@ -791,8 +785,18 @@ static inline const arch_register_req_t *arch_get_in_register_req(
static inline const arch_register_req_t *arch_get_out_register_req(
const ir_node *node, int pos)
{
const arch_irn_ops_t *ops = get_irn_ops_simple(node);
return ops->get_irn_reg_req_out(node, pos);
const backend_info_t *info = be_get_info(node);
if (info->out_infos == NULL)
return arch_no_register_req;
return info->out_infos[pos].req;
}
static inline void arch_set_out_register_req(ir_node *node, int pos,
const arch_register_req_t *req)
{
backend_info_t *info = be_get_info(node);
assert(pos < (int) arch_irn_get_n_outs(node));
info->out_infos[pos].req = req;
}
#endif /* FIRM_BE_BEARCH_H */
#endif
......@@ -833,7 +833,7 @@ static void apply_solution(be_ilpsched_env_t *env, lpp_t *lpp, ir_node *block) {
case iro_Phi:
add_to_sched(env, block, irn, 0);
break;
case iro_Start:
case beo_Start:
case iro_End:
case iro_Proj:
case iro_Bad:
......@@ -1672,7 +1672,7 @@ static void create_branch_constraint(be_ilpsched_env_t *env, lpp_t *lpp, be_ilps
foreach_linked_irns(ba->head_ilp_nodes, cur_irn) {
switch (get_irn_opcode(cur_irn)) {
case iro_Phi:
case iro_Start:
case beo_Start:
case iro_End:
case iro_Proj:
case iro_Bad:
......
......@@ -40,21 +40,26 @@ void be_info_new_node(ir_node *node)
struct obstack *obst;
backend_info_t *info;
if (is_Anchor(node))
return;
if (is_Proj(node)) // Projs need no be info, their tuple holds all information
/* Projs need no be info, their tuple holds all information */
if (is_Proj(node))
return;
obst = be_get_birg_obst(current_ir_graph);
info = OALLOCZ(obst, backend_info_t);
if (is_Phi(node)) {
assert(node->backend_info == NULL);
node->backend_info = info;
/* Hack! We still have middle end nodes in the backend (which was probably
a bad decision back then), which have no register constraints.
Set some none_requirements here.
*/
if (get_irn_mode(node) != mode_T
&& get_irn_opcode(node) <= iro_Last) {
info->out_infos = NEW_ARR_D(reg_out_info_t, obst, 1);
memset(info->out_infos, 0, 1 * sizeof(info->out_infos[0]));
info->out_infos[0].req = arch_no_register_req;
}
assert(node->backend_info == NULL);
node->backend_info = info;
}
static void new_Phi_copy_attr(const ir_node *old_node, ir_node *new_node)
......
......@@ -64,7 +64,7 @@
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL);
#define BE_SCHED_NODE(irn) (be_is_Keep(irn) || be_is_CopyKeep(irn) || be_is_RegParams(irn))
#define BE_SCHED_NODE(irn) (be_is_Keep(irn) || be_is_CopyKeep(irn) || be_is_Start(irn))
enum {
BE_SCHED_SELECT_TRIVIAL,
......
......@@ -120,7 +120,7 @@ ir_op *op_be_Return;
ir_op *op_be_IncSP;
ir_op *op_be_AddSP;
ir_op *op_be_SubSP;
ir_op *op_be_RegParams;
ir_op *op_be_Start;
ir_op *op_be_FrameAddr;
ir_op *op_be_Barrier;
......@@ -328,15 +328,16 @@ ir_node *be_new_Spill(const arch_register_class_t *cls,
be_node_set_reg_class_in(res, be_pos_Spill_frame, cls_frame);
be_node_set_reg_class_in(res, be_pos_Spill_val, cls);
/*
* For spills and reloads, we return "none" as requirement for frame
* pointer, so every input is ok. Some backends need this (e.g. STA).
* pointer, so every input is ok. Some backends need this (STA).
* Matze: we should investigate if this is really needed, this solution
* looks very hacky to me
*/
be_set_constr_in(res, be_pos_Spill_frame, arch_no_register_req);
arch_set_out_register_req(res, 0, arch_no_register_req);
return res;
}
......@@ -352,8 +353,9 @@ ir_node *be_new_Reload(const arch_register_class_t *cls,
in[1] = mem;
res = new_ir_node(NULL, irg, block, op_be_Reload, mode, 2, in);
init_node_attr(res, 2, 2);
init_node_attr(res, 2, 1);
be_node_set_reg_class_out(res, 0, cls);
be_node_set_reg_class_in(res, be_pos_Reload_frame, cls_frame);
arch_irn_set_flags(res, arch_irn_flags_rematerializable);
......@@ -717,13 +719,13 @@ ir_node *be_new_SubSP(const arch_register_t *sp, ir_node *bl, ir_node *old_sp, i
return irn;
}
ir_node *be_new_RegParams(ir_node *bl, int n_outs)
ir_node *be_new_Start(ir_node *bl, int n_outs)
{
ir_node *res;
int i;
ir_graph *irg = get_Block_irg(bl);
res = new_ir_node(NULL, irg, bl, op_be_RegParams, mode_T, 0, NULL);
res = new_ir_node(NULL, irg, bl, op_be_Start, mode_T, 0, NULL);
init_node_attr(res, 0, -1);
for (i = 0; i < n_outs; ++i) {
add_register_req_out(res);
......@@ -1037,14 +1039,6 @@ ir_node *be_reload(const arch_register_class_t *cls, ir_node *insert, ir_mode *m
*/
static const arch_register_req_t *be_node_get_out_reg_req(
const ir_node *irn, int pos)
{
const backend_info_t *info = be_get_info(irn);
assert(pos < ARR_LEN(info->out_infos));
return info->out_infos[pos].req;
}
static const arch_register_req_t *be_node_get_in_reg_req(
const ir_node *irn, int pos)
{
......@@ -1116,7 +1110,6 @@ static int be_node_get_sp_bias(const ir_node *irn)
/* for be nodes */
static const arch_irn_ops_t be_node_irn_ops = {
be_node_get_in_reg_req,
be_node_get_out_reg_req,
be_node_classify,
be_node_get_frame_entity,
be_node_set_frame_entity,
......@@ -1170,7 +1163,6 @@ static int dummy_get_sp_bias(const ir_node *node)
/* for "middleend" nodes */
static const arch_irn_ops_t dummy_be_irn_ops = {
dummy_reg_req,
dummy_reg_req,
dummy_classify,
dummy_get_frame_entity,
......@@ -1192,6 +1184,25 @@ static const arch_irn_ops_t dummy_be_irn_ops = {
*/
ir_node *be_new_Phi(ir_node *block, int n_ins, ir_node **ins, ir_mode *mode,
const arch_register_class_t *cls)
{
struct obstack *obst = be_get_birg_obst(get_irn_irg(block));
backend_info_t *info;
ir_node *phi = new_r_Phi(block, n_ins, ins, mode);
info = be_get_info(phi);
info->out_infos = NEW_ARR_D(reg_out_info_t, obst, 1);
memset(info->out_infos, 0, 1 * sizeof(info->out_infos[0]));
if (cls == NULL) {
info->out_infos[0].req = arch_no_register_req;
} else {
info->out_infos[0].req = cls->class_req;
}
return phi;
}
/**
* Guess correct register class of a phi node by looking at its arguments
*/
......@@ -1295,7 +1306,6 @@ int be_dump_phi_reg_reqs(ir_node *node, FILE *F, dump_reason_t reason)
}
static const arch_irn_ops_t phi_irn_ops = {
phi_get_irn_reg_req,
phi_get_irn_reg_req,
dummy_classify,
dummy_get_frame_entity,
......@@ -1431,8 +1441,7 @@ static void copy_attr(const ir_node *old_node, ir_node *new_node)
if (old_info->out_infos != NULL) {
unsigned n_outs = ARR_LEN(old_info->out_infos);
/* need dyanmic out infos? */
if (be_is_RegParams(new_node) || be_is_Barrier(new_node)
|| be_is_Perm(new_node)) {
if (be_is_Barrier(new_node) || be_is_Perm(new_node)) {
new_info->out_infos = NEW_ARR_F(reg_out_info_t, n_outs);
} else {
new_info->out_infos = NEW_ARR_D(reg_out_info_t, obst, n_outs);
......@@ -1502,7 +1511,7 @@ void be_init_op(void)
op_be_AddSP = new_ir_op(beo_AddSP, "be_AddSP", op_pin_state_pinned, N, oparity_unary, 0, sizeof(be_node_attr_t), &be_node_op_ops);
op_be_SubSP = new_ir_op(beo_SubSP, "be_SubSP", op_pin_state_pinned, N, oparity_unary, 0, sizeof(be_node_attr_t), &be_node_op_ops);
op_be_IncSP = new_ir_op(beo_IncSP, "be_IncSP", op_pin_state_pinned, N, oparity_unary, 0, sizeof(be_incsp_attr_t), &be_node_op_ops);
op_be_RegParams = new_ir_op(beo_RegParams, "be_RegParams", op_pin_state_pinned, N, oparity_zero, 0, sizeof(be_node_attr_t), &be_node_op_ops);
op_be_Start = new_ir_op(beo_Start, "be_Start", op_pin_state_pinned, N, oparity_zero, 0, sizeof(be_node_attr_t), &be_node_op_ops);
op_be_FrameAddr = new_ir_op(beo_FrameAddr, "be_FrameAddr", op_pin_state_floats, N, oparity_unary, 0, sizeof(be_frame_attr_t), &be_node_op_ops);
op_be_Barrier = new_ir_op(beo_Barrier, "be_Barrier", op_pin_state_pinned, N, oparity_dynamic, 0, sizeof(be_node_attr_t), &be_node_op_ops);
......@@ -1518,7 +1527,7 @@ void be_init_op(void)
op_be_AddSP->ops.node_cmp_attr = node_cmp_attr;
op_be_SubSP->ops.node_cmp_attr = node_cmp_attr;
op_be_IncSP->ops.node_cmp_attr = IncSP_cmp_attr;
op_be_RegParams->ops.node_cmp_attr = node_cmp_attr;
op_be_Start->ops.node_cmp_attr = node_cmp_attr;
op_be_FrameAddr->ops.node_cmp_attr = FrameAddr_cmp_attr;
op_be_Barrier->ops.node_cmp_attr = node_cmp_attr;
......
......@@ -53,7 +53,7 @@ extern ir_op *op_be_Return;
extern ir_op *op_be_IncSP;
extern ir_op *op_be_AddSP;
extern ir_op *op_be_SubSP;
extern ir_op *op_be_RegParams;
extern ir_op *op_be_Start;
extern ir_op *op_be_FrameAddr;
extern ir_op *op_be_Barrier;
......@@ -346,7 +346,7 @@ void be_Return_set_emit_pop(ir_node *ret, int emit_pop);
/** appends a node to the return node, returns the position of the node */
int be_Return_append_node(ir_node *ret, ir_node *node);
ir_node *be_new_RegParams(ir_node *bl, int n_out);
ir_node *be_new_Start(ir_node *block, int n_out);
ir_node *be_new_Barrier(ir_node *bl, int n, ir_node *in[]);
......@@ -454,6 +454,12 @@ void be_set_phi_reg_req(ir_node *phi, const arch_register_req_t *req);