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Zwinkau
libfirm
Commits
48e0419d
Commit
48e0419d
authored
Sep 26, 2006
by
Christian Würdig
Browse files
set correct noreg register when assimilating loads
parent
63489594
Changes
3
Hide whitespace changes
Inline
Side-by-side
ir/be/ia32/bearch_ia32.c
View file @
48e0419d
...
...
@@ -73,6 +73,21 @@ ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
USE_SSE2
(
cg
)
?
&
ia32_xmm_regs
[
REG_XMM_NOREG
]
:
&
ia32_vfp_regs
[
REG_VFP_NOREG
]);
}
/**
* Returns gp_noreg or fp_noreg, depending in input requirements.
*/
ir_node
*
ia32_get_admissible_noreg
(
ia32_code_gen_t
*
cg
,
ir_node
*
irn
,
int
pos
)
{
arch_register_req_t
req
;
const
arch_register_req_t
*
p_req
;
p_req
=
arch_get_register_req
(
cg
->
arch_env
,
&
req
,
irn
,
pos
);
assert
(
p_req
&&
"Missing register requirements"
);
if
(
p_req
->
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
])
return
ia32_new_NoReg_gp
(
cg
);
else
return
ia32_new_NoReg_fp
(
cg
);
}
/**************************************************
* _ _ _ __
* | | | (_)/ _|
...
...
@@ -744,6 +759,9 @@ static int ia32_possible_memory_operand(const void *self, const ir_node *irn, un
}
static
void
ia32_perform_memory_operand
(
const
void
*
self
,
ir_node
*
irn
,
ir_node
*
spill
,
unsigned
int
i
)
{
const
ia32_irn_ops_t
*
ops
=
self
;
ia32_code_gen_t
*
cg
=
ops
->
cg
;
assert
(
ia32_possible_memory_operand
(
self
,
irn
,
i
)
&&
"Cannot perform memory operand change"
);
if
(
i
==
2
)
{
...
...
@@ -756,8 +774,6 @@ static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node
set_ia32_op_type
(
irn
,
ia32_AddrModeS
);
set_ia32_am_flavour
(
irn
,
ia32_B
);
set_ia32_ls_mode
(
irn
,
get_irn_mode
(
get_irn_n
(
irn
,
i
)));
//TODO this will fail, if spill is a PhiM (give PhiMs entities?)
set_ia32_frame_ent
(
irn
,
be_get_frame_entity
(
spill
));
set_ia32_use_frame
(
irn
);
set_ia32_got_reload
(
irn
);
...
...
@@ -769,7 +785,7 @@ static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node
We would need cg object to get a real noreg, but we cannot
access it from here.
*/
set_irn_n
(
irn
,
3
,
get_irn_n
(
irn
,
1
));
set_irn_n
(
irn
,
3
,
ia32_get_admissible_noreg
(
cg
,
irn
,
3
));
//FIXME DBG_OPT_AM_S(reload, irn);
}
...
...
ir/be/ia32/bearch_ia32_t.h
View file @
48e0419d
...
...
@@ -163,6 +163,11 @@ ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
*/
ir_node
*
ia32_new_NoReg_fp
(
ia32_code_gen_t
*
cg
);
/**
* Returns gp_noreg or fp_noreg, depending on input requirements.
*/
ir_node
*
ia32_get_admissible_noreg
(
ia32_code_gen_t
*
cg
,
ir_node
*
irn
,
int
pos
);
/**
* Maps all intrinsic calls that the backend support
* and map all instructions the backend did not support
...
...
ir/be/ia32/ia32_optimize.c
View file @
48e0419d
...
...
@@ -1491,7 +1491,6 @@ static void optimize_lea(ir_node *irn, void *env) {
}
}
/**
* Checks for address mode patterns and performs the
* necessary transformations.
...
...
@@ -1501,8 +1500,7 @@ static void optimize_am(ir_node *irn, void *env) {
ia32_am_opt_env_t
*
am_opt_env
=
env
;
ia32_code_gen_t
*
cg
=
am_opt_env
->
cg
;
heights_t
*
h
=
am_opt_env
->
h
;
ir_node
*
block
,
*
noreg_gp
,
*
noreg_fp
;
ir_node
*
left
,
*
right
;
ir_node
*
block
,
*
left
,
*
right
;
ir_node
*
store
,
*
load
,
*
mem_proj
;
ir_node
*
succ
,
*
addr_b
,
*
addr_i
;
int
check_am_src
=
0
;
...
...
@@ -1512,9 +1510,7 @@ static void optimize_am(ir_node *irn, void *env) {
if
(
!
is_ia32_irn
(
irn
)
||
is_ia32_Ld
(
irn
)
||
is_ia32_St
(
irn
)
||
is_ia32_Store8Bit
(
irn
))
return
;
block
=
get_nodes_block
(
irn
);
noreg_gp
=
ia32_new_NoReg_gp
(
cg
);
noreg_fp
=
ia32_new_NoReg_fp
(
cg
);
block
=
get_nodes_block
(
irn
);
DBG
((
mod
,
LEVEL_1
,
"checking for AM
\n
"
));
...
...
@@ -1641,12 +1637,12 @@ static void optimize_am(ir_node *irn, void *env) {
if
(
get_irn_arity
(
irn
)
==
5
)
{
/* binary AMop */
set_irn_n
(
irn
,
4
,
get_irn_n
(
load
,
2
));
set_irn_n
(
irn
,
2
,
noreg_gp
);
set_irn_n
(
irn
,
2
,
ia32_get_admissible_noreg
(
cg
,
irn
,
2
)
);
}
else
{
/* unary AMop */
set_irn_n
(
irn
,
3
,
get_irn_n
(
load
,
2
));
set_irn_n
(
irn
,
2
,
noreg_gp
);
set_irn_n
(
irn
,
2
,
ia32_get_admissible_noreg
(
cg
,
irn
,
2
)
);
}
/* connect the memory Proj of the Store to the op */
...
...
@@ -1739,7 +1735,7 @@ static void optimize_am(ir_node *irn, void *env) {
set_ia32_pncode
(
irn
,
get_inversed_pnc
(
get_ia32_pncode
(
irn
)));
/* disconnect from Load */
set_irn_n
(
irn
,
3
,
noreg_gp
);
set_irn_n
(
irn
,
3
,
ia32_get_admissible_noreg
(
cg
,
irn
,
3
)
);
DBG_OPT_AM_S
(
right
,
irn
);
...
...
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