Commit 4b335fcf authored by Michael Beck's avatar Michael Beck
Browse files

- fixed architecture flags

[r20160]
parent f1e5de9e
......@@ -63,15 +63,25 @@ enum cpu_arch_features {
arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
arch_feature_mmx = 0x00004000, /**< MMX instructions */
arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
arch_feature_sse1 = 0x00010000 | arch_feature_mmx, /**< SSE1 instructions, include MMX */
arch_feature_sse2 = 0x00020000 | arch_feature_sse1, /**< SSE2 instructions, include SSE1 */
arch_feature_sse3 = 0x00040000 | arch_feature_sse2, /**< SSE3 instructions, include SSE2 */
arch_feature_ssse3 = 0x00080000 | arch_feature_sse3, /**< SSSE3 instructions, include SSE3 */
arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
arch_feature_3DNowE = 0x00200000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
arch_feature_64bit = 0x00400000 | arch_feature_sse2, /**< x86_64 support, includes SSE2 */
arch_feature_mmx = 0x00004000, /**< MMX instructions */
arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
arch_feature_64bit = 0x00400000, /**< x86_64 support */
arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
};
#define FLAGS(x, f) (((x) & (f)) != 0)
......@@ -86,31 +96,31 @@ enum cpu_support {
cpu_i386 = arch_i386,
cpu_i486 = arch_i486,
cpu_pentium = arch_pentium,
cpu_pentium_mmx = arch_pentium | arch_feature_mmx,
cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_feature_mmx,
cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_feature_sse1,
cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_feature_sse2,
cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_feature_sse2,
cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_feature_sse3,
cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_feature_64bit | arch_feature_sse3,
cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_feature_64bit | arch_feature_ssse3,
cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
/* AMD CPU's */
cpu_k6 = arch_k6 | arch_feature_mmx,
cpu_k6_PLUS = arch_k6 | arch_feature_mmx | arch_feature_3DNow,
cpu_geode = arch_geode | arch_feature_sse1 | arch_feature_3DNowE,
cpu_athlon = arch_athlon | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6_insn,
cpu_athlon64 = arch_athlon | arch_feature_sse2 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
cpu_k8 = arch_k8 | arch_feature_sse2 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
cpu_k8_sse3 = arch_k8 | arch_feature_sse3 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
cpu_k10 = arch_k10 | arch_feature_sse3 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
cpu_k6 = arch_k6 | arch_mmx_insn,
cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
/* other CPU's */
cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
cpu_c3_2 = arch_ppro | arch_feature_sse1, /* really no 3DNow! */
cpu_c3_2 = arch_ppro | arch_sse1_insn, /* really no 3DNow! */
};
static int opt_size = 0;
......@@ -484,7 +494,7 @@ void ia32_setup_cg_config(void)
/* P4s don't like inc/decs because they only partially write the flags
register which produces false dependencies */
ia32_cg_config.use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
ia32_cg_config.use_sse2 = use_sse2;
ia32_cg_config.use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
ia32_cg_config.use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
ia32_cg_config.use_ftst = !FLAGS(arch, arch_feature_p6_insn);
ia32_cg_config.use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment