be: Rename reg_class of struct arch_register_t to cls.

All other structs holding a register class call it cls, too.

ir/be/amd64/amd64_emitter.c

@@ -164,7 +164,7 @@ static void emit_register_insn_mode(const arch_register_t *reg,
 static void emit_register_mode(const arch_register_t *reg,
                                amd64_insn_mode_t insn_mode)
 {
-	if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_xmm]) {
+	if (reg->cls == &amd64_reg_classes[CLASS_amd64_xmm]) {
 		emit_register(reg);
 	} else {
 		emit_register_insn_mode(reg, insn_mode);
@@ -694,16 +694,16 @@ static void emit_be_Perm(const ir_node *node)
 	arch_register_t const *const reg0 = arch_get_irn_register_out(node, 0);
 	arch_register_t const *const reg1 = arch_get_irn_register_out(node, 1);
 
-	arch_register_class_t const* const cls0 = reg0->reg_class;
-	assert(cls0 == reg1->reg_class && "Register class mismatch at Perm");
+	arch_register_class_t const* const cls = reg0->cls;
+	assert(cls == reg1->cls && "Register class mismatch at Perm");
 
-	if (cls0 == &amd64_reg_classes[CLASS_amd64_gp]) {
-	     amd64_emitf(node, "xchg %^R, %^R", reg0, reg1);
-     } else if (cls0 == &amd64_reg_classes[CLASS_amd64_xmm]) {
-          amd64_emitf(node, "pxor %^R, %^R", reg0, reg1);
-          amd64_emitf(node, "pxor %^R, %^R", reg1, reg0);
-          amd64_emitf(node, "pxor %^R, %^R", reg0, reg1);
-     } else {
+	if (cls == &amd64_reg_classes[CLASS_amd64_gp]) {
+		amd64_emitf(node, "xchg %^R, %^R", reg0, reg1);
+	} else if (cls == &amd64_reg_classes[CLASS_amd64_xmm]) {
+		amd64_emitf(node, "pxor %^R, %^R", reg0, reg1);
+		amd64_emitf(node, "pxor %^R, %^R", reg1, reg0);
+		amd64_emitf(node, "pxor %^R, %^R", reg0, reg1);
+	} else {
 		panic("unexpected register class in be_Perm (%+F)", node);
 	}
 }

ir/be/amd64/amd64_transform.c

@@ -1820,7 +1820,7 @@ static ir_node *gen_Proj_Proj_Start(ir_node *node)
 	if (param->reg != NULL) {
 		/* argument transmitted in register */
 		const arch_register_t *reg    = param->reg;
-		ir_mode               *mode   = reg->reg_class->mode;
+		ir_mode               *mode   = reg->cls->mode;
 		unsigned               new_pn = param->reg_offset + start_params_offset;
 		ir_node               *value  = new_r_Proj(new_start, mode, new_pn);
 		return value;

ir/be/amd64/bearch_amd64.c

@@ -196,7 +196,7 @@ static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_e
 static ir_node* create_spproj(ir_node *pred, int pos)
 {
 	const arch_register_t *spreg = &amd64_registers[REG_RSP];
-	ir_mode               *spmode = spreg->reg_class->mode;
+	ir_mode               *spmode = spreg->cls->mode;
 	ir_node               *sp     = new_r_Proj(pred, spmode, pos);
 	arch_set_irn_register(sp, spreg);
 	return sp;

ir/be/arm/arm_cconv.c

@@ -92,7 +92,7 @@ calling_convention_t *arm_decide_calling_convention(const ir_graph *irg,
 				const arch_register_t *reg = param_regs[regnum++];
 				param->reg1 = reg;
 			} else {
-				ir_mode *pmode = param_regs[0]->reg_class->mode;
+				ir_mode *pmode = param_regs[0]->cls->mode;
 				ir_type *type  = get_type_for_mode(pmode);
 				param->type    = type;
 				param->offset  = stack_offset;

ir/be/arm/arm_transform.c

@@ -1557,7 +1557,7 @@ static ir_node *gen_Proj_Proj_Start(ir_node *node)
 	const arch_register_t *reg0 = param->reg0;
 	if (reg0 != NULL) {
 		/* argument transmitted in register */
-		ir_mode *mode   = reg0->reg_class->mode;
+		ir_mode *mode   = reg0->cls->mode;
 		unsigned new_pn = param->reg_offset + start_params_offset;
 		ir_node *value  = new_r_Proj(new_start, mode, new_pn);
 
@@ -1636,7 +1636,7 @@ static ir_node *gen_Proj_Proj_Call(ir_node *node)
 	if (regn < 0) {
 		panic("Internal error in calling convention for return %+F", node);
 	}
-	ir_mode *mode = res->reg0->reg_class->mode;
+	ir_mode *const mode = res->reg0->cls->mode;
 
 	arm_free_calling_convention(cconv);
 
@@ -1883,7 +1883,7 @@ static ir_node *gen_Return(ir_node *node)
 	ir_node *start = get_irg_start(irg);
 	for (unsigned i = 0; i < n_callee_saves; ++i) {
 		const arch_register_t *reg   = callee_saves[i];
-		ir_mode               *mode  = reg->reg_class->mode;
+		ir_mode               *mode  = reg->cls->mode;
 		unsigned               idx   = start_callee_saves_offset + i;
 		ir_node               *value = new_r_Proj(start, mode, idx);
 		in[p]   = value;

ir/be/bearch.c

@@ -130,7 +130,7 @@ bool arch_reg_is_allocatable(const arch_register_req_t *req,
                              const arch_register_t *reg)
 {
 	assert(req->type != arch_register_req_type_none);
-	if (req->cls != reg->reg_class)
+	if (req->cls != reg->cls)
 		return false;
 	if (reg->type & arch_register_type_virtual)
 		return true;

ir/be/bearch.h

@@ -207,7 +207,7 @@ void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
  */
 struct arch_register_t {
 	const char                  *name;         /**< The name of the register. */
-	const arch_register_class_t *reg_class;    /**< The class of the register */
+	arch_register_class_t const *cls;          /**< The class of the register */
 	/** register constraint allowing just this register */
 	const arch_register_req_t   *single_req;
 	arch_register_type_t         type;         /**< The type of the register. */

ir/be/belower.c

@@ -76,7 +76,7 @@ static void mark_live_nodes_registers(const ir_node *irn, lower_env_t *env)
 {
 	ir_node                     *block     = get_nodes_block(irn);
 	ir_graph                    *irg       = get_irn_irg(irn);
-	arch_register_class_t const *reg_class = arch_get_irn_register(get_irn_n(irn, 0))->reg_class;
+	arch_register_class_t const *cls       = arch_get_irn_register(get_irn_n(irn, 0))->cls;
 	arch_env_t const            *arch_env  = be_get_irg_arch_env(irg);
 	be_irg_t                    *birg      = be_birg_from_irg(irg);
 	unsigned                     n_regs    = arch_env->n_registers;
@@ -84,7 +84,7 @@ static void mark_live_nodes_registers(const ir_node *irn, lower_env_t *env)
 
 	be_lv_t *lv = be_get_irg_liveness(irg);
 	assert(lv->sets_valid && "Live sets are invalid");
-	be_lv_foreach_cls(lv, block, be_lv_state_end, reg_class, live) {
+	be_lv_foreach_cls(lv, block, be_lv_state_end, cls, live) {
 		set_reg_free(free_regs, live, false);
 	}
 
@@ -106,7 +106,7 @@ static arch_register_t const *get_free_register(ir_node *const perm, lower_env_t
 
 	ir_node                     *block     = get_nodes_block(perm);
 	ir_graph                    *irg       = get_irn_irg(perm);
-	arch_register_class_t const *reg_class = arch_get_irn_register(get_irn_n(perm, 0))->reg_class;
+	arch_register_class_t const *cls       = arch_get_irn_register(get_irn_n(perm, 0))->cls;
 	arch_env_t const            *arch_env  = be_get_irg_arch_env(irg);
 	unsigned                     n_regs    = arch_env->n_registers;
 	unsigned                    *free_regs = (unsigned*)ir_nodehashmap_get(arch_register_t const, &env->live_regs, perm);
@@ -138,7 +138,7 @@ static arch_register_t const *get_free_register(ir_node *const perm, lower_env_t
 
 	rbitset_foreach(free_regs, n_regs, free_idx) {
 		arch_register_t const *free_reg = &arch_env->registers[free_idx];
-		if (free_reg->reg_class != reg_class)
+		if (free_reg->cls != cls)
 			continue;
 
 		return free_reg;

ir/be/benode.c

@@ -214,7 +214,7 @@ ir_node *be_new_MemPerm(ir_node *const block, int n, ir_node *const *const in)
 	ir_node *irn = new_ir_node(NULL, irg, block, op_be_MemPerm, mode_T, n+1, real_in);
 
 	init_node_attr(irn, n + 1, n, arch_irn_flags_none);
-	be_node_set_reg_class_in(irn, 0, sp->reg_class);
+	be_node_set_reg_class_in(irn, 0, sp->cls);
 
 	be_memperm_attr_t *attr = (be_memperm_attr_t*)get_irn_generic_attr(irn);
 	attr->in_entities  = OALLOCNZ(get_irg_obstack(irg), ir_entity*, n);
@@ -284,8 +284,7 @@ ir_node *be_new_IncSP(const arch_register_t *sp, ir_node *bl,
 {
 	ir_graph *irg = get_irn_irg(bl);
 	ir_node  *in[] = { old_sp };
-	ir_node  *irn  = new_ir_node(NULL, irg, bl, op_be_IncSP, sp->reg_class->mode,
-	                             ARRAY_SIZE(in), in);
+	ir_node  *irn  = new_ir_node(NULL, irg, bl, op_be_IncSP, sp->cls->mode, ARRAY_SIZE(in), in);
 	init_node_attr(irn, 1, 1, arch_irn_flags_none);
 	be_incsp_attr_t *a    = (be_incsp_attr_t*)get_irn_generic_attr(irn);
 	a->offset             = offset;
@@ -293,7 +292,7 @@ ir_node *be_new_IncSP(const arch_register_t *sp, ir_node *bl,
 	a->base.exc.pin_state = op_pin_state_pinned;
 
 	/* Set output constraint to stack register. */
-	be_node_set_reg_class_in(irn, 0, sp->reg_class);
+	be_node_set_reg_class_in(irn, 0, sp->cls);
 	be_set_constr_single_reg_out(irn, 0, sp, arch_register_req_type_produces_sp);
 	return irn;
 }
@@ -389,7 +388,7 @@ unsigned be_get_MemPerm_entity_arity(const ir_node *irn)
 const arch_register_req_t *be_create_reg_req(struct obstack *obst,
 		const arch_register_t *reg, arch_register_req_type_t additional_types)
 {
-	const arch_register_class_t *cls     = reg->reg_class;
+	arch_register_class_t const *cls     = reg->cls;
 	unsigned                     n_regs  = arch_register_class_n_regs(cls);
 	unsigned                    *limited = rbitset_obstack_alloc(obst, n_regs);
 	rbitset_set(limited, reg->index);
@@ -517,7 +516,7 @@ static unsigned get_start_reg_index(ir_graph *irg, const arch_register_t *reg)
 		arch_register_req_t const *const out_req = arch_get_irn_register_req_out(start, i);
 		if (!arch_register_req_is(out_req, limited))
 			continue;
-		if (out_req->cls != reg->reg_class)
+		if (out_req->cls != reg->cls)
 			continue;
 		if (!rbitset_is_set(out_req->limited, reg->index))
 			continue;
@@ -530,7 +529,7 @@ ir_node *be_get_initial_reg_value(ir_graph *irg, const arch_register_t *reg)
 {
 	unsigned i     = get_start_reg_index(irg, reg);
 	ir_node *start = get_irg_start(irg);
-	ir_mode *mode  = arch_register_class_mode(reg->reg_class);
+	ir_mode *mode  = arch_register_class_mode(reg->cls);
 
 	ir_node *const proj = get_Proj_for_pn(start, i);
 	return proj ? proj : new_r_Proj(start, mode, i);

ir/be/bestate.c

@@ -269,7 +269,7 @@ static block_info_t *compute_block_start_state(minibelady_env_t *env,
 	}
 
 	/* check all Live-Ins */
-	be_lv_foreach_cls(env->lv, block, be_lv_state_in, env->reg->reg_class, node) {
+	be_lv_foreach_cls(env->lv, block, be_lv_state_in, env->reg->cls, node) {
 		if (arch_get_irn_register(node) != env->reg)
 			continue;
 

ir/be/ia32/ia32_common_transform.c

@@ -120,7 +120,7 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber)
 	for (size_t i = 0; i != N_IA32_REGISTERS; ++i) {
 		arch_register_t const *const reg = &ia32_registers[i];
 		if (strcmp(reg->name, clobber) == 0 ||
-		    (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp] && strcmp(reg->name + 1, clobber) == 0)) {
+		    (reg->cls == &ia32_reg_classes[CLASS_ia32_gp] && strcmp(reg->name + 1, clobber) == 0)) {
 			return reg;
 		}
 	}

ir/be/ia32/ia32_emitter.c

@@ -1181,7 +1181,7 @@ static void Copy_emitter(const ir_node *node, const ir_node *op)
 		return;
 
 	/* copies of fp nodes aren't real... */
-	if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
+	if (in->cls == &ia32_reg_classes[CLASS_ia32_fp])
 		return;
 
 	ia32_emitf(node, "movl %R, %R", in, out);
@@ -1205,16 +1205,16 @@ static void emit_be_Perm(const ir_node *node)
 	arch_register_t const *const reg0 = arch_get_irn_register_out(node, 0);
 	arch_register_t const *const reg1 = arch_get_irn_register_out(node, 1);
 
-	arch_register_class_t const *const cls0 = reg0->reg_class;
-	assert(cls0 == reg1->reg_class && "Register class mismatch at Perm");
+	arch_register_class_t const *const cls = reg0->cls;
+	assert(cls == reg1->cls && "Register class mismatch at Perm");
 
-	if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
+	if (cls == &ia32_reg_classes[CLASS_ia32_gp]) {
 		ia32_emitf(node, "xchg %R, %R", reg1, reg0);
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
+	} else if (cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
 		ia32_emitf(NULL, "xorpd %R, %R", reg1, reg0);
 		ia32_emitf(NULL, "xorpd %R, %R", reg0, reg1);
 		ia32_emitf(node, "xorpd %R, %R", reg1, reg0);
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
+	} else if (cls == &ia32_reg_classes[CLASS_ia32_fp]) {
 		/* is a NOP */
 	} else {
 		panic("unexpected register class in be_Perm (%+F)", node);
@@ -2000,10 +2000,10 @@ static void bemit_copy(const ir_node *copy)
 	if (in == out)
 		return;
 	/* copies of fp nodes aren't real... */
-	if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
+	if (in->cls == &ia32_reg_classes[CLASS_ia32_fp])
 		return;
 
-	assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
+	assert(in->cls == &ia32_reg_classes[CLASS_ia32_gp]);
 	bemit8(0x8B);
 	bemit_modrr(in, out);
 }
@@ -2012,11 +2012,11 @@ static void bemit_perm(const ir_node *node)
 {
 	arch_register_t       const *const reg0 = arch_get_irn_register_out(node, 0);
 	arch_register_t       const *const reg1 = arch_get_irn_register_out(node, 1);
-	arch_register_class_t const *const cls0 = reg0->reg_class;
+	arch_register_class_t const *const cls  = reg0->cls;
 
-	assert(cls0 == reg1->reg_class && "Register class mismatch at Perm");
+	assert(cls == reg1->cls && "Register class mismatch at Perm");
 
-	if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
+	if (cls == &ia32_reg_classes[CLASS_ia32_gp]) {
 		if (reg0->index == REG_GP_EAX) {
 			bemit8(0x90 + reg1->encoding);
 		} else if (reg1->index == REG_GP_EAX) {
@@ -2025,12 +2025,12 @@ static void bemit_perm(const ir_node *node)
 			bemit8(0x87);
 			bemit_modrr(reg0, reg1);
 		}
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
+	} else if (cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
 		panic("unimplemented"); // TODO implement
 		//ia32_emitf(NULL, "xorpd %R, %R", reg1, reg0);
 		//ia32_emitf(NULL, "xorpd %R, %R", reg0, reg1);
 		//ia32_emitf(node, "xorpd %R, %R", reg1, reg0);
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
+	} else if (cls == &ia32_reg_classes[CLASS_ia32_fp]) {
 		/* is a NOP */
 	} else {
 		panic("unexpected register class in be_Perm (%+F)", node);

ir/be/ia32/ia32_finish.c

@@ -242,7 +242,7 @@ static void assure_should_be_same_requirements(ir_node *node)
 		/* requirement already fulfilled? */
 		if (in_reg == out_reg)
 			continue;
-		assert(in_reg->reg_class == out_reg->reg_class);
+		assert(in_reg->cls == out_reg->cls);
 
 		/* check if any other input operands uses the out register */
 		ir_node *uses_out_reg     = NULL;

ir/be/ia32/ia32_optimize.c

@@ -488,7 +488,7 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn)
 		if (!is_ia32_Load(node)) {
 			if (be_is_Copy(node)) {
 				const arch_register_t *dreg = arch_get_irn_register(node);
-				if (dreg->reg_class != &ia32_reg_classes[CLASS_ia32_gp]) {
+				if (dreg->cls != &ia32_reg_classes[CLASS_ia32_gp]) {
 					/* not a GP copy, ignore */
 					continue;
 				}

ir/be/ia32/ia32_transform.c

@@ -4248,10 +4248,9 @@ static ir_node *gen_Proj_Proj_Start(ir_node *node)
 	/* stack paramter should have been lowered to loads already */
 	assert(param->reg != NULL);
 	/* argument transmitted in register */
-	const arch_register_t *reg    = param->reg;
-	ir_mode               *mode   = reg->reg_class->mode;
-	unsigned               new_pn = param->reg_offset + start_params_offset;
-	ir_node               *value  = new_r_Proj(new_start, mode, new_pn);
+	ir_mode *const mode   = param->reg->cls->mode;
+	unsigned const new_pn = param->reg_offset + start_params_offset;
+	ir_node *const value  = new_r_Proj(new_start, mode, new_pn);
 	return value;
 }
 

ir/be/ia32/ia32_x87.c

@@ -1081,7 +1081,7 @@ static void sim_Keep(x87_state *state, ir_node *node)
 
 	foreach_irn_in(node, i, op) {
 		const arch_register_t *op_reg = arch_get_irn_register(op);
-		if (op_reg->reg_class != &ia32_reg_classes[CLASS_ia32_fp])
+		if (op_reg->cls != &ia32_reg_classes[CLASS_ia32_fp])
 			continue;
 
 		unsigned    reg_id       = op_reg->index;

ir/be/scripts/generate_regalloc_if.pl

@@ -170,7 +170,7 @@ EOF
 		$regtypes_def .= <<EOF;
 	{
 		.name         = "${realname}",
-		.reg_class    = ${class_ptr},
+		.cls          = ${class_ptr},
 		.single_req   = &${arch}_single_reg_req_${old_classname}_${name},
 		.type         = ${type},
 		.index        = REG_${classuc}_${ucname},

ir/be/sparc/sparc_cconv.c

@@ -249,7 +249,7 @@ calling_convention_t *sparc_decide_calling_convention(ir_type *function_type,
 				param->req1       = reg->single_req;
 				++regnum;
 			} else {
-				ir_mode *regmode = param_regs[0]->reg_class->mode;
+				ir_mode *regmode = param_regs[0]->cls->mode;
 				ir_type *type    = get_type_for_mode(regmode);
 				param->type      = type;
 				param->offset    = stack_offset;

ir/be/sparc/sparc_finish.c

@@ -76,7 +76,7 @@ static void assure_should_be_same_requirements(ir_node *node)
 		/* requirement already fulfilled? */
 		if (in_reg == out_reg)
 			continue;
-		assert(in_reg->reg_class == out_reg->reg_class);
+		assert(in_reg->cls == out_reg->cls);
 
 		/* check if any other input operands uses the out register */
 		ir_node *uses_out_reg     = NULL;

ir/be/sparc/sparc_transform.c

@@ -1900,7 +1900,7 @@ static ir_node *gen_Return(ir_node *node)
 		size_t    n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
 		for (size_t i = 0; i < n_callee_saves; ++i) {
 			const arch_register_t *reg   = omit_fp_callee_saves[i];
-			ir_mode               *mode  = reg->reg_class->mode;
+			ir_mode               *mode  = reg->cls->mode;
 			ir_node               *value
 					= new_r_Proj(start, mode, i + start_callee_saves_offset);
 			in[p]   = value;
@@ -2629,7 +2629,7 @@ static ir_node *gen_Proj_Proj_Start(ir_node *node)
 	if (param->reg0 != NULL) {
 		/* argument transmitted in register */
 		const arch_register_t *reg      = param->reg0;
-		ir_mode               *reg_mode = reg->reg_class->mode;
+		ir_mode               *reg_mode = reg->cls->mode;
 		unsigned               new_pn   = param->reg_offset + start_params_offset;
 		ir_node               *value    = new_r_Proj(new_start, reg_mode, new_pn);
 		bool                   is_float = false;
@@ -2647,7 +2647,7 @@ static ir_node *gen_Proj_Proj_Start(ir_node *node)
 			ir_node *value1 = NULL;
 
 			if (reg1 != NULL) {
-				ir_mode *reg1_mode = reg1->reg_class->mode;
+				ir_mode *const reg1_mode = reg1->cls->mode;
 				value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
 			} else if (param->entity != NULL) {
 				ir_node *fp  = get_initial_fp(irg);