Commit 5c18ac70 authored by Matthias Braun's avatar Matthias Braun
Browse files

let backends announce whether they support unaligned memaccesses

This also disables the memcombine optimisation if unaligned stores are
not supported by the backend.
We may add some tests in the future to reenable this in cases where we
can prove that the combined store is aligned.
parent af21a773
......@@ -102,6 +102,9 @@ typedef struct backend_params {
unsigned byte_order_big_endian:1;
/** 1 if backend supports generation of position independent code (PIC) */
unsigned pic_supported:1;
/** unaligned memory accesses are not supported natively (but the backend
* may break the access up into several smaller ones) */
unsigned unaligned_memaccess_supported:1;
/**
* Shifts on this architecture only read some bits of the shift value.
......
......@@ -247,8 +247,9 @@ static int TEMPLATE_is_mux_allowed(ir_node *sel, ir_node *mux_false,
static const backend_params *TEMPLATE_get_backend_params(void)
{
static backend_params p = {
0, /* 0: little-endian, 1: big-endian */
0, /* PIC code supported */
false, /* false: little-endian, true: big-endian */
false, /* PIC code supported */
false, /* unaligned memory access supported */
32, /* modulo_shift */
NULL, /* architecture dependent settings, will be set later */
TEMPLATE_is_mux_allowed, /* parameter for if conversion */
......
......@@ -546,8 +546,9 @@ static const ir_settings_arch_dep_t amd64_arch_dep = {
*/
static const backend_params *amd64_get_backend_params(void) {
static backend_params p = {
0, /* little endian */
0, /* PIC code not supported */
false, /* little endian */
false, /* PIC code not supported */
true, /* unaligned memory */
32, /* modulo shift */
&amd64_arch_dep,
amd64_is_mux_allowed, /* parameter for if conversion */
......
......@@ -415,8 +415,9 @@ static const backend_params *arm_get_libfirm_params(void)
32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
1, /* big endian */
0, /* PIC code not supported */
true, /* big endian */
false, /* PIC code not supported */
false, /* unaligned memory access */
32, /* modulo shift */
&ad, /* will be set later */
arm_is_mux_allowed, /* allow_ifconv function */
......
......@@ -1404,8 +1404,9 @@ static const ir_settings_arch_dep_t ia32_arch_dep = {
32, /* Mulh allowed up to 32 bit */
};
static backend_params ia32_backend_params = {
0, /* little endian */
1, /* PIC code supported */
false, /* little endian */
true, /* PIC code supported */
true, /* unaligned memory access */
32, /* modulo shift */
&ia32_arch_dep, /* will be set later */
ia32_is_mux_allowed,
......
......@@ -561,8 +561,9 @@ static const backend_params *sparc_get_backend_params(void)
32, /* max_bits_for_mulh */
};
static backend_params p = {
1, /* big endian */
0, /* PIC code supported */
true, /* big endian */
false, /* PIC code supported */
false, /* unaligned memory access */
32, /* modulo shift */
&arch_dep, /* will be set later */
sparc_is_mux_allowed, /* parameter for if conversion */
......
......@@ -2173,6 +2173,12 @@ again:;
void combine_memops(ir_graph *irg)
{
/* We don't have code yet to test whether the address is aligned for the
* combined modes, so we can only do this if the backend supports unaligned
* stores. */
if (!be_get_backend_param()->unaligned_memaccess_supported)
return;
irg_walk_graph(irg, combine_memop, NULL, NULL);
}
......
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