added new option ia32-nopushargs

ir/be/ia32/bearch_ia32.c

@@ -1430,12 +1430,13 @@ static ia32_isa_t ia32_isa_template = {
 	NULL,                    /* types */
 	NULL,                    /* tv_ents */
 	(0                 |
-	IA32_OPT_INCDEC    |     /* optimize add 1, sub 1 into inc/dec               default: on  */
-	IA32_OPT_DOAM      |     /* optimize address mode                            default: on  */
-	IA32_OPT_LEA       |     /* optimize for LEAs                                default: on  */
-	IA32_OPT_PLACECNST |     /* place constants immediately before instructions, default: on  */
-	IA32_OPT_IMMOPS    |     /* operations can use immediates,                   default: on  */
-	IA32_OPT_EXTBB),         /* use extended basic block scheduling,             default: on  */
+	IA32_OPT_INCDEC    |     /* optimize add 1, sub 1 into inc/dec               default: on */
+	IA32_OPT_DOAM      |     /* optimize address mode                            default: on */
+	IA32_OPT_LEA       |     /* optimize for LEAs                                default: on */
+	IA32_OPT_PLACECNST |     /* place constants immediately before instructions, default: on */
+	IA32_OPT_IMMOPS    |     /* operations can use immediates,                   default: on */
+	IA32_OPT_EXTBB     |     /* use extended basic block scheduling,             default: on */
+	IA32_OPT_PUSHARGS),      /* create pushs for function argument passing,      default: on */
 	arch_pentium_4,          /* instruction architecture */
 	arch_pentium_4,          /* optimize for architecture */
 	fp_sse2,                 /* use sse2 unit */
@@ -1730,7 +1731,13 @@ static int ia32_get_reg_class_alignment(const void *self, const arch_register_cl
 	return bytes;
 }
 
-static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
+static ia32_intrinsic_env_t intrinsic_env = {
+	NULL,    /**< the irg, these entities belong to */
+	NULL,    /**< entity for first div operand (move into FPU) */
+	NULL,    /**< entity for second div operand (move into FPU) */
+	NULL,    /**< entity for converts ll -> d */
+	NULL,    /**< entity for converts d -> ll */
+};
 
 /**
  * Returns the libFirm configuration parameter for this backend.
@@ -1820,6 +1827,7 @@ static const lc_opt_table_entry_t ia32_options[] = {
 	LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
 	LC_OPT_ENT_NEGBIT("noimmop",     "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
 	LC_OPT_ENT_NEGBIT("noextbb",     "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
+	LC_OPT_ENT_NEGBIT("nopushargs",  "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
 	LC_OPT_ENT_ENUM_INT("gasmode",   "set the GAS compatibility mode", &gas_var),
 	{ NULL }
 };
@@ -1838,6 +1846,7 @@ static const lc_opt_table_entry_t ia32_options[] = {
  * ia32-noplacecnst  do not place constants,
  * ia32-noimmop      no operations with immediates
  * ia32-noextbb      do not use extended basic block scheduling
+ * ia32-nopushargs   do not create pushs for function argument passing
  * ia32-gasmode      set the GAS compatibility mode
  */
 static void ia32_register_options(lc_opt_entry_t *ent)

ir/be/ia32/bearch_ia32_t.h

@@ -28,6 +28,7 @@ typedef enum _ia32_optimize_t {
 	IA32_OPT_PLACECNST = 8,   /**< place constants in the blocks where they are used */
 	IA32_OPT_IMMOPS    = 16,  /**< create operations with immediate operands */
 	IA32_OPT_EXTBB     = 32,  /**< do extended basic block scheduling */
+	IA32_OPT_PUSHARGS  = 64,  /**< create pushs for function argument passing */
 } ia32_optimize_t;
 
 /**
@@ -147,10 +148,11 @@ typedef struct _ia32_transform_env_t {
 } ia32_transform_env_t;
 
 typedef struct _ia32_intrinsic_env_t {
-	entity *ll_div_op1;    /**< entity for first div operand (move into FPU) */
-	entity *ll_div_op2;    /**< entity for second div operand (move into FPU) */
-	entity *ll_d_conv;     /**< entity for converts ll -> d */
-	entity *d_ll_conv;     /**< entity for converts d -> ll */
+	ir_graph *irg;           /**< the irg, these entities belong to */
+	entity   *ll_div_op1;    /**< entity for first div operand (move into FPU) */
+	entity   *ll_div_op2;    /**< entity for second div operand (move into FPU) */
+	entity   *ll_d_conv;     /**< entity for converts ll -> d */
+	entity   *d_ll_conv;     /**< entity for converts d -> ll */
 } ia32_intrinsic_env_t;
 
 /**