Commit 634830b6 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

be: Move the info about the register classes and registers struct the...

be: Move the info about the register classes and registers struct the arch_env_t into struct arch_isa_if_t.
parent 1289d1b6
......@@ -58,12 +58,8 @@ static void TEMPLATE_before_ra(ir_graph *irg)
static TEMPLATE_isa_t TEMPLATE_isa_template = {
.base = {
.n_registers = N_TEMPLATE_REGISTERS,
.registers = TEMPLATE_registers,
.n_register_classes = N_TEMPLATE_CLASSES,
.register_classes = TEMPLATE_reg_classes,
.spill_cost = 7,
.reload_cost = 5,
.spill_cost = 7,
.reload_cost = 5,
},
};
......@@ -159,6 +155,10 @@ static ir_node *TEMPLATE_new_reload(ir_node *value, ir_node *spill,
}
static arch_isa_if_t const TEMPLATE_isa_if = {
.n_registers = N_TEMPLATE_REGISTERS,
.registers = TEMPLATE_registers,
.n_register_classes = N_TEMPLATE_CLASSES,
.register_classes = TEMPLATE_reg_classes,
.init = TEMPLATE_init,
.finish = TEMPLATE_finish,
.get_params = TEMPLATE_get_backend_params,
......
......@@ -641,12 +641,8 @@ static void amd64_finish_graph(ir_graph *irg)
static amd64_isa_t amd64_isa_template = {
.base = {
.n_registers = N_AMD64_REGISTERS,
.registers = amd64_registers,
.n_register_classes = N_AMD64_CLASSES,
.register_classes = amd64_reg_classes,
.spill_cost = 7,
.reload_cost = 5,
.spill_cost = 7,
.reload_cost = 5,
},
};
......@@ -764,8 +760,7 @@ static const backend_params *amd64_get_backend_params(void) {
static int amd64_is_valid_clobber(const char *clobber)
{
return x86_parse_clobber(&amd64_isa_template.base,
amd64_additional_clobber_names, clobber) != NULL;
return x86_parse_clobber(amd64_additional_clobber_names, clobber) != NULL;
}
static void amd64_init_types(void)
......@@ -793,6 +788,10 @@ static void amd64_init(void)
}
static arch_isa_if_t const amd64_isa_if = {
.n_registers = N_AMD64_REGISTERS,
.registers = amd64_registers,
.n_register_classes = N_AMD64_CLASSES,
.register_classes = amd64_reg_classes,
.init = amd64_init,
.finish = amd64_finish,
.get_params = amd64_get_backend_params,
......
......@@ -175,12 +175,8 @@ static void arm_handle_intrinsics(ir_graph *irg)
static arm_isa_t arm_isa_template = {
.base = {
.n_registers = N_ARM_REGISTERS,
.registers = arm_registers,
.n_register_classes = N_ARM_CLASSES,
.register_classes = arm_reg_classes,
.spill_cost = 7,
.reload_cost = 5,
.spill_cost = 7,
.reload_cost = 5,
},
};
......@@ -309,6 +305,10 @@ static void arm_init(void)
}
static arch_isa_if_t const arm_isa_if = {
.n_registers = N_ARM_REGISTERS,
.registers = arm_registers,
.n_register_classes = N_ARM_CLASSES,
.register_classes = arm_reg_classes,
.init = arm_init,
.finish = arm_finish,
.get_params = arm_get_libfirm_params,
......
......@@ -8,6 +8,7 @@
* @brief Processor architecture specification.
* @author Sebastian Hack
*/
#include "be_t.h"
#include "bearch.h"
#include "benode.h"
#include "beinfo.h"
......@@ -108,11 +109,11 @@ bool arch_reg_is_allocatable(const arch_register_req_t *req,
return true;
}
const arch_register_t *arch_find_register(const arch_env_t *arch_env,
const char *name)
arch_register_t const *arch_find_register(char const *const name)
{
for (size_t i = 0, n = arch_env->n_registers; i < n; ++i) {
const arch_register_t *reg = &arch_env->registers[i];
arch_register_t const *const regs = isa_if->registers;
for (size_t i = 0, n = isa_if->n_registers; i < n; ++i) {
arch_register_t const *const reg = &regs[i];
if (strcmp(reg->name, name) == 0)
return reg;
}
......
......@@ -301,6 +301,11 @@ struct arch_irn_ops_t {
* Architecture interface.
*/
struct arch_isa_if_t {
unsigned n_registers; /**< number of registers */
arch_register_t const *registers; /**< register array */
unsigned n_register_classes; /**< number of register classes */
arch_register_class_t const *register_classes; /**< register classes */
/**
* Initializes the isa interface. This is necessary before calling any
* other functions from this interface.
......@@ -394,14 +399,8 @@ struct arch_isa_if_t {
* ISA base class.
*/
struct arch_env_t {
unsigned n_registers; /**< number of registers */
const arch_register_t *registers; /**< register array */
/** number of register classes*/
unsigned n_register_classes;
/** register classes */
const arch_register_class_t *register_classes;
unsigned spill_cost; /**< cost for a be_Spill node */
unsigned reload_cost; /**< cost for a be_Reload node */
unsigned spill_cost; /**< cost for a be_Spill node */
unsigned reload_cost; /**< cost for a be_Reload node */
};
static inline bool arch_irn_is_ignore(const ir_node *irn)
......@@ -417,8 +416,7 @@ static inline bool arch_irn_consider_in_reg_alloc(
return req->cls == cls && !arch_register_req_is(req, ignore);
}
const arch_register_t *arch_find_register(const arch_env_t *arch_env,
const char *name);
arch_register_t const *arch_find_register(char const *name);
#define be_foreach_value(node, value, code) \
do { \
......
......@@ -281,9 +281,9 @@ static void be_ra_chordal_main(ir_graph *irg)
/* use one of the generic spiller */
/* Perform the following for each register class. */
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
for (int j = 0, m = arch_env->n_register_classes; j < m; ++j) {
const arch_register_class_t *cls = &arch_env->register_classes[j];
arch_register_class_t const *const reg_classes = isa_if->register_classes;
for (int j = 0, m = isa_if->n_register_classes; j < m; ++j) {
arch_register_class_t const *const cls = &reg_classes[j];
if (cls->flags & arch_register_class_flag_manual_ra)
continue;
......
......@@ -77,9 +77,8 @@ static void mark_live_nodes_registers(const ir_node *irn, lower_env_t *env)
ir_node *block = get_nodes_block(irn);
ir_graph *irg = get_irn_irg(irn);
arch_register_class_t const *cls = arch_get_irn_register(get_irn_n(irn, 0))->cls;
arch_env_t const *arch_env = be_get_irg_arch_env(irg);
be_irg_t *birg = be_birg_from_irg(irg);
unsigned n_regs = arch_env->n_registers;
unsigned n_regs = isa_if->n_registers;
unsigned *free_regs = rbitset_duplicate_obstack_alloc(&env->obst, birg->allocatable_regs, n_regs);
be_lv_t *lv = be_get_irg_liveness(irg);
......@@ -104,10 +103,7 @@ static arch_register_t const *get_free_register(ir_node *const perm, lower_env_t
return NULL;
ir_node *block = get_nodes_block(perm);
ir_graph *irg = get_irn_irg(perm);
arch_register_class_t const *cls = arch_get_irn_register(get_irn_n(perm, 0))->cls;
arch_env_t const *arch_env = be_get_irg_arch_env(irg);
unsigned n_regs = arch_env->n_registers;
unsigned *free_regs = (unsigned*)ir_nodehashmap_get(arch_register_t const, &env->live_regs, perm);
sched_foreach_reverse(block, node) {
......@@ -135,8 +131,10 @@ static arch_register_t const *get_free_register(ir_node *const perm, lower_env_t
break;
}
arch_register_t const *const regs = isa_if->registers;
unsigned const n_regs = isa_if->n_registers;
rbitset_foreach(free_regs, n_regs, free_idx) {
arch_register_t const *free_reg = &arch_env->registers[free_idx];
arch_register_t const *free_reg = &regs[free_idx];
if (free_reg->cls != cls)
continue;
......
......@@ -27,10 +27,9 @@
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
static const arch_env_t *arch_env;
static be_lv_t *lv;
static ir_node *current_node;
ir_node **register_values;
static be_lv_t *lv;
static ir_node *current_node;
ir_node **register_values;
static void clear_reg_value(ir_node *node)
{
......@@ -158,7 +157,7 @@ static void process_block(ir_node *block, void *data)
(void)data;
/* construct initial register assignment */
memset(register_values, 0, sizeof(ir_node*) * arch_env->n_registers);
memset(register_values, 0, sizeof(ir_node*) * isa_if->n_registers);
DB((dbg, LEVEL_1, "\nProcessing block %+F (from end)\n", block));
be_lv_foreach(lv, block, be_lv_state_end, node) {
......@@ -406,10 +405,9 @@ void be_peephole_opt(ir_graph *irg)
{
be_assure_live_sets(irg);
arch_env = be_get_irg_arch_env(irg);
lv = be_get_irg_liveness(irg);
lv = be_get_irg_liveness(irg);
register_values = XMALLOCN(ir_node*, arch_env->n_registers);
register_values = XMALLOCN(ir_node*, isa_if->n_registers);
irg_block_walk_graph(irg, process_block, NULL, NULL);
......
......@@ -1819,10 +1819,9 @@ static void be_pref_alloc(ir_graph *new_irg)
/* determine a good coloring order */
determine_block_order();
const arch_env_t *arch_env = be_get_irg_arch_env(new_irg);
int n_cls = arch_env->n_register_classes;
for (int c = 0; c < n_cls; ++c) {
cls = &arch_env->register_classes[c];
arch_register_class_t const *const reg_classes = isa_if->register_classes;
for (int c = 0, n_cls = isa_if->n_register_classes; c < n_cls; ++c) {
cls = &reg_classes[c];
if (cls->flags & arch_register_class_flag_manual_ra)
continue;
......
......@@ -822,10 +822,8 @@ static void prepare_constr_insn(ir_node *const node)
continue;
if (!arch_register_req_is(req, limited))
continue;
if (def_constr == NULL) {
const arch_env_t *const arch_env = birg->main_env->arch_env;
def_constr = rbitset_alloca(arch_env->n_registers);
}
if (def_constr == NULL)
def_constr = rbitset_alloca(isa_if->n_registers);
rbitset_foreach(req->limited, cls->n_regs, e) {
const arch_register_t *reg = arch_register_for_index(cls, e);
rbitset_set(def_constr, reg->global_index);
......
......@@ -677,8 +677,7 @@ static void verify_block_register_allocation(ir_node *block, void *data)
{
be_verify_reg_alloc_env_t *const env = (be_verify_reg_alloc_env_t*)data;
ir_graph *const irg = get_irn_irg(block);
unsigned const n_regs = be_get_irg_arch_env(irg)->n_registers;
unsigned const n_regs = isa_if->n_registers;
ir_node const **const registers = ALLOCANZ(ir_node const*, n_regs);
be_lv_foreach(env->lv, block, be_lv_state_end, lv_node) {
......
......@@ -1446,12 +1446,8 @@ static void ia32_finish(void)
*/
static ia32_isa_t ia32_isa_template = {
.base = {
.n_registers = N_IA32_REGISTERS,
.registers = ia32_registers,
.n_register_classes = N_IA32_CLASSES,
.register_classes = ia32_reg_classes,
.spill_cost = 7,
.reload_cost = 5,
.spill_cost = 7,
.reload_cost = 5,
},
};
......@@ -1483,8 +1479,7 @@ static void ia32_mark_remat(ir_node *node)
static int ia32_is_valid_clobber(const char *clobber)
{
return x86_parse_clobber(&ia32_isa_template.base,
ia32_additional_clobber_names, clobber) != NULL;
return x86_parse_clobber(ia32_additional_clobber_names, clobber) != NULL;
}
static void ia32_lower_for_target(void)
......@@ -1588,6 +1583,10 @@ static const lc_opt_table_entry_t ia32_options[] = {
};
static arch_isa_if_t const ia32_isa_if = {
.n_registers = N_IA32_REGISTERS,
.registers = ia32_registers,
.n_register_classes = N_IA32_CLASSES,
.register_classes = ia32_reg_classes,
.init = ia32_init,
.finish = ia32_finish,
.get_params = ia32_get_libfirm_params,
......
......@@ -81,16 +81,15 @@ static arch_register_req_t const *x86_make_register_req(struct obstack *obst,
return req;
}
arch_register_t const *x86_parse_clobber(const arch_env_t *arch_env,
const x86_clobber_name_t *additional_clobber_names,
const char *const clobber)
arch_register_t const *x86_parse_clobber(x86_clobber_name_t const *const additional_clobber_names, char const *const clobber)
{
arch_register_t const *reg = arch_find_register(arch_env, clobber);
arch_register_t const *reg = arch_find_register(clobber);
if (reg != NULL)
return reg;
arch_register_t const *const regs = isa_if->registers;
for (size_t i = 0; additional_clobber_names[i].name != NULL; ++i) {
if (strcmp(additional_clobber_names[i].name, clobber) == 0)
return &arch_env->registers[additional_clobber_names[i].index];
return &regs[additional_clobber_names[i].index];
}
return NULL;
}
......@@ -399,15 +398,12 @@ ir_node *x86_match_ASM(const ir_node *node, new_bd_asm_func new_bd_asm,
}
/* parse clobbers */
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
unsigned clobber_bits[arch_env->n_register_classes];
unsigned clobber_bits[isa_if->n_register_classes];
memset(&clobber_bits, 0, sizeof(clobber_bits));
ident **const clobbers = get_ASM_clobbers(node);
for (size_t c = 0; c < n_clobbers; ++c) {
char const *const clobber = get_id_str(clobbers[c]);
arch_register_t const *const reg
= x86_parse_clobber(arch_env, additional_clobber_names, clobber);
arch_register_t const *const reg = x86_parse_clobber(additional_clobber_names, clobber);
if (reg != NULL) {
assert(reg->cls->n_regs <= sizeof(unsigned) * 8);
/* x87 registers may still be used as input, even if clobbered. */
......
......@@ -79,8 +79,7 @@ typedef void (*emit_register_func)(const arch_register_t *reg, char modifier,
void x86_emit_asm(const ir_node *node, const x86_asm_attr_t *attr,
emit_register_func emit_register);
const arch_register_t *x86_parse_clobber(const arch_env_t *arch_env,
const x86_clobber_name_t *additional_clobber_names, const char *name);
arch_register_t const *x86_parse_clobber(x86_clobber_name_t const *additional_clobber_names, char const *name);
typedef ir_node* (*new_bd_asm_func)(dbg_info *dbgi, ir_node *block, int arity,
ir_node *in[], int out_arity,
......
......@@ -40,12 +40,8 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
static sparc_isa_t sparc_isa_template = {
.base = {
.n_registers = N_SPARC_REGISTERS,
.registers = sparc_registers,
.n_register_classes = N_SPARC_CLASSES,
.register_classes = sparc_reg_classes,
.spill_cost = 7,
.reload_cost = 5,
.spill_cost = 7,
.reload_cost = 5,
},
};
......@@ -555,6 +551,10 @@ static ir_node *sparc_new_reload(ir_node *value, ir_node *spill,
}
static arch_isa_if_t const sparc_isa_if = {
.n_registers = N_SPARC_REGISTERS,
.registers = sparc_registers,
.n_register_classes = N_SPARC_CLASSES,
.register_classes = sparc_reg_classes,
.init = sparc_init,
.finish = sparc_finish,
.get_params = sparc_get_backend_params,
......
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