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Commit 6647a215 authored by Matthias Braun's avatar Matthias Braun
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cleanup, use C99

parent 9dc926c1
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ir/be/ia32/ia32_architecture.c
View file @ 6647a215
......@@ -798,12 +798,11 @@ static void autodetect_arch(void)
/* We use the cpuid instruction to detect the CPU features */
if (x86_toogle_cpuid()) {
cpuid_registers regs;
char vendorid[13];
x86_cpu_info_t cpu_info;
/* get vendor ID */
cpuid_registers regs;
x86_cpuid(&regs, 0);
char vendorid[13];
memcpy(&vendorid[0], &regs.r.ebx, 4);
memcpy(&vendorid[4], &regs.r.edx, 4);
memcpy(&vendorid[8], &regs.r.ecx, 4);
......@@ -812,6 +811,7 @@ static void autodetect_arch(void)
/* get processor info and feature bits */
x86_cpuid(&regs, 1);
x86_cpu_info_t cpu_info;
cpu_info.cpu_stepping = (regs.r.eax >> 0) & 0x0F;
cpu_info.cpu_model = (regs.r.eax >> 4) & 0x0F;
cpu_info.cpu_family = (regs.r.eax >> 8) & 0x0F;
......@@ -923,12 +923,9 @@ void ia32_setup_cg_config(void)
void ia32_init_architecture(void)
{
lc_opt_entry_t *be_grp, *ia32_grp;
memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
ia32_grp = lc_opt_get_grp(be_grp, "ia32");
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
lc_opt_add_table(ia32_grp, ia32_architecture_options);
}
ir/be/ia32/ia32_fpu.c
View file @ 6647a215
......@@ -39,20 +39,15 @@ static ir_entity *create_ent(int value, const char *name)
{
ir_mode *mode = mode_Hu;
ir_type *type = new_type_primitive(mode);
ir_type *glob = get_glob_type();
ir_graph *cnst_irg;
ir_entity *ent;
ir_node *cnst;
set_type_alignment_bytes(type, 4);
ent = new_entity(glob, new_id_from_str(name), type);
ir_type *glob = get_glob_type();
ir_entity *ent = new_entity(glob, new_id_from_str(name), type);
set_entity_ld_ident(ent, get_entity_ident(ent));
set_entity_visibility(ent, ir_visibility_local);
add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
cnst_irg = get_const_code_irg();
cnst = new_r_Const_long(cnst_irg, mode, value);
ir_graph *cnst_irg = get_const_code_irg();
ir_node *cnst = new_r_Const_long(cnst_irg, mode, value);
set_atomic_ent_value(ent, cnst);
return ent;
......@@ -67,12 +62,12 @@ static void create_fpcw_entities(void)
static ir_node *create_fpu_mode_spill(void *env, ir_node *state, bool force,
ir_node *after)
{
(void) env;
(void)env;
/* we don't spill the fpcw in unsafe mode */
if (ia32_cg_config.use_unsafe_floatconv) {
ir_node *block = get_nodes_block(state);
if (force == 1 || !is_ia32_ChangeCW(state)) {
if (force || !is_ia32_ChangeCW(state)) {
ir_node *spill = new_bd_ia32_FnstCWNOP(NULL, block, state);
sched_add_after(after, spill);
return spill;
......@@ -80,7 +75,7 @@ static ir_node *create_fpu_mode_spill(void *env, ir_node *state, bool force,
return NULL;
}
if (force == 1 || !is_ia32_ChangeCW(state)) {
if (force || !is_ia32_ChangeCW(state)) {
ir_graph *irg = get_irn_irg(state);
ir_node *block = get_nodes_block(state);
ir_node *noreg = ia32_new_NoReg_gp(irg);
......@@ -96,7 +91,6 @@ static ir_node *create_fpu_mode_spill(void *env, ir_node *state, bool force,
sched_add_after(skip_Proj(after), spill);
return spill;
}
return NULL;
}
......@@ -111,9 +105,7 @@ static ir_node *create_fldcw_ent(ir_node *block, ir_entity *entity)
ir_graph *irg = get_irn_irg(block);
ir_node *nomem = get_irg_no_mem(irg);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *reload;
reload = new_bd_ia32_FldCW(NULL, block, noreg, noreg, nomem);
ir_node *reload = new_bd_ia32_FldCW(NULL, block, noreg, noreg, nomem);
set_ia32_op_type(reload, ia32_AddrModeS);
set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
set_ia32_am_ent(reload, entity);
......@@ -128,17 +120,16 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
ir_node *spill, ir_node *before,
ir_node *last_state)
{
(void)env;
ir_graph *irg = get_irn_irg(state);
ir_node *block = get_nodes_block(before);
ir_node *frame = get_irg_frame(irg);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *reload = NULL;
(void) env;
if (ia32_cg_config.use_unsafe_floatconv) {
if (fpcw_round == NULL) {
if (fpcw_round == NULL)
create_fpcw_entities();
}
if (spill != NULL) {
reload = create_fldcw_ent(block, fpcw_round);
} else {
......@@ -219,52 +210,43 @@ typedef struct collect_fpu_mode_nodes_env_t {
static void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
{
collect_fpu_mode_nodes_env_t *env = (collect_fpu_mode_nodes_env_t*)data;
const arch_register_t *reg;
if (!mode_is_data(get_irn_mode(node)))
return;
reg = arch_get_irn_register(node);
if (reg == &ia32_registers[REG_FPCW] && !is_ia32_ChangeCW(node)) {
collect_fpu_mode_nodes_env_t *env = (collect_fpu_mode_nodes_env_t*)data;
const arch_register_t *reg = arch_get_irn_register(node);
if (reg == &ia32_registers[REG_FPCW] && !is_ia32_ChangeCW(node))
ARR_APP1(ir_node*, env->state_nodes, node);
}
}
static void rewire_fpu_mode_nodes(ir_graph *irg)
{
collect_fpu_mode_nodes_env_t env;
be_ssa_construction_env_t senv;
const arch_register_t *reg = &ia32_registers[REG_FPCW];
ir_node *initial_value;
ir_node **phis;
be_lv_t *lv = be_get_irg_liveness(irg);
size_t i, len;
/* do ssa construction for the fpu modes */
collect_fpu_mode_nodes_env_t env;
env.state_nodes = NEW_ARR_F(ir_node*, 0);
irg_walk_graph(irg, collect_fpu_mode_nodes_walker, NULL, &env);
/* nothing needs to be done, in fact we must not continue as for endless
* loops noone is using the initial_value and it will point to a bad node
* now
*/
* now */
if (ARR_LEN(env.state_nodes) == 0) {
DEL_ARR_F(env.state_nodes);
return;
}
initial_value = be_get_initial_reg_value(irg, reg);
const arch_register_t *reg = &ia32_registers[REG_FPCW];
ir_node *initial_value = be_get_initial_reg_value(irg, reg);
be_ssa_construction_env_t senv;
be_ssa_construction_init(&senv, irg);
be_ssa_construction_add_copies(&senv, env.state_nodes,
ARR_LEN(env.state_nodes));
be_ssa_construction_fix_users(&senv, initial_value);
be_lv_t *lv = be_get_irg_liveness(irg);
if (lv != NULL) {
be_ssa_construction_update_liveness_phis(&senv, lv);
be_liveness_update(lv, initial_value);
len = ARR_LEN(env.state_nodes);
for (i = 0; i < len; ++i) {
for (size_t i = 0, len = ARR_LEN(env.state_nodes); i < len; ++i) {
be_liveness_update(lv, env.state_nodes[i]);
}
} else {
......@@ -272,9 +254,8 @@ static void rewire_fpu_mode_nodes(ir_graph *irg)
}
/* set registers for the phis */
phis = be_ssa_construction_get_new_phis(&senv);
len = ARR_LEN(phis);
for (i = 0; i < len; ++i) {
ir_node **phis = be_ssa_construction_get_new_phis(&senv);
for (size_t i = 0, len = ARR_LEN(phis); i < len; ++i) {
ir_node *phi = phis[i];
arch_set_irn_register(phi, reg);
}
......
ir/be/ia32/ia32_x87.c
View file @ 6647a215
......@@ -48,7 +48,7 @@ typedef struct x87_simulator x87_simulator;
* An entry on the simulated x87 stack.
*/
typedef struct st_entry {
int reg_idx; /**< the virtual register index of this stack value */
unsigned reg_idx; /**< the virtual register index of this stack value */
ir_node *node; /**< the node that produced this value */
} st_entry;
......@@ -57,33 +57,22 @@ typedef struct st_entry {
*/
typedef struct x87_state {
st_entry st[N_FLOAT_REGS]; /**< the register stack */
int depth; /**< the current stack depth */
unsigned depth; /**< the current stack depth */
x87_simulator *sim; /**< The simulator. */
} x87_state;
/** An empty state, used for blocks without fp instructions. */
static x87_state empty = { { {0, NULL}, }, 0, NULL };
/**
* Return values of the instruction simulator functions.
*/
enum {
NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
in the schedule AFTER the current node. */
};
/**
* The type of an instruction simulator function.
*
* @param state the x87 state
* @param n the node to be simulated
*
* @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
* simulated further
* NO_NODE_ADDED otherwise
* @return true if a node was added AFTER n in schedule that MUST be simulated
* further
*/
typedef int (*sim_func)(x87_state *state, ir_node *n);
typedef bool (*sim_func)(x87_state *state, ir_node *n);
/**
* A block state: Every block has a x87 state at the beginning and at the end.
......@@ -112,17 +101,16 @@ struct x87_simulator {
* Returns the current stack depth.
*
* @param state the x87 state
*
* @return the x87 stack depth
*/
static int x87_get_depth(const x87_state *state)
static unsigned x87_get_depth(const x87_state *state)
{
return state->depth;
}
static st_entry *x87_get_entry(x87_state *const state, int const pos)
static st_entry *x87_get_entry(x87_state *const state, unsigned const pos)
{
assert(0 <= pos && pos < state->depth);
assert(pos < state->depth);
return &state->st[N_FLOAT_REGS - state->depth + pos];
}
......@@ -131,10 +119,9 @@ static st_entry *x87_get_entry(x87_state *const state, int const pos)
*
* @param state the x87 state
* @param pos a stack position
*
* @return the fp register index that produced the value at st(pos)
*/
static int x87_get_st_reg(const x87_state *state, int pos)
static unsigned x87_get_st_reg(const x87_state *state, unsigned pos)
{
return x87_get_entry((x87_state*)state, pos)->reg_idx;
}
......@@ -147,7 +134,7 @@ static int x87_get_st_reg(const x87_state *state, int pos)
*/
static void x87_dump_stack(const x87_state *state)
{
for (int i = state->depth; i-- != 0;) {
for (unsigned i = state->depth; i-- > 0;) {
st_entry const *const entry = x87_get_entry((x87_state*)state, i);
DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
}
......@@ -163,7 +150,8 @@ static void x87_dump_stack(const x87_state *state)
* @param node the IR node that produces the value of the fp register
* @param pos the stack position where the new value should be entered
*/
static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
static void x87_set_st(x87_state *state, unsigned reg_idx, ir_node *node,
unsigned pos)
{
st_entry *const entry = x87_get_entry(state, pos);
entry->reg_idx = reg_idx;
......@@ -179,7 +167,7 @@ static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
* @param state the x87 state
* @param pos the stack position to change the tos with
*/
static void x87_fxch(x87_state *state, int pos)
static void x87_fxch(x87_state *state, unsigned pos)
{
st_entry *const a = x87_get_entry(state, pos);
st_entry *const b = x87_get_entry(state, 0);
......@@ -196,17 +184,16 @@ static void x87_fxch(x87_state *state, int pos)
*
* @param state the x87 state
* @param reg_idx the register fp index
*
* @return the stack position where the register is stacked
* or -1 if the virtual register was not found
*/
static int x87_on_stack(const x87_state *state, int reg_idx)
static unsigned x87_on_stack(const x87_state *state, unsigned reg_idx)
{
for (int i = 0; i < state->depth; ++i) {
for (unsigned i = 0; i < state->depth; ++i) {
if (x87_get_st_reg(state, i) == reg_idx)
return i;
}
return -1;
return (unsigned)-1;
}
/**
......@@ -216,9 +203,9 @@ static int x87_on_stack(const x87_state *state, int reg_idx)
* @param reg_idx the register fp index
* @param node the node that produces the value of the fp register
*/
static void x87_push(x87_state *state, int reg_idx, ir_node *node)
static void x87_push(x87_state *state, unsigned reg_idx, ir_node *node)
{
assert(x87_on_stack(state, reg_idx) == -1 && "double push");
assert(x87_on_stack(state, reg_idx) == (unsigned)-1 && "double push");
assert(state->depth < N_FLOAT_REGS && "stack overrun");
++state->depth;
......@@ -226,7 +213,8 @@ static void x87_push(x87_state *state, int reg_idx, ir_node *node)
entry->reg_idx = reg_idx;
entry->node = node;
DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
DB((dbg, LEVEL_2, "After PUSH: "));
DEBUG_ONLY(x87_dump_stack(state);)
}
/**
......@@ -237,10 +225,9 @@ static void x87_push(x87_state *state, int reg_idx, ir_node *node)
static void x87_pop(x87_state *state)
{
assert(state->depth > 0 && "stack underrun");
--state->depth;
DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
DB((dbg, LEVEL_2, "After POP: "));
DEBUG_ONLY(x87_dump_stack(state);)
}
/**
......@@ -258,13 +245,11 @@ static void x87_emms(x87_state *state)
*
* @param sim the x87 simulator handle
* @param block the current block
*
* @return the block state
*/
static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
{
blk_state *res = pmap_get(blk_state, sim->blk_states, block);
if (res == NULL) {
res = OALLOC(&sim->obst, blk_state);
res->begin = NULL;
......@@ -272,7 +257,6 @@ static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
pmap_insert(sim->blk_states, block, res);
}
return res;
}
......@@ -281,7 +265,6 @@ static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
*
* @param sim the x87 simulator handle
* @param src the x87 state that will be cloned
*
* @return a cloned copy of the src state
*/
static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
......@@ -300,38 +283,16 @@ static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
*/
static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
{
assert(get_irn_mode(n) == mode_T && "Need mode_T node");
assert(get_irn_mode(n) == mode_T);
foreach_out_edge(n, edge) {
ir_node *proj = get_edge_src_irn(edge);
if (get_irn_mode(proj) == m)
return proj;
}
panic("Proj not found");
}
/**
* Wrap the arch_* function here so we can check for errors.
*/
static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
{
const arch_register_t *res = arch_get_irn_register(irn);
assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
return res;
}
static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
int pos)
{
const arch_register_t *res = arch_get_irn_register_out(irn, pos);
assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
return res;
}
static inline const arch_register_t *get_st_reg(int index)
static inline const arch_register_t *get_st_reg(unsigned index)
{
return &ia32_registers[REG_ST0 + index];
}
......@@ -343,7 +304,7 @@ static inline const arch_register_t *get_st_reg(int index)
* @param n the node after the fxch
* @param pos exchange st(pos) with st(0)
*/
static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
static void x87_create_fxch(x87_state *state, ir_node *n, unsigned pos)
{
x87_fxch(state, pos);
......@@ -372,15 +333,10 @@ static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
* @param block the current block
* @param state the current x87 stack state, might be modified
* @param dst_state destination state
*
* @return state
*/
static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
{
int i, n_cycles, k, ri;
unsigned cycles[4], all_mask;
char cycle_idx[4][8];
assert(state->depth == dst_state->depth);
/* Some mathematics here:
......@@ -396,12 +352,14 @@ static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state
* in the next block to bring one operand on top, so the
* number of ops in the first case is identical.
* Further, no more than 4 cycles can exists (4 x 2). */
all_mask = (1 << (state->depth)) - 1;
for (n_cycles = 0; all_mask; ++n_cycles) {
int src_idx, dst_idx;
unsigned all_mask = (1 << (state->depth)) - 1;
unsigned cycles[4];
unsigned char cycle_idx[4][8];
unsigned n_cycles;
for (n_cycles = 0; all_mask != 0; ++n_cycles) {
/* find the first free slot */
unsigned i;
for (i = 0; i < state->depth; ++i) {
if (all_mask & (1 << i)) {
all_mask &= ~(1 << i);
......@@ -412,15 +370,15 @@ static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state
}
}
if (! all_mask) {
if (all_mask == 0) {
/* no more cycles found */
break;
}
k = 0;
unsigned k = 0;
cycles[n_cycles] = (1 << i);
cycle_idx[n_cycles][k++] = i;
for (src_idx = i; ; src_idx = dst_idx) {
for (unsigned src_idx = i, dst_idx; ; src_idx = dst_idx) {
dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
if ((all_mask & (1 << dst_idx)) == 0)
......@@ -430,10 +388,10 @@ static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state
cycles[n_cycles] |= (1 << dst_idx);
all_mask &= ~(1 << dst_idx);
}
cycle_idx[n_cycles][k] = -1;
cycle_idx[n_cycles][k] = (unsigned char)-1;
}
if (n_cycles <= 0) {
if (n_cycles == 0) {
/* no permutation needed */
return state;
}
......@@ -444,39 +402,32 @@ static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state
DB((dbg, LEVEL_2, " to\n"));
DEBUG_ONLY(x87_dump_stack(dst_state);)
#ifdef DEBUG_libfirm
DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
for (ri = 0; ri < n_cycles; ++ri) {
for (unsigned ri = 0; ri < n_cycles; ++ri) {
DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
for (k = 0; cycle_idx[ri][k] != -1; ++k)
for (unsigned k = 0; cycle_idx[ri][k] != (unsigned char)-1; ++k)
DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
DB((dbg, LEVEL_2, "\n"));
}
#endif
/*
* Find the place node must be insert.
/* Find the place node must be insert.
* We have only one successor block, so the last instruction should
* be a jump.
*/
* be a jump. */
ir_node *const before = sched_last(block);
assert(is_cfop(before));
/* now do the permutations */
for (ri = 0; ri < n_cycles; ++ri) {
if ((cycles[ri] & 1) == 0) {
/* this cycle does not include the tos */
for (unsigned ri = 0; ri < n_cycles; ++ri) {
if ((cycles[ri] & 1) == 0)
x87_create_fxch(state, before, cycle_idx[ri][0]);
}
for (k = 1; cycle_idx[ri][k] != -1; ++k) {
for (unsigned k = 1; cycle_idx[ri][k] != (unsigned char)-1; ++k) {
x87_create_fxch(state, before, cycle_idx[ri][k]);
}
if ((cycles[ri] & 1) == 0) {
/* this cycle does not include the tos */
if ((cycles[ri] & 1) == 0)
x87_create_fxch(state, before, cycle_idx[ri][0]);
}
}
return state;
}
......@@ -488,7 +439,8 @@ static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state
* @param pos push st(pos) on stack
* @param val the value to push
*/
static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const out_reg_idx, ir_node *const val)
static void x87_create_fpush(x87_state *state, ir_node *n, unsigned pos,
unsigned const out_reg_idx, ir_node *const val)
{
x87_push(state, out_reg_idx, val);
......@@ -509,10 +461,10 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const ou
* @param state the x87 state
* @param n the node after the fpop
* @param pos the index of the entry to remove the register stack
*
* @return the fpop node
*/
static ir_node *x87_create_fpop(x87_state *const state, ir_node *const n, int const pos)
static ir_node *x87_create_fpop(x87_state *const state, ir_node *const n,
unsigned const pos)
{
if (pos != 0) {
st_entry *const dst = x87_get_entry(state, pos);
......@@ -543,19 +495,17 @@ static ir_node *x87_create_fpop(x87_state *const state, ir_node *const n, int co
* @param irn The node at which liveness should be computed.
* @param live The bitset of registers live before @p irn. This set gets modified by updating it to
* the registers live after irn.
*
* @return The live bitset.
*/
static fp_liveness fp_liveness_transfer(ir_node *irn, fp_liveness live)
{
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
be_foreach_definition(irn, cls, def, req,
const arch_register_t *reg = x87_get_irn_register(def);
const arch_register_t *reg = arch_get_irn_register(def);
live &= ~(1 << reg->index);
);
be_foreach_use(irn, cls, in_req_, op, op_req_,
const arch_register_t *reg = x87_get_irn_register(op);
const arch_register_t *reg = arch_get_irn_register(op);
live |= 1 << reg->index;
);
return live;
......@@ -566,7 +516,6 @@ static fp_liveness fp_liveness_transfer(ir_node *irn, fp_liveness live)
*
* @param sim the simulator handle
* @param bl the block
*
* @return The live bitset at the end of this block
*/
static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
......@@ -576,7 +525,7 @@ static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *b
const be_lv_t *lv = sim->lv;
be_lv_foreach_cls(lv, block, be_lv_state_end, cls, node) {
const arch_register_t *reg = x87_get_irn_register(node);
const arch_register_t *reg = arch_get_irn_register(node);
live |= 1 << reg->index;
}
......@@ -592,13 +541,12 @@ static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *b
* @param sim the simulator handle
* @param pos the node
* @param kill kill mask for the output registers
*
* @return The live bitset.
*/
static unsigned fp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
static fp_liveness fp_live_args_after(x87_simulator *sim, const ir_node *pos,
fp_liveness kill)
{
unsigned idx = get_irn_idx(pos);
assert(idx < sim->n_idx);
return sim->live[idx] & ~kill;
}
......@@ -612,20 +560,18 @@ static unsigned fp_live_args_after(x87_simulator *sim, const ir_node *pos, unsig
static void update_liveness(x87_simulator *sim, ir_node *block)
{