Commit 66fa68a3 authored by Matthias Braun's avatar Matthias Braun
Browse files

be: use designated initializer for regs, regclasses, reg_reqs

parent 216d5d11
......@@ -55,90 +55,93 @@ static pmap *node_to_stack;
static be_stackorder_t *stackorder;
static const arch_register_req_t amd64_requirement_gp = {
arch_register_req_type_normal,
&amd64_reg_classes[CLASS_amd64_gp],
NULL,
0,
0,
0
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = NULL,
.type = arch_register_req_type_normal,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const arch_register_req_t amd64_requirement_flags = {
arch_register_req_type_normal,
&amd64_reg_classes[CLASS_amd64_flags],
NULL,
0,
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_flags],
.limited = NULL,
.type = arch_register_req_type_normal,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const arch_register_req_t amd64_requirement_xmm = {
arch_register_req_type_normal,
&amd64_reg_classes[CLASS_amd64_xmm],
NULL,
0,
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_xmm],
.limited = NULL,
.type = arch_register_req_type_normal,
.other_same = 0,
.other_different = 0,
.width = 1,
};
#define BIT(x) (1u << x)
static const arch_register_req_t amd64_requirement_gp_same_0 = {
arch_register_req_type_normal | arch_register_req_type_should_be_same,
&amd64_reg_classes[CLASS_amd64_gp],
NULL,
BIT(0),
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = NULL,
.type = arch_register_req_type_normal
| arch_register_req_type_should_be_same,
.other_same = BIT(0),
.other_different = 0,
.width = 1,
};
static const arch_register_req_t amd64_requirement_xmm_same_0 = {
arch_register_req_type_normal | arch_register_req_type_should_be_same,
&amd64_reg_classes[CLASS_amd64_xmm],
NULL,
BIT(0),
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_xmm],
.limited = NULL,
.type = arch_register_req_type_normal
| arch_register_req_type_should_be_same,
.other_same = BIT(0),
.other_different = 0,
.width = 1,
};
static const arch_register_req_t amd64_requirement_gp_same_0_not_1 = {
arch_register_req_type_normal | arch_register_req_type_should_be_same
| arch_register_req_type_must_be_different,
&amd64_reg_classes[CLASS_amd64_gp],
NULL,
BIT(0),
BIT(1),
1
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = NULL,
.type = arch_register_req_type_normal
| arch_register_req_type_should_be_same
| arch_register_req_type_must_be_different,
.other_same = BIT(0),
.other_different = BIT(1),
.width = 1,
};
static const unsigned amd64_limited_gp_rcx [] = { BIT(REG_GP_RCX) };
static const arch_register_req_t amd64_requirement_rcx = {
arch_register_req_type_limited,
&amd64_reg_classes[CLASS_amd64_gp],
amd64_limited_gp_rcx,
0,
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = amd64_limited_gp_rcx,
.type = arch_register_req_type_limited,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const unsigned amd64_limited_gp_rax [] = { BIT(REG_GP_RAX) };
static const arch_register_req_t amd64_requirement_rax = {
arch_register_req_type_limited,
&amd64_reg_classes[CLASS_amd64_gp],
amd64_limited_gp_rax,
0,
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = amd64_limited_gp_rax,
.type = arch_register_req_type_limited,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const unsigned amd64_limited_gp_rdx [] = { BIT(REG_GP_RDX) };
static const arch_register_req_t amd64_requirement_rdx = {
arch_register_req_type_limited,
&amd64_reg_classes[CLASS_amd64_gp],
amd64_limited_gp_rdx,
0,
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = amd64_limited_gp_rdx,
.type = arch_register_req_type_limited,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const arch_register_req_t *mem_reqs[] = {
......@@ -155,7 +158,6 @@ static const arch_register_req_t *xmm_mem_reqs[] = {
&arch_no_requirement,
};
static const arch_register_req_t *reg_reg_mem_reqs[] = {
&amd64_requirement_gp,
&amd64_requirement_gp,
......
......@@ -132,22 +132,22 @@ static void amd64_before_ra(ir_graph *irg)
}
static const arch_register_req_t amd64_requirement_gp = {
arch_register_req_type_normal,
&amd64_reg_classes[CLASS_amd64_gp],
NULL,
0,
0,
1
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = NULL,
.type = arch_register_req_type_normal,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const unsigned amd64_limited_gp_rsp [] = { (1 << REG_GP_RSP) };
static const arch_register_req_t amd64_single_reg_req_gp_rsp = {
arch_register_req_type_limited,
&amd64_reg_classes[CLASS_amd64_gp],
amd64_limited_gp_rsp,
0,
0,
1
.type = arch_register_req_type_limited,
.cls = &amd64_reg_classes[CLASS_amd64_gp],
.limited = amd64_limited_gp_rsp,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const arch_register_req_t *am_pushpop_base_reqs[] = {
......
......@@ -17,12 +17,12 @@
#include "raw_bitset.h"
arch_register_req_t const arch_no_requirement = {
arch_register_req_type_none,
NULL,
NULL,
0,
0,
0
.cls = NULL,
.limited = NULL,
.type = arch_register_req_type_none,
.other_same = 0,
.other_different = 0,
.width = 0,
};
/**
......
......@@ -1143,12 +1143,12 @@ sub generate_requirements {
$result = <<EOF;
{
arch_register_req_type_none,
NULL, /* regclass */
NULL, /* limit bitset */
0, /* same pos */
0, /* different pos */
0 /* width */
.cls = NULL,
.limited = NULL,
.type = arch_register_req_type_none,
.other_same = 0,
.other_different = 0,
.width = 0,
};
EOF
......@@ -1158,12 +1158,12 @@ EOF
$class = $reqs;
$result = <<EOF;
{
${reqtype},
& ${arch}_reg_classes[CLASS_${arch}_${class}],
NULL, /* limit bitset */
0, /* same pos */
0, /* different pos */
$width /* width */
.cls = &${arch}_reg_classes[CLASS_${arch}_${class}],
.limited = NULL,
.type = ${reqtype},
.other_same = 0,
.other_different = 0,
.width = $width,
};
EOF
......@@ -1194,12 +1194,12 @@ EOF
$class = $regclass;
$result = <<EOF;
{
${reqtype},
& ${arch}_reg_classes[CLASS_${arch}_${class}],
${limit_bitset},
${same_pos}, /* same pos */
${different_pos}, /* different pos */
$width /* width */
.cls = &${arch}_reg_classes[CLASS_${arch}_${class}],
.limited = ${limit_bitset},
.type = ${reqtype},
.other_same = ${same_pos},
.other_different = ${different_pos},
.width = $width,
};
EOF
......
......@@ -134,19 +134,30 @@ foreach my $class_name (keys(%reg_classes)) {
$single_constraints .= <<EOF;
static const arch_register_req_t ${arch}_class_reg_req_${old_classname} = {
arch_register_req_type_normal,
&${arch}_reg_classes[CLASS_${arch}_${old_classname}],
NULL,
0,
0,
1
.cls = &${arch}_reg_classes[CLASS_${arch}_${old_classname}],
.limited = NULL,
.type = arch_register_req_type_normal,
.other_same = 0,
.other_different = 0,
.width = 1,
};
EOF
$classdef .= "\tCLASS_$class_name = $class_idx,\n";
my $numregs = @class;
my $first_reg = "&${arch}_registers[REG_". uc($class[0]->{"name"}) . "]";
push(@regclasses, "{ $class_idx, \"$class_name\", $numregs, NULL, $first_reg, $flags_prepared, &${arch}_class_reg_req_${old_classname} }");
my $rcdef = <<EOF;
{
.name = \"$class_name\",
.mode = NULL,
.regs = $first_reg,
.class_req = &${arch}_class_reg_req_${old_classname},
.index = $class_idx,
.n_regs = $numregs,
.flags = $flags_prepared,
},
EOF
push(@regclasses, $rcdef);
my $idx = 0;
$reginit .= "\t$arch\_reg_classes[CLASS_".$class_name."].mode = $class_mode;\n";
......@@ -173,14 +184,14 @@ EOF
$regtypes_def .= <<EOF;
{
"${realname}",
${class_ptr},
REG_${classuc}_${ucname},
REG_${ucname},
${type},
&${arch}_single_reg_req_${old_classname}_${name},
${dwarf_number},
${encoding}
.name = "${realname}",
.reg_class = ${class_ptr},
.single_req = &${arch}_single_reg_req_${old_classname}_${name},
.type = ${type},
.index = REG_${classuc}_${ucname},
.global_index = REG_${ucname},
.dwarf_number = ${dwarf_number},
.encoding = ${encoding},
},
EOF
......@@ -188,12 +199,12 @@ EOF
$single_constraints .= <<EOF;
static const unsigned ${arch}_limited_${old_classname}_${name} [] = ${limitedarray};
static const arch_register_req_t ${arch}_single_reg_req_${old_classname}_${name} = {
arch_register_req_type_limited,
${class_ptr},
${arch}_limited_${old_classname}_${name},
0,
0,
1
.type = arch_register_req_type_limited,
.cls = ${class_ptr},
.limited = ${arch}_limited_${old_classname}_${name},
.other_same = 0,
.other_different = 0,
.width = 1,
};
EOF
......@@ -280,7 +291,7 @@ print OUT<<EOF;
${single_constraints}
EOF
print OUT "arch_register_class_t ${arch}_reg_classes[] = {\n\t".join(",\n\t", @regclasses)."\n};\n\n";
print OUT "arch_register_class_t ${arch}_reg_classes[] = {\n".join("",@regclasses)."\n};\n\n";
print OUT<<EOF;
......
......@@ -2292,31 +2292,32 @@ static ir_node *gen_Free(ir_node *node)
}
static const arch_register_req_t float1_req = {
arch_register_req_type_normal,
&sparc_reg_classes[CLASS_sparc_fp],
NULL,
0,
0,
1
.cls = &sparc_reg_classes[CLASS_sparc_fp],
.limited = NULL,
.type = arch_register_req_type_normal,
.other_same = 0,
.other_different = 0,
.width = 1,
};
static const arch_register_req_t float2_req = {
arch_register_req_type_normal | arch_register_req_type_aligned,
&sparc_reg_classes[CLASS_sparc_fp],
NULL,
0,
0,
2
.cls = &sparc_reg_classes[CLASS_sparc_fp],
.limited = NULL,
.type = arch_register_req_type_normal
| arch_register_req_type_aligned,
.other_same = 0,
.other_different = 0,
.width = 2,
};
static const arch_register_req_t float4_req = {
arch_register_req_type_normal | arch_register_req_type_aligned,
&sparc_reg_classes[CLASS_sparc_fp],
NULL,
0,
0,
4
.cls = &sparc_reg_classes[CLASS_sparc_fp],
.limited = NULL,
.type = arch_register_req_type_normal
| arch_register_req_type_aligned,
.other_same = 0,
.other_different = 0,
.width = 4,
};
static const arch_register_req_t *get_float_req(ir_mode *mode)
{
assert(mode_is_float(mode));
......
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