Commit 6b45fde8 authored by Matthias Braun's avatar Matthias Braun
Browse files

rework fragile ops to have a throws_exception attribute

parent b7dd849f
......@@ -143,10 +143,13 @@ ENUM_BITSET(ir_relation)
* constrained flags for memory operations.
*/
typedef enum ir_cons_flags {
cons_none = 0, /**< No constrains. */
cons_volatile = 1U << 0, /**< Memory operation is volatile. */
cons_unaligned = 1U << 1, /**< Memory operation is unaligned. */
cons_floats = 1U << 2 /**< Memory operation can float. */
cons_none = 0, /**< No constrains. */
cons_volatile = 1U << 0, /**< Memory operation is volatile. */
cons_unaligned = 1U << 1, /**< Memory operation is unaligned. */
cons_floats = 1U << 2, /**< Memory operation can float. */
cons_throws_exception = 1U << 3, /**< fragile op throws exception (and
produces X_regular and X_except
values) */
} ir_cons_flags;
ENUM_BITSET(ir_cons_flags)
......
......@@ -488,6 +488,17 @@ FIRM_API int is_x_except_Proj(const ir_node *node);
*/
FIRM_API int is_x_regular_Proj(const ir_node *node);
/**
* Set throws exception attribute of a fragile node
* @p throws_exception must be 0 or 1
*/
FIRM_API void ir_set_throws_exception(ir_node *node, int throws_exception);
/**
* Returns throws_exception attribute of a fragile node
*/
FIRM_API int ir_throws_exception(const ir_node *node);
/** returns the name of an ir_relation */
FIRM_API const char *get_relation_string(ir_relation relation);
......
......@@ -362,6 +362,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
int *reg_param_idxs;
int *stack_param_idx;
int i, n, destroy_all_regs;
int throws_exception;
size_t s;
size_t p;
dbg_info *dbgi;
......@@ -591,6 +592,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
assert(n_ins == (int) (n_reg_params + ARR_LEN(states)));
/* ins collected, build the call */
throws_exception = ir_throws_exception(irn);
if (env->call->flags.bits.call_has_imm && is_SymConst(call_ptr)) {
/* direct call */
low_call = be_new_Call(dbgi, irg, bl, curr_mem, curr_sp, curr_sp,
......@@ -603,6 +605,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
n_reg_results + pn_be_Call_first_res + ARR_LEN(destroyed_regs),
n_ins, in, get_Call_type(irn));
}
ir_set_throws_exception(low_call, throws_exception);
be_Call_set_pop(low_call, call->pop);
/* put the call into the list of all calls for later processing */
......@@ -616,9 +619,9 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
/* now handle results */
for (i = 0; i < n_res; ++i) {
int pn;
ir_node *proj = res_projs[i];
be_abi_call_arg_t *arg = get_call_arg(call, 1, i, 0);
long pn = i + pn_be_Call_first_res;
/* returns values on stack not supported yet */
assert(arg->in_reg);
......@@ -753,7 +756,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
}
if (! mem_proj) {
mem_proj = new_r_Proj(low_call, mode_M, pn_be_Call_M_regular);
mem_proj = new_r_Proj(low_call, mode_M, pn_be_Call_M);
keep_alive(mem_proj);
}
}
......
......@@ -1385,6 +1385,7 @@ void be_init_op(void)
op_be_Keep = new_ir_op(beo_Keep, "be_Keep", op_pin_state_exc_pinned, irop_flag_keep, oparity_dynamic, 0, sizeof(be_node_attr_t), &be_node_op_ops);
op_be_CopyKeep = new_ir_op(beo_CopyKeep, "be_CopyKeep", op_pin_state_exc_pinned, irop_flag_keep, oparity_variable, 0, sizeof(be_node_attr_t), &be_node_op_ops);
op_be_Call = new_ir_op(beo_Call, "be_Call", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_variable, 0, sizeof(be_call_attr_t), &be_node_op_ops);
ir_op_set_fragile_indices(op_be_Call, n_be_Call_mem, pn_be_Call_X_regular, pn_be_Call_X_except);
op_be_Return = new_ir_op(beo_Return, "be_Return", op_pin_state_exc_pinned, irop_flag_cfopcode, oparity_dynamic, 0, sizeof(be_return_attr_t), &be_node_op_ops);
op_be_AddSP = new_ir_op(beo_AddSP, "be_AddSP", op_pin_state_exc_pinned, irop_flag_none, oparity_unary, 0, sizeof(be_node_attr_t), &be_node_op_ops);
op_be_SubSP = new_ir_op(beo_SubSP, "be_SubSP", op_pin_state_exc_pinned, irop_flag_none, oparity_unary, 0, sizeof(be_node_attr_t), &be_node_op_ops);
......
......@@ -285,10 +285,11 @@ enum {
* Projection numbers for result of be_Call node: use for Proj nodes!
*/
typedef enum {
pn_be_Call_M_regular = pn_Call_M, /**< The memory result of a be_Call. */
pn_be_Call_M = pn_Call_M, /**< The memory result of a be_Call. */
pn_be_Call_X_regular = pn_Call_X_regular,
pn_be_Call_X_except = pn_Call_X_except,
pn_be_Call_sp = pn_Call_max+1,
pn_be_Call_first_res /**< The first result proj number of a
be_Call. */
pn_be_Call_first_res /**< The first result proj number of a be_Call. */
} pn_be_Call;
/**
......
......@@ -889,6 +889,7 @@ static void transform_to_Store(ir_node *node)
ir_node *nomem = get_irg_no_mem(irg);
ir_node *ptr = get_irg_frame(irg);
ir_node *val = get_irn_n(node, n_be_Spill_val);
ir_node *res;
ir_node *store;
ir_node *sched_point = NULL;
......@@ -897,17 +898,23 @@ static void transform_to_Store(ir_node *node)
}
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2)
if (ia32_cg_config.use_sse2) {
store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
else
res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
} else {
store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
}
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
} else if (get_mode_size_bits(mode) == 8) {
store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
} else {
store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
}
set_ia32_op_type(store, ia32_AddrModeD);
......@@ -923,7 +930,7 @@ static void transform_to_Store(ir_node *node)
sched_remove(node);
}
exchange(node, store);
exchange(node, res);
}
static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
......
......@@ -751,6 +751,7 @@ ir_node *ia32_gen_CopyB(ir_node *node)
ir_node *res = NULL;
dbg_info *dbgi = get_irn_dbg_info(node);
int size = get_type_size_bytes(get_CopyB_type(node));
int throws_exception = ir_throws_exception(node);
int rem;
/* If we have to copy more than 32 bytes, we use REP MOVSx and */
......@@ -769,6 +770,7 @@ ir_node *ia32_gen_CopyB(ir_node *node)
}
res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
}
ir_set_throws_exception(res, throws_exception);
SET_IA32_ORIG_NODE(res, node);
......
......@@ -173,6 +173,7 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
ir_node *nomem = get_irg_no_mem(irg);
ir_node *cwstore, *load, *load_res, *orn, *store, *fldcw;
ir_node *store_proj;
ir_node *or_const;
assert(last_state != NULL);
......@@ -204,9 +205,10 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
/* use mode_Iu, as movl has a shorter opcode than movw */
set_ia32_ls_mode(store, mode_Iu);
set_ia32_use_frame(store);
store_proj = new_r_Proj(store, mode_M, pn_ia32_Store_M);
sched_add_before(before, store);
fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store);
fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store_proj);
set_ia32_op_type(fldcw, ia32_AddrModeS);
set_ia32_ls_mode(fldcw, lsmode);
set_ia32_use_frame(fldcw);
......
......@@ -483,12 +483,15 @@ static void peephole_IncSP_Store_to_push(ir_node *irn)
ir_node *val, *mem, *mem_proj;
ir_node *store = stores[i];
ir_node *noreg = ia32_new_NoReg_gp(irg);
const ir_edge_t *edge;
const ir_edge_t *next;
val = get_irn_n(store, n_ia32_unary_op);
mem = get_irn_n(store, n_ia32_mem);
spreg = arch_get_irn_register(curr_sp);
push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
mem, val, curr_sp);
copy_mark(store, push);
if (first_push == NULL)
......@@ -503,8 +506,22 @@ static void peephole_IncSP_Store_to_push(ir_node *irn)
/* create memory Proj */
mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
/* rewire Store Projs */
foreach_out_edge_safe(store, edge, next) {
ir_node *proj = get_edge_src_irn(edge);
if (!is_Proj(proj))
continue;
switch (get_Proj_proj(proj)) {
case pn_ia32_Store_M:
exchange(proj, mem_proj);
break;
default:
panic("unexpected Proj on Store->IncSp");
}
}
/* use the memproj now */
be_peephole_exchange(store, mem_proj);
be_peephole_exchange(store, push);
inc_ofs -= 4;
}
......
......@@ -1221,7 +1221,6 @@ Store => {
emit => '. mov%M %SI3, %AM',
latency => 2,
units => [ "GP" ],
mode => "mode_M",
},
Store8Bit => {
......@@ -1234,7 +1233,6 @@ Store8Bit => {
emit => '. mov%M %SB3, %AM',
latency => 2,
units => [ "GP" ],
mode => "mode_M",
},
Lea => {
......@@ -1436,13 +1434,14 @@ Popcnt => {
},
Call => {
op_flags => [ "fragile" ],
state => "exc_pinned",
reg_req => {
in => [ "gp", "gp", "none", "gp", "esp", "fpcw", "eax", "ecx", "edx" ],
out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ]
out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "none", "none" ]
},
ins => [ "base", "index", "mem", "addr", "stack", "fpcw", "eax", "ecx", "edx" ],
outs => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ],
outs => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "X_regular", "X_except" ],
attr_type => "ia32_call_attr_t",
attr => "unsigned pop, ir_type *call_tp",
am => "source,unary",
......@@ -1882,7 +1881,6 @@ xStore => {
emit => '. mov%XXM %S3, %AM',
latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
xStoreSimple => {
......@@ -1895,7 +1893,6 @@ xStoreSimple => {
emit => '. mov%XXM %S3, %AM',
latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
CvtSI2SS => {
......@@ -1980,11 +1977,12 @@ Cwtl => {
},
Conv_I2I => {
op_flags => [ "fragile" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp" ],
out => [ "gp", "none", "none" ] },
out => [ "gp", "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "res", "flags", "M" ],
outs => [ "res", "flags", "M", "X_regular", "X_except" ],
am => "source,unary",
units => [ "GP" ],
latency => 1,
......@@ -1994,11 +1992,12 @@ Conv_I2I => {
},
Conv_I2I8Bit => {
op_flags => [ "fragile" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ],
out => [ "gp", "none", "none" ] },
out => [ "gp", "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "res", "flags", "M" ],
outs => [ "res", "flags", "M", "X_regular", "X_except" ],
am => "source,unary",
units => [ "GP" ],
latency => 1,
......@@ -2150,7 +2149,6 @@ vfst => {
init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
units => [ "VFP" ],
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
......@@ -2166,22 +2164,25 @@ vfild => {
},
vfist => {
op_flags => [ "fragile" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ], out => [ "none" ] },
reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ],
out => [ "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val", "fpcw" ],
outs => [ "M" ],
outs => [ "dummy", "M", "X_regular", "X_except" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
# SSE3 fisttp instruction
vfisttp => {
op_flags => [ "fragile" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "in_r4", "none" ]},
reg_req => { in => [ "gp", "gp", "none", "vfp" ],
out => [ "in_r4", "none", "none", "none" ]},
ins => [ "base", "index", "mem", "val" ],
outs => [ "res", "M" ],
outs => [ "res", "M", "X_regular", "X_except" ],
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
......@@ -2720,7 +2721,6 @@ xxStore => {
emit => '. movdqu %binop',
units => [ "SSE" ],
latency => 1,
mode => "mode_M",
},
); # end of %nodes
......
This diff is collapsed.
......@@ -1328,6 +1328,20 @@ int is_x_regular_Proj(const ir_node *node)
return get_Proj_proj(node) == pred->op->pn_x_regular;
}
void ir_set_throws_exception(ir_node *node, int throws_exception)
{
except_attr *attr = &node->attr.except;
assert(is_fragile_op(node));
attr->throws_exception = throws_exception;
}
int ir_throws_exception(const ir_node *node)
{
const except_attr *attr = &node->attr.except;
assert(is_fragile_op(node));
return attr->throws_exception;
}
ir_node **get_Tuple_preds_arr(ir_node *node)
{
assert(is_Tuple(node));
......@@ -1524,6 +1538,9 @@ int (is_SymConst_addr_ent)(const ir_node *node)
/* Returns true if the operation manipulates control flow. */
int is_cfop(const ir_node *node)
{
if (is_fragile_op(node) && ir_throws_exception(node))
return true;
return is_op_cfopcode(get_irn_op(node));
}
......
......@@ -327,7 +327,7 @@ static inline op_pin_state _get_irn_pinned(const ir_node *node)
state = _get_op_pinned(_get_irn_op(node));
if (state >= op_pin_state_exc_pinned)
return node->attr.except.pin_state;
return (op_pin_state)node->attr.except.pin_state;
return state;
}
......
......@@ -5833,7 +5833,7 @@ static ir_node *transform_node_Load(ir_node *n)
ir_node *bad = new_r_Bad(irg, mode_X);
ir_mode *mode = get_Load_mode(n);
ir_node *res = new_r_Proj(pred_load, mode, pn_Load_res);
ir_node *in[pn_Load_max+1] = { mem, jmp, bad, res };
ir_node *in[pn_Load_max+1] = { mem, res, jmp, bad };
ir_node *tuple = new_r_Tuple(block, ARRAY_SIZE(in), in);
return tuple;
}
......@@ -5853,7 +5853,7 @@ static ir_node *transform_node_Load(ir_node *n)
ir_graph *irg = get_irn_irg(n);
ir_node *bad = new_r_Bad(irg, mode_X);
ir_node *res = value;
ir_node *in[pn_Load_max+1] = { mem, jmp, bad, res };
ir_node *in[pn_Load_max+1] = { mem, res, jmp, bad };
ir_node *tuple = new_r_Tuple(block, ARRAY_SIZE(in), in);
return tuple;
}
......
......@@ -202,9 +202,12 @@ typedef struct sel_attr {
/** Exception attributes. */
typedef struct except_attr {
op_pin_state pin_state; /**< the pin state for operations that might generate a exception:
If it's know that no exception will be generated, could be set to
op_pin_state_floats. */
unsigned pin_state : 2; /**< the pin state for operations with
variable pinned state. Contains a
op_pin_state */
unsigned throws_exception : 1; /**< if true a fragile op throws and
must produce X_except and X_regular
values */
} except_attr;
/** Call attributes. */
......
......@@ -733,6 +733,17 @@ static int verify_node_Proj_Bound(const ir_node *p)
return 1;
}
static int verify_node_Proj_fragile(const ir_node *node)
{
ir_node *pred = get_Proj_pred(node);
int throws_exception = ir_throws_exception(pred);
ASSERT_AND_RET((!is_x_except_Proj(node) || throws_exception)
&& (!is_x_regular_Proj(node) || throws_exception),
"X_except und X_regular Proj only allowed when throws_exception is set",
0);
return 1;
}
/**
* verify a Proj node
*/
......@@ -746,6 +757,12 @@ static int verify_node_Proj(const ir_node *p)
ASSERT_AND_RET(get_irn_mode(pred) == mode_T, "mode of a 'projed' node is not Tuple", 0);
ASSERT_AND_RET(get_irg_pinned(irg) == op_pin_state_floats || get_nodes_block(pred) == get_nodes_block(p), "Proj must be in same block as its predecessor", 0);
if (is_fragile_op(pred)) {
int res = verify_node_Proj_fragile(p);
if (res != 1)
return res;
}
op = get_irn_op(pred);
if (op->ops.verify_proj_node)
return op->ops.verify_proj_node(p);
......
......@@ -209,28 +209,34 @@ ir_prog_pass_t *lower_intrinsics_pass(
* @param reg_jmp new regular control flow, if NULL, a Jmp will be used
* @param exc_jmp new exception control flow, if reg_jmp == NULL, a Bad will be used
*/
static void replace_call(ir_node *irn, ir_node *call, ir_node *mem, ir_node *reg_jmp, ir_node *exc_jmp)
static void replace_call(ir_node *irn, ir_node *call, ir_node *mem,
ir_node *reg_jmp, ir_node *exc_jmp)
{
ir_node *block = get_nodes_block(call);
ir_graph *irg = get_irn_irg(block);
ir_node *rest = new_r_Tuple(block, 1, &irn);
if (reg_jmp == NULL) {
/* Beware: do we need here a protection against CSE? Better we do it. */
int old_cse = get_opt_cse();
set_opt_cse(0);
reg_jmp = new_r_Jmp(block);
set_opt_cse(old_cse);
exc_jmp = new_r_Bad(irg, mode_X);
if (ir_throws_exception(call)) {
turn_into_tuple(call, pn_Call_max+1);
if (reg_jmp == NULL) {
reg_jmp = new_r_Jmp(block);
}
if (exc_jmp == NULL) {
exc_jmp = new_r_Bad(irg, mode_X);
}
set_Tuple_pred(call, pn_Call_X_regular, reg_jmp);
set_Tuple_pred(call, pn_Call_X_except, exc_jmp);
} else {
assert(reg_jmp == NULL);
assert(exc_jmp == NULL);
turn_into_tuple(call, pn_Call_T_result+1);
assert(pn_Call_M <= pn_Call_T_result);
assert(pn_Call_X_regular > pn_Call_T_result);
assert(pn_Call_X_except > pn_Call_T_result);
}
irn = new_r_Tuple(block, 1, &irn);
turn_into_tuple(call, pn_Call_max+1);
set_Tuple_pred(call, pn_Call_M, mem);
set_Tuple_pred(call, pn_Call_X_regular, reg_jmp);
set_Tuple_pred(call, pn_Call_X_except, exc_jmp);
set_Tuple_pred(call, pn_Call_T_result, irn);
} /* replace_call */
set_Tuple_pred(call, pn_Call_T_result, rest);
}
/* A mapper for the integer abs. */
int i_mapper_abs(ir_node *call, void *ctx)
......@@ -298,9 +304,15 @@ int i_mapper_alloca(ir_node *call, void *ctx)
irn = new_rd_Alloc(dbg, block, mem, op, firm_unknown_type, stack_alloc);
mem = new_rd_Proj(dbg, irn, mode_M, pn_Alloc_M);
no_exc = new_rd_Proj(dbg, irn, mode_X, pn_Alloc_X_regular);
exc = new_rd_Proj(dbg, irn, mode_X, pn_Alloc_X_except);
irn = new_rd_Proj(dbg, irn, get_modeP_data(), pn_Alloc_res);
if (ir_throws_exception(call)) {
no_exc = new_rd_Proj(dbg, irn, mode_X, pn_Alloc_X_regular);
exc = new_rd_Proj(dbg, irn, mode_X, pn_Alloc_X_except);
ir_set_throws_exception(irn, true);
} else {
no_exc = NULL;
exc = NULL;
}
DBG_OPT_ALGSIM0(call, irn, FS_OPT_RTS_ALLOCA);
replace_call(irn, call, mem, no_exc, exc);
......@@ -356,13 +368,15 @@ int i_mapper_cbrt(ir_node *call, void *ctx)
/* A mapper for the floating point pow. */
int i_mapper_pow(ir_node *call, void *ctx)
{
ir_node *left = get_Call_param(call, 0);
ir_node *right = get_Call_param(call, 1);
ir_node *block = get_nodes_block(call);
ir_graph *irg = get_irn_irg(block);
ir_node *reg_jmp = NULL;
ir_node *exc_jmp = NULL;
ir_node *irn;
dbg_info *dbg;
ir_node *mem;
ir_node *left = get_Call_param(call, 0);
ir_node *right = get_Call_param(call, 1);
ir_node *block = get_nodes_block(call);
ir_graph *irg = get_irn_irg(block);
ir_node *irn, *reg_jmp = NULL, *exc_jmp = NULL;
(void) ctx;
if (is_Const(left) && is_Const_one(left)) {
......@@ -397,8 +411,11 @@ int i_mapper_pow(ir_node *call, void *ctx)
div = new_rd_Div(dbg, block, mem, irn, left, mode, op_pin_state_pinned);
mem = new_r_Proj(div, mode_M, pn_Div_M);
irn = new_r_Proj(div, mode, pn_Div_res);
reg_jmp = new_r_Proj(div, mode_X, pn_Div_X_regular);
exc_jmp = new_r_Proj(div, mode_X, pn_Div_X_except);
if (ir_throws_exception(call)) {
reg_jmp = new_r_Proj(div, mode_X, pn_Div_X_regular);
exc_jmp = new_r_Proj(div, mode_X, pn_Div_X_except);
ir_set_throws_exception(div, true);
}
}
DBG_OPT_ALGSIM0(call, irn, FS_OPT_RTS_POW);
replace_call(irn, call, mem, reg_jmp, exc_jmp);
......@@ -919,9 +936,15 @@ replace_by_call:
/* replace the strcmp by (*x) */
irn = new_rd_Load(dbg, block, mem, v, mode, cons_none);
mem = new_r_Proj(irn, mode_M, pn_Load_M);
exc = new_r_Proj(irn, mode_X, pn_Load_X_except);
reg = new_r_Proj(irn, mode_X, pn_Load_X_regular);
irn = new_r_Proj(irn, mode, pn_Load_res);
if (ir_throws_exception(call)) {
exc = new_r_Proj(irn, mode_X, pn_Load_X_except);
reg = new_r_Proj(irn, mode_X, pn_Load_X_regular);
ir_set_throws_exception(irn, true);
} else {
exc = NULL;
reg = NULL;
}
/* conv to the result mode */
mode = get_type_mode(res_tp);
......
......@@ -272,6 +272,11 @@ def preprocess_node(node):
fqname = ".exc.pin_state",
init = "pin_state"
))
if hasattr(node, "throws_init"):
initattrs.append(dict(
fqname = ".exc.throws_exception",
init = node.throws_init
))
for arg in node.constructor_args:
arguments.append(prepare_attr(arg))
......
......@@ -39,9 +39,9 @@ class Alloc(Op):
]
outs = [
("M", "memory result"),
("res", "pointer to newly allocated memory"),
("X_regular", "control flow when no exception occurs"),
("X_except", "control flow when exception occured"),
("res", "pointer to newly allocated memory"),
]