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Commit 6d660d16 authored by Christoph Mallon's avatar Christoph Mallon
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Generate new_bd_* instead of new_rd_* functions in the backend. The nodes are... 

Generate new_bd_* instead of new_rd_* functions in the backend.  The nodes are always created on the current irg.

[r23535]
parent 64885e8b
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Inline Side-by-side
ir/be/TEMPLATE/TEMPLATE_transform.c
View file @ 6d660d16
......@@ -68,7 +68,7 @@ extern ir_op *get_op_Mulh(void);
* @return the created TEMPLATE Add node
*/
static ir_node *gen_Add(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_TEMPLATE_Add(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_Add(env->dbg, env->block, op1, op2, env->mode);
}
......@@ -85,10 +85,10 @@ static ir_node *gen_Add(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op
*/
static ir_node *gen_Mul(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
if (mode_is_float(env->mode)) {
return new_rd_TEMPLATE_fMul(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_fMul(env->dbg, env->block, op1, op2, env->mode);
}
else {
return new_rd_TEMPLATE_Mul(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_Mul(env->dbg, env->block, op1, op2, env->mode);
}
}
......@@ -105,7 +105,7 @@ static ir_node *gen_Mul(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op
* @return the created TEMPLATE And node
*/
static ir_node *gen_And(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_TEMPLATE_And(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_And(env->dbg, env->block, op1, op2, env->mode);
}
......@@ -121,7 +121,7 @@ static ir_node *gen_And(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op
* @return the created TEMPLATE Or node
*/
static ir_node *gen_Or(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_TEMPLATE_Or(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_Or(env->dbg, env->block, op1, op2, env->mode);
}
......@@ -137,7 +137,7 @@ static ir_node *gen_Or(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2
* @return the created TEMPLATE Eor node
*/
static ir_node *gen_Eor(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_TEMPLATE_Eor(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_Eor(env->dbg, env->block, op1, op2, env->mode);
}
......@@ -154,10 +154,10 @@ static ir_node *gen_Eor(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op
*/
static ir_node *gen_Sub(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
if (mode_is_float(env->mode)) {
return new_rd_TEMPLATE_fSub(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_fSub(env->dbg, env->block, op1, op2, env->mode);
}
else {
return new_rd_TEMPLATE_Sub(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_Sub(env->dbg, env->block, op1, op2, env->mode);
}
}
......@@ -174,7 +174,7 @@ static ir_node *gen_Sub(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op
* @return the created TEMPLATE fDiv node
*/
static ir_node *gen_Quot(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_TEMPLATE_fDiv(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_fDiv(env->dbg, env->block, op1, op2, env->mode);
}
......@@ -190,7 +190,7 @@ static ir_node *gen_Quot(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *o
* @return the created TEMPLATE Shl node
*/
static ir_node *gen_Shl(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_TEMPLATE_Shl(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_Shl(env->dbg, env->block, op1, op2, env->mode);
}
......@@ -206,7 +206,7 @@ static ir_node *gen_Shl(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op
* @return the created TEMPLATE Shr node
*/
static ir_node *gen_Shr(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_TEMPLATE_Shr(env->dbg, env->irg, env->block, op1, op2, env->mode);
return new_bd_TEMPLATE_Shr(env->dbg, env->block, op1, op2, env->mode);
}
......@@ -223,9 +223,9 @@ static ir_node *gen_Shr(TEMPLATE_transform_env_t *env, ir_node *op1, ir_node *op
*/
static ir_node *gen_Minus(TEMPLATE_transform_env_t *env, ir_node *op) {
if (mode_is_float(env->mode)) {
return new_rd_TEMPLATE_fMinus(env->dbg, env->irg, env->block, op, env->mode);
return new_bd_TEMPLATE_fMinus(env->dbg, env->block, op, env->mode);
}
return new_rd_TEMPLATE_Minus(env->dbg, env->irg, env->block, op, env->mode);
return new_bd_TEMPLATE_Minus(env->dbg, env->block, op, env->mode);
}
......@@ -241,7 +241,7 @@ static ir_node *gen_Minus(TEMPLATE_transform_env_t *env, ir_node *op) {
* @return the created TEMPLATE Not node
*/
static ir_node *gen_Not(TEMPLATE_transform_env_t *env, ir_node *op) {
return new_rd_TEMPLATE_Not(env->dbg, env->irg, env->block, op, env->mode);
return new_bd_TEMPLATE_Not(env->dbg, env->block, op, env->mode);
}
......@@ -259,9 +259,9 @@ static ir_node *gen_Load(TEMPLATE_transform_env_t *env) {
ir_node *node = env->irn;
if (mode_is_float(env->mode)) {
return new_rd_TEMPLATE_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
return new_bd_TEMPLATE_fLoad(env->dbg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
}
return new_rd_TEMPLATE_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
return new_bd_TEMPLATE_Load(env->dbg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
}
......@@ -279,9 +279,9 @@ static ir_node *gen_Store(TEMPLATE_transform_env_t *env) {
ir_node *node = env->irn;
if (mode_is_float(env->mode)) {
return new_rd_TEMPLATE_fStore(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
return new_bd_TEMPLATE_fStore(env->dbg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
}
return new_rd_TEMPLATE_Store(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
return new_bd_TEMPLATE_Store(env->dbg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
}
......
ir/be/arm/arm_optimize.c
View file @ 6d660d16
......@@ -149,19 +149,18 @@ static void peephole_be_IncSP(ir_node *node) {
*/
static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
{
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
int cnt;
ir_node *ptr;
ptr = new_rd_arm_Add_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
ptr = new_bd_arm_Add_i(dbg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
sched_add_before(node, ptr);
for (cnt = 1; cnt < v->ops; ++cnt) {
long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
ir_node *next = new_rd_arm_Add_i(dbg, irg, block, ptr, mode_Iu, value);
ir_node *next = new_bd_arm_Add_i(dbg, block, ptr, mode_Iu, value);
arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
sched_add_before(node, next);
ptr = next;
......@@ -174,19 +173,18 @@ static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
*/
static ir_node *gen_ptr_sub(ir_node *node, ir_node *frame, arm_vals *v)
{
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
int cnt;
ir_node *ptr;
ptr = new_rd_arm_Sub_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
ptr = new_bd_arm_Sub_i(dbg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
sched_add_before(node, ptr);
for (cnt = 1; cnt < v->ops; ++cnt) {
long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
ir_node *next = new_rd_arm_Sub_i(dbg, irg, block, ptr, mode_Iu, value);
ir_node *next = new_bd_arm_Sub_i(dbg, block, ptr, mode_Iu, value);
arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
sched_add_before(node, next);
ptr = next;
......@@ -229,14 +227,14 @@ static void peephole_be_Spill(ir_node *node) {
if (mode_is_float(mode)) {
if (USE_FPA(cg->isa)) {
/* transform into fpaStf */
store = new_rd_arm_fpaStf(dbg, irg, block, ptr, value, get_irg_no_mem(irg), mode);
store = new_bd_arm_fpaStf(dbg, block, ptr, value, get_irg_no_mem(irg), mode);
sched_add_before(node, store);
} else {
panic("peephole_be_Spill: spill not supported for this mode");
}
} else if (mode_is_dataM(mode)) {
/* transform into Store */;
store = new_rd_arm_Store(dbg, irg, block, ptr, value, get_irg_no_mem(irg));
store = new_bd_arm_Store(dbg, block, ptr, value, get_irg_no_mem(irg));
sched_add_before(node, store);
} else {
panic("peephole_be_Spill: spill not supported for this mode");
......@@ -282,7 +280,7 @@ static void peephole_be_Reload(ir_node *node) {
if (mode_is_float(mode)) {
if (USE_FPA(cg->isa)) {
/* transform into fpaLdf */
load = new_rd_arm_fpaLdf(dbg, irg, block, ptr, mem, mode);
load = new_bd_arm_fpaLdf(dbg, block, ptr, mem, mode);
sched_add_before(node, load);
proj = new_rd_Proj(dbg, irg, block, load, mode, pn_arm_fpaLdf_res);
arch_set_irn_register(proj, reg);
......@@ -291,7 +289,7 @@ static void peephole_be_Reload(ir_node *node) {
}
} else if (mode_is_dataM(mode)) {
/* transform into Store */;
load = new_rd_arm_Load(dbg, irg, block, ptr, mem);
load = new_bd_arm_Load(dbg, block, ptr, mem);
sched_add_before(node, load);
proj = new_rd_Proj(dbg, irg, block, load, mode_Iu, pn_arm_Load_res);
arch_set_irn_register(proj, reg);
......
ir/be/arm/arm_transform.c
View file @ 6d660d16
This diff is collapsed.
ir/be/arm/bearch_arm.c
View file @ 6d660d16
......@@ -300,7 +300,7 @@ static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
ir_graph *irg = current_ir_graph;
ir_node *conv;
conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
conv = new_bd_arm_fpaDbl2GP(NULL, bl, arg, mem);
/* move high/low */
*resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
*resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
......@@ -832,7 +832,7 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
ip = be_new_Copy(gp, irg, block, sp);
be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], arch_register_req_type_produces_sp);
store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
store = new_bd_arm_StoreStackM4Inc(NULL, block, sp, fp, ip, lr, pc, *mem);
sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
arch_set_irn_register(sp, env->arch_env->sp);
......@@ -842,7 +842,7 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
be_node_set_reg_class_in(keep, 1, gp);
be_set_constr_single_reg_out(keep, 0, &arm_gp_regs[REG_R12], arch_register_req_type_produces_sp);
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
fp = new_bd_arm_Sub_i(NULL, block, keep, get_irn_mode(fp), 4);
arch_set_irn_register(fp, env->arch_env->bp);
fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ have custom register requirements
be_set_constr_single_reg_out(fp, 0, env->arch_env->bp, 0);
......@@ -878,11 +878,11 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
} else {
ir_node *sub12_node;
ir_node *load_node;
sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
sub12_node = new_bd_arm_Sub_i(NULL, bl, curr_bp, mode_Iu, 12);
// FIXME
//set_arm_req_out_all(sub12_node, sub12_req);
arch_set_irn_register(sub12_node, env->arch_env->sp);
load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
load_node = new_bd_arm_LoadStackM3(NULL, bl, sub12_node, *mem);
// FIXME
//set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
//set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
......
ir/be/ia32/bearch_ia32.c
View file @ 6d660d16
......@@ -119,7 +119,7 @@ static ia32_intrinsic_env_t intrinsic_env = {
};
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
create_const_node_func func,
......@@ -131,7 +131,7 @@ static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
return *place;
block = get_irg_start_block(cg->irg);
res = func(NULL, cg->irg, block);
res = func(NULL, block);
arch_set_irn_register(res, reg);
*place = res;
......@@ -143,37 +143,37 @@ static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
/* Creates the unique per irg GP NoReg node. */
ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
&ia32_gp_regs[REG_GP_NOREG]);
}
ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
&ia32_vfp_regs[REG_VFP_NOREG]);
}
ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
&ia32_xmm_regs[REG_XMM_NOREG]);
}
ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
&ia32_gp_regs[REG_GP_UKNWN]);
}
ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
&ia32_vfp_regs[REG_VFP_UKNWN]);
}
ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
&ia32_xmm_regs[REG_XMM_UKNWN]);
}
ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
&ia32_fp_cw_regs[REG_FPCW]);
}
......@@ -355,7 +355,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
/* push ebp */
push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
*mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
......@@ -412,7 +412,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
ir_node *leave;
/* leave */
leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
} else {
......@@ -429,7 +429,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
arch_register_req_type_ignore);
/* pop ebp */
pop = new_rd_ia32_PopEbp(NULL, env->irg, bl, *mem, curr_sp);
pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
......@@ -570,7 +570,6 @@ static int ia32_get_op_estimated_cost(const ir_node *irn)
* @return The inverse operation or NULL if operation invertible
*/
static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
ir_graph *irg;
ir_mode *mode;
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
......@@ -593,7 +592,6 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
irn);
return NULL;
irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_irn_mode(irn);
irn_mode = get_irn_mode(irn);
......@@ -612,7 +610,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
......@@ -621,13 +619,13 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
#endif
......@@ -637,17 +635,17 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
if (i == n_ia32_binary_left) {
inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
......@@ -657,24 +655,24 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
#endif
break;
case iro_ia32_Not: {
inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
......@@ -935,7 +933,7 @@ ir_node *turn_back_am(ir_node *node)
ir_node *mem = get_irn_n(node, n_ia32_mem);
ir_node *noreg;
ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
......@@ -1061,16 +1059,16 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
if (mode_is_float(spillmode)) {
if (ia32_cg_config.use_sse2)
new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
else
new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
/* Reload 128 bit SSE registers */
new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
}
else
new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_ls_mode(new_op, spillmode);
......@@ -1131,16 +1129,16 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2)
store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
else
store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
} else if (get_mode_size_bits(mode) == 8) {
store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
} else {
store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
}
set_ia32_op_type(store, ia32_AddrModeD);
......@@ -1160,13 +1158,13 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
}
static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
ir_graph *irg = get_irn_irg(node);
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_graph *irg = get_irn_irg(node);
ir_node *frame = get_irg_frame(irg);
ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
......@@ -1179,13 +1177,13 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo
}
static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
ir_graph *irg = get_irn_irg(node);
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_graph *irg = get_irn_irg(node);
ir_node *frame = get_irg_frame(irg);
ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
......@@ -1478,7 +1476,7 @@ static ir_node *ia32_get_pic_base(void *self) {
return get_eip;
block = get_irg_start_block(cg->irg);
get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
get_eip = new_bd_ia32_GetEIP(NULL, block);
cg->get_eip = get_eip;
be_dep_on_frame(get_eip);
......
ir/be/ia32/ia32_common_transform.c
View file @ 6d660d16
......@@ -169,8 +169,8 @@ ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
{
ir_graph *irg = current_ir_graph;
ir_node *start_block = get_irg_start_block(irg);
ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
symconst, symconst_sign, val);
ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
symconst_sign, val);
arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
return immediate;
......@@ -439,7 +439,6 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c,
ir_node *gen_ASM(ir_node *node)
{
ir_graph *irg = current_ir_graph;
ir_node *block = NULL;
ir_node *new_block = NULL;
dbg_info *dbgi = get_irn_dbg_info(node);
......@@ -527,7 +526,7 @@ ir_node *gen_ASM(ir_node *node)
}
++reg_map_size;
obst = get_irg_obstack(irg);
obst = get_irg_obstack(current_ir_graph);
register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
......@@ -637,7 +636,7 @@ ir_node *gen_ASM(ir_node *node)
++out_idx;
}
new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
get_ASM_text(node), register_map);
if (arity == 0)
......@@ -660,7 +659,6 @@ ir_node *gen_CopyB(ir_node *node) {
ir_node *mem = NULL;
ir_node *new_mem = NULL;
ir_node *res = NULL;
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
int size = get_type_size_bytes(get_CopyB_type(node));
int rem;
......@@ -695,16 +693,16 @@ ir_node *gen_CopyB(ir_node *node) {
rem = size & 0x3; /* size % 4 */
size >>= 2;
res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
res = new_bd_ia32_Const(dbgi, block, NULL, 0, size);
be_dep_on_frame(res);
res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
} else {
if(size == 0) {
ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
node);
}
res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
}
SET_IA32_ORIG_NODE(res, node);
......@@ -714,7 +712,6 @@ ir_node *gen_CopyB(ir_node *node) {
ir_node *gen_Proj_tls(ir_node *node) {
ir_node *block = NULL;
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = NULL;
ir_node *res = NULL;
......@@ -733,7 +730,7 @@ ir_node *gen_Proj_tls(ir_node *node) {
default: panic("invalid transformer");
}