Commit 6e0675a0 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

be: Remove the write-only attribute bp from struct arch_env_t.

parent 896b2539
...@@ -111,7 +111,6 @@ static TEMPLATE_isa_t TEMPLATE_isa_template = { ...@@ -111,7 +111,6 @@ static TEMPLATE_isa_t TEMPLATE_isa_template = {
.n_register_classes = N_TEMPLATE_CLASSES, .n_register_classes = N_TEMPLATE_CLASSES,
.register_classes = TEMPLATE_reg_classes, .register_classes = TEMPLATE_reg_classes,
.sp = &TEMPLATE_registers[REG_SP], .sp = &TEMPLATE_registers[REG_SP],
.bp = &TEMPLATE_registers[REG_BP],
.spill_cost = 7, .spill_cost = 7,
.reload_cost = 5, .reload_cost = 5,
}, },
......
...@@ -654,7 +654,6 @@ static amd64_isa_t amd64_isa_template = { ...@@ -654,7 +654,6 @@ static amd64_isa_t amd64_isa_template = {
.n_register_classes = N_AMD64_CLASSES, .n_register_classes = N_AMD64_CLASSES,
.register_classes = amd64_reg_classes, .register_classes = amd64_reg_classes,
.sp = &amd64_registers[REG_RSP], .sp = &amd64_registers[REG_RSP],
.bp = &amd64_registers[REG_RBP],
.spill_cost = 7, .spill_cost = 7,
.reload_cost = 5, .reload_cost = 5,
}, },
......
...@@ -249,7 +249,6 @@ static arm_isa_t arm_isa_template = { ...@@ -249,7 +249,6 @@ static arm_isa_t arm_isa_template = {
.n_register_classes = N_ARM_CLASSES, .n_register_classes = N_ARM_CLASSES,
.register_classes = arm_reg_classes, .register_classes = arm_reg_classes,
.sp = &arm_registers[REG_SP], .sp = &arm_registers[REG_SP],
.bp = &arm_registers[REG_R11],
.spill_cost = 7, .spill_cost = 7,
.reload_cost = 5, .reload_cost = 5,
}, },
......
...@@ -450,7 +450,6 @@ struct arch_env_t { ...@@ -450,7 +450,6 @@ struct arch_env_t {
/** register classes */ /** register classes */
const arch_register_class_t *register_classes; const arch_register_class_t *register_classes;
const arch_register_t *sp; /**< The stack pointer register. */ const arch_register_t *sp; /**< The stack pointer register. */
const arch_register_t *bp; /**< The base pointer register. */
unsigned spill_cost; /**< cost for a be_Spill node */ unsigned spill_cost; /**< cost for a be_Spill node */
unsigned reload_cost; /**< cost for a be_Reload node */ unsigned reload_cost; /**< cost for a be_Reload node */
}; };
......
...@@ -1565,7 +1565,6 @@ static ia32_isa_t ia32_isa_template = { ...@@ -1565,7 +1565,6 @@ static ia32_isa_t ia32_isa_template = {
.n_register_classes = N_IA32_CLASSES, .n_register_classes = N_IA32_CLASSES,
.register_classes = ia32_reg_classes, .register_classes = ia32_reg_classes,
.sp = &ia32_registers[REG_ESP], .sp = &ia32_registers[REG_ESP],
.bp = &ia32_registers[REG_EBP],
.spill_cost = 7, .spill_cost = 7,
.reload_cost = 5, .reload_cost = 5,
}, },
......
...@@ -64,7 +64,6 @@ static sparc_isa_t sparc_isa_template = { ...@@ -64,7 +64,6 @@ static sparc_isa_t sparc_isa_template = {
.n_register_classes = N_SPARC_CLASSES, .n_register_classes = N_SPARC_CLASSES,
.register_classes = sparc_reg_classes, .register_classes = sparc_reg_classes,
.sp = &sparc_registers[REG_SP], .sp = &sparc_registers[REG_SP],
.bp = &sparc_registers[REG_FRAME_POINTER],
.spill_cost = 7, .spill_cost = 7,
.reload_cost = 5, .reload_cost = 5,
}, },
......
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