fixed a bunch of warnings

[r16181]

ir/be/TEMPLATE/TEMPLATE_transform.c

@@ -308,10 +308,13 @@ static ir_node *gen_Store(TEMPLATE_transform_env_t *env) {
  * @param env     the debug module
  */
 void TEMPLATE_transform_node(ir_node *node, void *env) {
+#ifdef DEBUG_libfirm
 	TEMPLATE_code_gen_t *cgenv = (TEMPLATE_code_gen_t *)env;
+#endif
 	ir_opcode code             = get_irn_opcode(node);
 	ir_node *asm_node          = NULL;
 	TEMPLATE_transform_env_t tenv;
+	(void) env;
 
 	if (is_Block(node))
 		return;

ir/be/beilpsched.c

@@ -689,6 +689,7 @@ static void refine_asap_alap_times(ir_node *irn, void *walk_env) {
 
 static INLINE void check_for_keeps(waitq *keeps, ir_node *block, ir_node *irn) {
 	const ir_edge_t *edge;
+        (void) block;
 
 	foreach_out_edge(irn, edge) {
 		ir_node *user = get_edge_src_irn(edge);
@@ -1871,6 +1872,7 @@ static void create_ilp(ir_node *block, void *walk_env) {
 
 		DBG((env->dbg, LEVEL_1, "Creating LPP with estimated numbers: %d vars, %d cst\n",
 			estimated_n_var, estimated_n_cst));
+                (void) estimated_n_var;
 
 		/* set up the LPP object */
 		snprintf(name, sizeof(name), "ilp scheduling IRG %s", get_entity_ld_name(get_irg_entity(env->irg)));
@@ -1943,19 +1945,19 @@ static void create_ilp(ir_node *block, void *walk_env) {
 
 		/* check for valid solution */
 		if (! lpp_is_sol_valid(lpp)) {
-			char buf[1024];
-			FILE *f;
-
 			DEBUG_ONLY({
-				if (firm_dbg_get_mask(env->dbg) >= 2) {
-					snprintf(buf, sizeof(buf), "lpp_block_%lu.infeasible.txt", get_irn_node_nr(block));
-					f = fopen(buf, "w");
-					lpp_dump_plain(lpp, f);
-					fclose(f);
-					snprintf(buf, sizeof(buf), "lpp_block_%lu.infeasible.mps", get_irn_node_nr(block));
-					lpp_dump(lpp, buf);
-					dump_ir_block_graph(env->irg, "-infeasible");
-				}
+                            char buf[1024];
+                            FILE *f;
+
+                            if (firm_dbg_get_mask(env->dbg) >= 2) {
+                              snprintf(buf, sizeof(buf), "lpp_block_%lu.infeasible.txt", get_irn_node_nr(block));
+                              f = fopen(buf, "w");
+                              lpp_dump_plain(lpp, f);
+                              fclose(f);
+                              snprintf(buf, sizeof(buf), "lpp_block_%lu.infeasible.mps", get_irn_node_nr(block));
+                              lpp_dump(lpp, buf);
+                              dump_ir_block_graph(env->irg, "-infeasible");
+                           }
 			})
 
 			ir_fprintf(stderr, "ILP found no solution within time (%+F, %+F), falling back to heuristics.\n", block, env->irg);

ir/be/belower.c

@@ -895,7 +895,7 @@ static int push_through_perm(ir_node *perm, void *data)
 	int i, n;
 	const ir_edge_t *edge;
 	ir_node *last_proj, *irn;
-	const arch_register_class_t *cls;
+	const arch_register_class_t *cls = NULL;
 
 	DBG((mod, LEVEL_1, "perm move %+F irg %+F\n", perm, irg));
 

ir/be/beschedrss.c

@@ -1729,8 +1729,8 @@ static serialization_t *compute_best_admissible_serialization(rss_t *rss, ir_nod
 	int        j, k;
 	ir_node    *irn;
 	ir_nodeset_iterator_t iter;
-	rss_edge_t min_benefit_edge;
-	rss_edge_t min_omega20_edge;
+	rss_edge_t min_benefit_edge = {NULL, NULL, NULL};
+	rss_edge_t min_omega20_edge = {NULL, NULL, NULL};
 	rss_irn_t  *ser_u_omega1 = NULL, *ser_v_omega1 = NULL;
 	rss_irn_t  *ser_u_omega20 = NULL, *ser_v_omega20 = NULL;
 
@@ -1811,8 +1811,10 @@ static serialization_t *compute_best_admissible_serialization(rss_t *rss, ir_nod
 			/* v cannot be serialized with itself
 			 * ignore nodes where serialization does not help */
 			if (i == j || IS_UNSERIALIZABLE_NODE(v)) {
+#ifdef DEBUG_libfirm
 				if (i != j)
 					DBG((rss->dbg, LEVEL_3, "\t\t\t%+F considered unserializable\n", v->irn));
+#endif
 				continue;
 			}
 

ir/be/ia32/ia32_intrinsics.c

@@ -729,11 +729,10 @@ static int map_Conv(ir_node *call, void *ctx) {
 		/* We have a Conv long long -> float here */
 		ir_node *a_l       = params[BINOP_Left_Low];
 		ir_node *a_h       = params[BINOP_Left_High];
-		ir_mode *mode_a_l  = get_irn_mode(a_l);
-		ir_mode *mode_a_h  = get_irn_mode(a_h);
 		ir_mode *fres_mode = get_type_mode(get_method_res_type(method, 0));
 
-		assert(! mode_is_float(mode_a_l) && ! mode_is_float(mode_a_h) && "unexpected Conv call");
+		assert(! mode_is_float(get_irn_mode(a_l))
+				&& ! mode_is_float(get_irn_mode(a_h)));
 
 		/* allocate memory on frame to store args */
 		ent = env->irg == irg ? env->ll_d_conv : NULL;

ir/be/ia32/ia32_new_nodes.c

@@ -1025,6 +1025,8 @@ init_ia32_x87_attributes(ir_node *res)
 #ifndef NDEBUG
 	ia32_attr_t *attr  = get_ia32_attr(res);
 	attr->attr_type   |= IA32_ATTR_ia32_x87_attr_t;
+#else
+	(void) res;
 #endif
 	ia32_current_cg->do_x87_sim = 1;
 }
@@ -1035,6 +1037,8 @@ init_ia32_asm_attributes(ir_node *res)
 #ifndef NDEBUG
 	ia32_attr_t *attr  = get_ia32_attr(res);
 	attr->attr_type   |= IA32_ATTR_ia32_asm_attr_t;
+#else
+	(void) res;
 #endif
 }
 

ir/be/ia32/ia32_transform.c

@@ -1623,10 +1623,9 @@ static ir_node *gen_Minus(ir_node *node)
  */
 static ir_node *gen_Not(ir_node *node) {
 	ir_node *op   = get_Not_op(node);
-	ir_mode *mode = get_irn_mode(node);
 
-	assert(mode != mode_b); /* should be lowered already */
-	assert (! mode_is_float(mode));
+	assert(get_irn_mode(node) != mode_b); /* should be lowered already */
+	assert (! mode_is_float(get_irn_mode(node)));
 
 	while(is_downconv(node)) {
 		node = get_Conv_op(node);
@@ -1778,7 +1777,7 @@ static ir_node *gen_Load(ir_node *node) {
 }
 
 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
-                       ir_node *ptr, ir_mode *mode, ir_node *other)
+                       ir_node *ptr, ir_node *other)
 {
 	ir_node *load;
 
@@ -1807,8 +1806,6 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
 			&& heights_reachable_in_block(heights, other, load))
 		return 0;
 
-	assert(get_Load_mode(load) == mode);
-
 	return 1;
 }
 
@@ -1829,10 +1826,10 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
 	ia32_address_t *addr = &am.addr;
 	memset(&am, 0, sizeof(am));
 
-	if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
+	if(use_dest_am(src_block, op1, mem, ptr, op2)) {
 		build_address(&am, op1);
 		new_op = create_immediate_or_transform(op2, 0);
-	} else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
+	} else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
 		build_address(&am, op2);
 		new_op = create_immediate_or_transform(op1, 0);
 	} else {
@@ -1877,7 +1874,7 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
 	ia32_address_t *addr = &am.addr;
 	memset(&am, 0, sizeof(am));
 
-	if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
+	if(!use_dest_am(src_block, op, mem, ptr, NULL))
 		return NULL;
 
 	build_address(&am, op);
@@ -2492,6 +2489,7 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
 	res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
 	                               nomem, res, mode_Bu);
 	SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
+	(void) orig_node;
 
 	return res;
 }
@@ -2786,6 +2784,7 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
 	set_am_attributes(res, &am);
 	set_ia32_ls_mode(res, smaller_mode);
 	SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+	(void) node;
 	res = fix_mem_proj(res, &am);
 
 	return res;

ir/be/ia32/ia32_x87.c

@@ -169,6 +169,7 @@ static int x87_get_st_reg(const x87_state *state, int pos) {
 	return state->st[MASK_TOS(state->tos + pos)].reg_idx;
 }  /* x87_get_st_reg */
 
+#ifdef DEBUG_libfirm
 /**
  * Return the node at st(pos).
  *
@@ -182,7 +183,6 @@ static ir_node *x87_get_st_node(const x87_state *state, int pos) {
 	return state->st[MASK_TOS(state->tos + pos)].node;
 }  /* x87_get_st_node */
 
-#ifdef DEBUG_libfirm
 /**
  * Dump the stack for debugging.
  *
@@ -671,10 +671,11 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
  */
 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
 {
-	ir_node *fpop;
+	ir_node *fpop = NULL;
 	ia32_x87_attr_t *attr;
 	int cpu = state->sim->isa->opt_arch;
 
+	assert(num > 0);
 	while (num > 0) {
 		x87_pop(state);
 		if (ARCH_ATHLON(cpu))
@@ -1587,12 +1588,13 @@ static int sim_Fucom(x87_state *state, ir_node *n) {
 	attr->x87[2] = NULL;
 	attr->attr.data.ins_permuted = permuted;
 
-	if (op2_idx >= 0)
+	if (op2_idx >= 0) {
 		DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
 			arch_register_get_name(op1), arch_register_get_name(op2)));
-	else
+	} else {
 		DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
 			arch_register_get_name(op1)));
+	}
 
 	return node_added;
 }

ir/be/ppc32/bearch_ppc32.c

@@ -37,6 +37,7 @@
 
 #include "bitset.h"
 #include "debug.h"
+#include "error.h"
 
 #include "../bearch_t.h"                /* the general register allocator interface */
 #include "../benode_t.h"
@@ -506,7 +507,7 @@ static void ppc32_transform_spill(ir_node *node, void *env)
 			store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
 				get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
 		}
-		else assert(0 && "Spill for register class not supported yet!");
+		else panic("Spill for register class not supported yet!");
 
 		set_ppc32_frame_entity(store, be_get_frame_entity(node));
 
@@ -540,7 +541,7 @@ static void ppc32_transform_spill(ir_node *node, void *env)
 		{
 			load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block,	get_irn_n(node, 0), get_irn_n(node, 1));
 		}
-		else assert(0 && "Reload for register class not supported yet!");
+		else panic("Reload for register class not supported yet!");
 
 		set_ppc32_frame_entity(load, be_get_frame_entity(node));