amd64: Add peephole optimization 'mov $0, %reg' -> 'xorl %reg, %reg'.

NEWS.md

@@ -13,6 +13,7 @@ libFirm 1.22.1 (2016-01-07)
 * Improve permutation moving for copy coalescing
 * Improve handling of negative overflow in float to int tarval conversion
 * Improve matching of immediates during instruction selection (amd64)
+* Add peephole optimization 'mov $0, %r' -> 'xorl %r, %r' (amd64)
 * Bugfixes
 
 libFirm 1.22.0 (2015-12-31)

ir/be/amd64/amd64_optimize.c

@@ -9,10 +9,35 @@
  */
 #include "amd64_optimize.h"
 
+#include "amd64_new_nodes.h"
+#include "benode.h"
 #include "bepeephole.h"
+#include "besched.h"
+#include "gen_amd64_regalloc_if.h"
+
+static void peephole_amd64_mov_imm(ir_node *const node)
+{
+	if (be_peephole_get_value(REG_EFLAGS))
+		return;
+
+	amd64_movimm_attr_t const *const attr = get_amd64_movimm_attr_const(node);
+	amd64_imm64_t       const *const imm  = &attr->immediate;
+	if (imm->kind == X86_IMM_VALUE && imm->offset == 0) {
+		/* mov $0, %reg -> xorl %reg, %reg */
+		dbg_info              *const dbgi  = get_irn_dbg_info(node);
+		ir_node               *const block = get_nodes_block(node);
+		ir_node               *const xor   = new_bd_amd64_xor_0(dbgi, block);
+		arch_register_t const *const reg   = arch_get_irn_register_out(node, pn_amd64_mov_imm_res);
+		arch_set_irn_register_out(xor, pn_amd64_xor_0_res, reg);
+		sched_add_before(node, xor);
+		ir_node *const res = be_new_Proj(xor, pn_amd64_xor_0_res);
+		be_peephole_exchange(node, res);
+	}
+}
 
 void amd64_peephole_optimization(ir_graph *const irg)
 {
 	ir_clear_opcodes_generic_func();
+	register_peephole_optimization(op_amd64_mov_imm, peephole_amd64_mov_imm);
 	be_peephole_opt(irg);
 }

ir/be/amd64/amd64_spec.pl

@@ -420,6 +420,7 @@ mov_imm => {
 	op_flags  => [ "constlike" ],
 	irn_flags => [ "rematerializable" ],
 	out_reqs  => [ "gp" ],
+	outs      => [ "res" ],
 	attr_type => "amd64_movimm_attr_t",
 	attr      => "amd64_insn_size_t size, const amd64_imm64_t *imm",
 	emit      => 'mov%MM $%C, %D0',