Commit 88760903 authored by Michael Beck's avatar Michael Beck
Browse files

fixed 64bit instrinsics for Div/Mod/Shr/Shl/Shrs

[r15505]
parent df144e68
......@@ -168,18 +168,25 @@ struct ia32_irn_ops_t {
ia32_code_gen_t *cg;
};
/**
* A helper type collecting needed info for IA32 intrinsic lowering.
*/
struct ia32_intrinsic_env_t {
ir_graph *irg; /**< the irg, these entities belong to */
ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
ir_entity *ll_d_conv; /**< entity for converts ll -> d */
ir_entity *d_ll_conv; /**< entity for converts d -> ll */
ir_entity *divdi3; /**< entity for __divdi3 library call */
ir_entity *moddi3; /**< entity for __moddi3 library call */
ir_entity *udivdi3; /**< entity for __udivdi3 library call */
ir_entity *umoddi3; /**< entity for __umoddi3 library call */
};
/** mode for the floating point control word */
/** The mode for the floating point control word. */
extern ir_mode *mode_fpcw;
/** current code generator */
/** The current code generator. */
extern ia32_code_gen_t *ia32_current_cg;
/**
......
......@@ -84,26 +84,27 @@ static void resolve_call(ir_node *call, ir_node *l_res, ir_node *h_res, ir_graph
* Map an Add (a_l, a_h, b_l, b_h)
*/
static int map_Add(ir_node *call, void *ctx) {
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *b_l = params[BINOP_Right_Low];
ir_node *b_h = params[BINOP_Right_High];
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *b_l = params[BINOP_Right_Low];
ir_node *b_h = params[BINOP_Right_High];
ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0));
ir_node *l_res, *h_res, *add;
(void) ctx;
assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes");
/* l_res = a_l + b_l */
/* h_res = a_h + b_h + carry */
add = new_rd_ia32_Add64Bit(dbg, irg, block, a_l, a_h, b_l, b_h);
l_res = new_r_Proj(irg, block, add, l_res_mode, pn_ia32_Add64Bit_low_res);
h_res = new_r_Proj(irg, block, add, h_res_mode, pn_ia32_Add64Bit_high_res);
l_res = new_r_Proj(irg, block, add, l_mode, pn_ia32_Add64Bit_low_res);
h_res = new_r_Proj(irg, block, add, l_mode, pn_ia32_Add64Bit_high_res);
resolve_call(call, l_res, h_res, irg, block);
return 1;
......@@ -113,26 +114,27 @@ static int map_Add(ir_node *call, void *ctx) {
* Map a Sub (a_l, a_h, b_l, b_h)
*/
static int map_Sub(ir_node *call, void *ctx) {
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *b_l = params[BINOP_Right_Low];
ir_node *b_h = params[BINOP_Right_High];
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *b_l = params[BINOP_Right_Low];
ir_node *b_h = params[BINOP_Right_High];
ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0));
ir_node *l_res, *h_res, *res;
(void) ctx;
assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes");
/* l_res = a_l - b_l */
/* h_res = a_h - b_h - carry */
res = new_rd_ia32_Sub64Bit(dbg, irg, block, a_l, a_h, b_l, b_h);
l_res = new_r_Proj(irg, block, res, l_res_mode, pn_ia32_Sub64Bit_low_res);
h_res = new_r_Proj(irg, block, res, h_res_mode, pn_ia32_Sub64Bit_high_res);
l_res = new_r_Proj(irg, block, res, l_mode, pn_ia32_Sub64Bit_low_res);
h_res = new_r_Proj(irg, block, res, l_mode, pn_ia32_Sub64Bit_high_res);
resolve_call(call, l_res, h_res, irg, block);
return 1;
......@@ -142,26 +144,25 @@ static int map_Sub(ir_node *call, void *ctx) {
* Map a Shl (a_l, a_h, count)
*/
static int map_Shl(ir_node *call, void *ctx) {
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *cnt = params[BINOP_Right_Low];
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *cnt = params[BINOP_Right_Low];
ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0));
ir_node *l_res, *h_res;
(void) ctx;
assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes");
/* h_res = SHLD a_h, a_l, cnt */
h_res = new_rd_ia32_l_ShlD(dbg, irg, block, a_h, a_l, cnt, l_res_mode);
h_res = new_rd_ia32_l_ShlD(dbg, irg, block, a_h, a_l, cnt, l_mode);
/* l_res = SHL a_l, cnt */
l_res = new_rd_ia32_l_Shl(dbg, irg, block, a_l, cnt, h_res_mode);
//add_irn_dep(l_res, h_res);
l_res = new_rd_ia32_l_ShlDep(dbg, irg, block, a_l, cnt, h_res, l_mode);
resolve_call(call, l_res, h_res, irg, block);
return 1;
......@@ -171,26 +172,25 @@ static int map_Shl(ir_node *call, void *ctx) {
* Map a Shr (a_l, a_h, count)
*/
static int map_Shr(ir_node *call, void *ctx) {
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *cnt = params[BINOP_Right_Low];
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *cnt = params[BINOP_Right_Low];
ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0));
ir_node *l_res, *h_res;
(void) ctx;
/* l_res = SHRD a_l, a_h, cnt */
l_res = new_rd_ia32_l_ShrD(dbg, irg, block, a_l, a_h, cnt, l_res_mode);
assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes");
/* h_res = SHR a_h, cnt */
h_res = new_rd_ia32_l_Shr(dbg, irg, block, a_h, cnt, h_res_mode);
/* l_res = SHRD a_h:a_l, cnt */
l_res = new_rd_ia32_l_ShrD(dbg, irg, block, a_l, a_h, cnt, l_mode);
//add_irn_dep(h_res, l_res);
/* h_res = SHR a_h, cnt */
h_res = new_rd_ia32_l_ShrDep(dbg, irg, block, a_h, cnt, l_res, l_mode);
resolve_call(call, l_res, h_res, irg, block);
return 1;
......@@ -214,13 +214,11 @@ static int map_Shrs(ir_node *call, void *ctx) {
assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes");
/* l_res = SHRD a_l, a_h, cnt */
/* l_res = SHRD a_h:a_l, cnt */
l_res = new_rd_ia32_l_ShrD(dbg, irg, block, a_l, a_h, cnt, l_mode);
/* h_res = SAR a_h, cnt */
h_res = new_rd_ia32_l_Sar(dbg, irg, block, a_h, cnt, l_mode);
//add_irn_dep(h_res, l_res);
h_res = new_rd_ia32_l_SarDep(dbg, irg, block, a_h, cnt, l_res, l_mode);
resolve_call(call, l_res, h_res, irg, block);
return 1;
......@@ -343,155 +341,86 @@ static int map_Abs(ir_node *call, void *ctx) {
return 1;
}
typedef enum {
IA32_INTRINSIC_DIV,
IA32_INTRINSIC_MOD,
} ia32_intrinsic_divmod_t;
#define ID(x) new_id_from_chars(x, sizeof(x)-1)
/**
* Maps a Div/Mod (a_l, a_h, b_l, b_h)
* Maps a Div. Change into a library call
*/
static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp) {
static int map_Div(ir_node *call, void *ctx) {
ia32_intrinsic_env_t *env = ctx;
ir_graph *irg = current_ir_graph;
dbg_info *dbg = get_irn_dbg_info(call);
ir_node *block = get_nodes_block(call);
ir_node **params = get_Call_param_arr(call);
ir_type *method = get_Call_type(call);
ir_node *a_l = params[BINOP_Left_Low];
ir_node *a_h = params[BINOP_Left_High];
ir_node *b_l = params[BINOP_Right_Low];
ir_node *b_h = params[BINOP_Right_High];
ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0));
int mode_bytes = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
ir_entity *ent_a = env->irg == irg ? env->ll_div_op1 : NULL;
ir_entity *ent_b = env->irg == irg ? env->ll_div_op2 : NULL;
ir_node *l_res, *h_res, *frame;
ir_node *store_l, *store_h;
ir_node *op_mem[2], *mem, *fa_mem, *fb_mem;
ir_node *fa, *fb, *fres;
ir_node *ptr;
ir_entity *ent;
symconst_symbol sym;
assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes");
/* allocate memory on frame to store args */
if (! ent_a) {
ent_a = env->ll_div_op1 =
frame_alloc_area(get_irg_frame_type(irg), 2 * mode_bytes, 16, 0);
env->irg = irg;
}
if (! ent_b) {
ent_b = env->ll_div_op2 =
frame_alloc_area(get_irg_frame_type(irg), 2 * mode_bytes, 16, 0);
env->irg = irg;
}
frame = get_irg_frame(irg);
/* store first arg */
store_l = new_rd_ia32_l_Store(dbg, irg, block, frame, a_l, get_irg_no_mem(irg));
set_ia32_frame_ent(store_l, ent_a);
set_ia32_use_frame(store_l);
set_ia32_ls_mode(store_l, get_irn_mode(a_l));
op_mem[0] = store_l;
store_h = new_rd_ia32_l_Store(dbg, irg, block, frame, a_h, get_irg_no_mem(irg));
set_ia32_frame_ent(store_h, ent_a);
add_ia32_am_offs_int(store_h, mode_bytes);
set_ia32_use_frame(store_h);
set_ia32_ls_mode(store_h, get_irn_mode(a_h));
op_mem[1] = store_h;
mem = new_r_Sync(irg, block, 2, op_mem);
/* load first arg into FPU */
fa = new_rd_ia32_l_vfild(dbg, irg, block, frame, mem);
set_ia32_frame_ent(fa, ent_a);
set_ia32_use_frame(fa);
set_ia32_ls_mode(fa, mode_D);
fa_mem = new_r_Proj(irg, block, fa, mode_M, pn_ia32_l_vfild_M);
fa = new_r_Proj(irg, block, fa, mode_E, pn_ia32_l_vfild_res);
/* store second arg */
store_l = new_rd_ia32_l_Store(dbg, irg, block, frame, b_l, get_irg_no_mem(irg));
set_ia32_frame_ent(store_l, ent_b);
set_ia32_use_frame(store_l);
set_ia32_ls_mode(store_l, get_irn_mode(b_l));
op_mem[0] = store_l;
store_h = new_rd_ia32_l_Store(dbg, irg, block, frame, b_h, get_irg_no_mem(irg));
set_ia32_frame_ent(store_h, ent_b);
add_ia32_am_offs_int(store_h, mode_bytes);
set_ia32_use_frame(store_h);
set_ia32_ls_mode(store_h, get_irn_mode(b_h));
op_mem[1] = store_h;
mem = new_r_Sync(irg, block, 2, op_mem);
/* load second arg into FPU */
fb = new_rd_ia32_l_vfild(dbg, irg, block, frame, mem);
set_ia32_frame_ent(fb, ent_b);
set_ia32_use_frame(fb);
set_ia32_ls_mode(fb, mode_D);
fb_mem = new_r_Proj(irg, block, fb, mode_M, pn_ia32_l_vfild_M);
fb = new_r_Proj(irg, block, fb, mode_E, pn_ia32_l_vfild_res);
op_mem[0] = fa_mem;
op_mem[1] = fb_mem;
mem = new_r_Sync(irg, block, 2, op_mem);
/* perform division */
switch (dmtp) {
case IA32_INTRINSIC_DIV:
fres = new_rd_ia32_l_vfdiv(dbg, irg, block, fa, fb);
fres = new_rd_Proj(dbg, irg, block, fres, mode_E, pn_ia32_l_vfdiv_res);
break;
case IA32_INTRINSIC_MOD:
fres = new_rd_ia32_l_vfprem(dbg, irg, block, fa, fb, mode_E);
break;
default:
assert(0);
if (mode_is_signed(l_mode)) {
/* 64bit signed Division */
ent = env->divdi3;
if (ent == NULL) {
/* create library entity */
ent = env->divdi3 = new_entity(get_glob_type(), ID("__divdi3"), method);
set_entity_visibility(ent, visibility_external_allocated);
set_entity_ld_ident(ent, ID("__divdi3"));
}
} else {
/* 64bit signed Division */
ent = env->udivdi3;
if (ent == NULL) {
/* create library entity */
ent = env->udivdi3 = new_entity(get_glob_type(), ID("__udivdi3"), method);
set_entity_visibility(ent, visibility_external_allocated);
set_entity_ld_ident(ent, ID("__udivdi3"));
}
}
/* store back result, we use ent_a here */
fres = new_rd_ia32_l_vfist(dbg, irg, block, frame, fres, mem);
set_ia32_frame_ent(fres, ent_a);
set_ia32_use_frame(fres);
set_ia32_ls_mode(fres, mode_D);
mem = fres;
/* load low part of the result */
l_res = new_rd_ia32_l_Load(dbg, irg, block, frame, mem);
set_ia32_frame_ent(l_res, ent_a);
set_ia32_use_frame(l_res);
set_ia32_ls_mode(l_res, l_mode);
l_res = new_r_Proj(irg, block, l_res, l_mode, pn_ia32_l_Load_res);
/* load hight part of the result */
h_res = new_rd_ia32_l_Load(dbg, irg, block, frame, mem);
set_ia32_frame_ent(h_res, ent_a);
add_ia32_am_offs_int(h_res, mode_bytes);
set_ia32_use_frame(h_res);
set_ia32_ls_mode(h_res, l_mode);
h_res = new_r_Proj(irg, block, h_res, l_mode, pn_ia32_l_Load_res);
/* lower the call */
resolve_call(call, l_res, h_res, irg, block);
sym.entity_p = ent;
ptr = get_Call_ptr(call);
set_SymConst_symbol(ptr, sym);
return 1;
}
static int map_Div(ir_node *call, void *ctx) {
return DivMod_mapper(call, ctx, IA32_INTRINSIC_DIV);
}
/**
* Maps a Mod. Change into a library call
*/
static int map_Mod(ir_node *call, void *ctx) {
return DivMod_mapper(call, ctx, IA32_INTRINSIC_MOD);
ia32_intrinsic_env_t *env = ctx;
ir_type *method = get_Call_type(call);
ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0));
ir_node *ptr;
ir_entity *ent;
symconst_symbol sym;
assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes");
if (mode_is_signed(l_mode)) {
/* 64bit signed Modulo */
ent = env->moddi3;
if (ent == NULL) {
/* create library entity */
ent = env->moddi3 = new_entity(get_glob_type(), ID("__moddi3"), method);
set_entity_visibility(ent, visibility_external_allocated);
set_entity_ld_ident(ent, ID("__moddi3"));
}
} else {
/* 64bit signed Modulo */
ent = env->umoddi3;
if (ent == NULL) {
/* create library entity */
ent = env->umoddi3 = new_entity(get_glob_type(), ID("__umoddi3"), method);
set_entity_visibility(ent, visibility_external_allocated);
set_entity_ld_ident(ent, ID("__umoddi3"));
}
}
sym.entity_p = ent;
ptr = get_Call_ptr(call);
set_SymConst_symbol(ptr, sym);
return 1;
}
/**
* Maps a Conv (a_l, a_h)
* Maps a Conv.
*/
static int map_Conv(ir_node *call, void *ctx) {
ia32_intrinsic_env_t *env = ctx;
......
......@@ -594,23 +594,27 @@ Shl => {
modified_flags => $status_flags
},
l_Shl => {
l_ShlDep => {
cmp_attr => "return 1;",
arity => 2
# value, cnt, dependency
arity => 3
},
ShlD => {
irn_flags => "R",
# FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shl
#
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
# this Shift and the only value dying is the ShiftCount. Then there would be
# a register missing, as result must not be ecx and all other registers are
# occupied. What we should write is "!in_r4 !in_r5", but this is not
# supported (and probably never will). So we create artificial interferences
# of the result with all inputs, so the spiller can always assure a free
# register.
reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
# this Shift and the only value dying is the ShiftCount. Then there would be a
# register missing, as result must not be ecx and all other registers are
# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
# (and probably never will). So we create artificial interferences of the result
# with all inputs, so the spiller can always assure a free register.
# reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
emit =>
'
if (get_ia32_immop_type(node) == ia32_ImmNone) {
......@@ -647,13 +651,15 @@ Shr => {
modified_flags => $status_flags
},
l_Shr => {
l_ShrDep => {
cmp_attr => "return 1;",
arity => 2
# value, cnt, dependency
arity => 3
},
ShrD => {
irn_flags => "R",
# FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shr
#
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
......@@ -662,7 +668,10 @@ ShrD => {
# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
# (and probably never will). So we create artificial interferences of the result
# with all inputs, so the spiller can always assure a free register.
reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
# reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
emit => '
if (get_ia32_immop_type(node) == ia32_ImmNone) {
if (get_ia32_op_type(node) == ia32_AddrModeD) {
......@@ -700,9 +709,16 @@ Sar => {
l_Sar => {
cmp_attr => "return 1;",
# value, cnt
arity => 2
},
l_SarDep => {
cmp_attr => "return 1;",
# value, cnt, dependency
arity => 3
},
Ror => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
......
......@@ -643,6 +643,13 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
set_ia32_emit_cl(new_op);
/* lowered shift instruction may have a dependency operand, handle it here */
if (get_irn_arity(node) == 3) {
/* we have a dependency */
ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
add_irn_dep(new_op, new_dep);
}
return new_op;
}
......@@ -3470,10 +3477,10 @@ static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
}
#define GEN_LOWERED_SHIFT_OP(op) \
static ir_node *gen_ia32_l_##op(ir_node *node) {\
return gen_shift_binop(node, get_binop_left(node), \
get_binop_right(node), new_rd_ia32_##op); \
#define GEN_LOWERED_SHIFT_OP(l_op, op) \
static ir_node *gen_ia32_##l_op(ir_node *node) { \
return gen_shift_binop(node, get_irn_n(node, 0), \
get_irn_n(node, 1), new_rd_ia32_##op); \
}
#define GEN_LOWERED_LOAD(op) \
......@@ -3599,9 +3606,10 @@ static ir_node *gen_ia32_l_Mul(ir_node *node) {
return muls;
}
GEN_LOWERED_SHIFT_OP(Shl)
GEN_LOWERED_SHIFT_OP(Shr)
GEN_LOWERED_SHIFT_OP(Sar)
GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
/**
* Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
......@@ -3616,8 +3624,8 @@ static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *new_op1 = be_transform_node(op1);
ir_node *new_op2 = be_transform_node(op2);
ir_node *new_count = be_transform_node(count);
ir_node *new_op = NULL;
ir_node *new_count = be_transform_node(count);
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
......@@ -4308,9 +4316,10 @@ static void register_transformers(void)
GEN(ia32_l_Mul);
GEN(ia32_l_Xor);
GEN(ia32_l_IMul);
GEN(ia32_l_Shl);
GEN(ia32_l_Shr);
GEN(ia32_l_ShlDep);
GEN(ia32_l_ShrDep);
GEN(ia32_l_Sar);
GEN(ia32_l_SarDep);
GEN(ia32_l_ShlD);
GEN(ia32_l_ShrD);
GEN(ia32_l_vfdiv);
......
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