amd64: Fixed incorrect code

ir/be/amd64/TODO

@@ -10,7 +10,6 @@ Correctness:
 - (Support 80bit long double with x87 instructions)
 
 Improve Quality:
-- Build leas instead of Adds
 - Immediate32 matching could be better and match SymConst, Add(SymConst, Const)
   combinations where possible. Be careful with PIC code this may usually not
   be legal!

ir/be/amd64/amd64_transform.c

@@ -422,19 +422,21 @@ static bool needs_extension(ir_node *op)
 	return !be_upper_bits_clean(op, mode);
 }
 
-static ir_node *create_sext(ir_node *const node, ir_mode *mode)
+static ir_node *create_sext(ir_node *block, ir_node *const node, ir_mode *mode)
 {
 	amd64_insn_mode_t insn_mode = get_insn_mode_from_mode(mode);
 	dbg_info *const   dbgi      = get_irn_dbg_info(node);
-	ir_node  *const   block     = get_nodes_block(node);
+	ir_node  *const   new_node  = be_transform_node(node);
+	ir_node  *const   new_block = be_transform_node(block);
 
 	amd64_shift_attr_t attr;
 	memset(&attr, 0, sizeof(attr));
 	attr.base.op_mode = AMD64_OP_SHIFT_IMM;
 	attr.insn_mode    = insn_mode;
 	attr.immediate    = get_mode_size_bits(mode) - 1;
-	ir_node *in[1]    = { node };
-	ir_node *sext     = new_bd_amd64_Sar(dbgi, block, ARRAY_SIZE(in), in, &attr);
+	ir_node *in[1]    = { new_node };
+	ir_node *sext     = new_bd_amd64_Sar(dbgi, new_block, ARRAY_SIZE(in),
+	                                     in, &attr);
 
 	arch_set_irn_register_reqs_in(sext, reg_reqs);
 	arch_set_irn_register_req_out(sext, 0, &amd64_requirement_gp_same_0);
@@ -442,11 +444,11 @@ static ir_node *create_sext(ir_node *const node, ir_mode *mode)
 	return sext;
 }
 
-static ir_node *create_zext(ir_node *const node)
+static ir_node *create_zext(ir_node *block, ir_node *const node)
 {
-	dbg_info *const dbgi  = get_irn_dbg_info(node);
-	ir_node  *const block = get_nodes_block(node);
-	ir_node  *const zero  = new_bd_amd64_Xor0(dbgi, block);
+	dbg_info *const dbgi      = get_irn_dbg_info(node);
+	ir_node  *const new_block = be_transform_node(block);
+	ir_node  *const zero      = new_bd_amd64_Xor0(dbgi, new_block);
 
 	arch_set_irn_register_reqs_in(zero, reg_reqs);
 	return zero;
@@ -916,8 +918,9 @@ static ir_node *gen_Shrs(ir_node *const node)
 static ir_node *create_div(ir_node *const node, ir_mode *const mode,
                            ir_node *const op1, ir_node *const op2)
 {
-	dbg_info *const dbgi    = get_irn_dbg_info(node);
-	ir_node  *const block   = be_transform_node(get_nodes_block(node));
+	dbg_info *const dbgi      = get_irn_dbg_info(node);
+	ir_node  *const block     = get_nodes_block(node);
+	ir_node  *const new_block = be_transform_node(block);
 	amd64_insn_mode_t insn_mode
 		= get_mode_size_bits(mode) > 32 ? INSN_MODE_64 : INSN_MODE_32;
 
@@ -935,15 +938,15 @@ static ir_node *create_div(ir_node *const node, ir_mode *const mode,
 
 	if (mode_is_signed(mode)) {
 		/* Sign extend RAX to RDX */
-		in[arity++] = create_sext(be_transform_node(op1), mode);
+		in[arity++] = create_sext(block, op1, mode);
 
-		res = new_bd_amd64_IDiv(dbgi, block, arity, in, insn_mode,
+		res = new_bd_amd64_IDiv(dbgi, new_block, arity, in, insn_mode,
                                 op_mode, addr);
 	} else {
 		/* Zero extend to register RDX */
-		in[arity++] = create_zext(node);
+		in[arity++] = create_zext(block, node);
 
-		res = new_bd_amd64_Div(dbgi, block, arity, in, insn_mode,
+		res = new_bd_amd64_Div(dbgi, new_block, arity, in, insn_mode,
                                op_mode, addr);
 	}