Commit 96cdb5f8 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Remove the very thin wrapper function arch_register_get_name().

parent 95a0ba04
......@@ -54,7 +54,7 @@ static void TEMPLATE_emit_immediate(const ir_node *node)
static void emit_register(const arch_register_t *reg)
{
be_emit_string(arch_register_get_name(reg));
be_emit_string(reg->name);
}
static void TEMPLATE_emit_source_register(const ir_node *node, int pos)
......
......@@ -136,7 +136,7 @@ void amd64_emitf(ir_node const *const node, char const *fmt, ...)
reg = va_arg(ap, arch_register_t const*);
emit_R:
be_emit_char('%');
be_emit_string(arch_register_get_name(reg));
be_emit_string(reg->name);
break;
case 'S': {
......
......@@ -64,7 +64,7 @@ static arm_isa_t *isa;
static void arm_emit_register(const arch_register_t *reg)
{
be_emit_string(arch_register_get_name(reg));
be_emit_string(reg->name);
}
static void arm_emit_source_register(const ir_node *node, int pos)
......
......@@ -250,11 +250,6 @@ static inline unsigned arch_register_get_index(const arch_register_t *reg)
return reg->index;
}
static inline const char *arch_register_get_name(const arch_register_t *reg)
{
return reg->name;
}
/**
* A class of registers.
* Like general purpose or floating point.
......
......@@ -470,7 +470,7 @@ static void assign(ir_node *block, void *env_ptr)
bitset_set(colors, col);
arch_set_irn_register(irn, reg);
DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n", arch_register_get_name(reg), col, irn));
DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n", reg->name, col, irn));
assert(!bitset_is_set(live, nr) && "Value's definition must not have been encountered");
bitset_set(live, nr);
......
......@@ -153,12 +153,11 @@ static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
*/
static void emit_8bit_register(const arch_register_t *reg)
{
const char *reg_name = arch_register_get_name(reg);
assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
|| reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
be_emit_char(reg_name[1]); /* get the basic name of the register */
be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('l');
}
......@@ -167,21 +166,18 @@ static void emit_8bit_register(const arch_register_t *reg)
*/
static void emit_8bit_register_high(const arch_register_t *reg)
{
const char *reg_name = arch_register_get_name(reg);
assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
|| reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
be_emit_char(reg_name[1]); /* get the basic name of the register */
be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('h');
}
static void emit_16bit_register(const arch_register_t *reg)
{
const char *reg_name = arch_register_get_name(reg);
be_emit_char('%');
be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
}
/**
......@@ -192,8 +188,6 @@ static void emit_16bit_register(const arch_register_t *reg)
*/
static void emit_register(const arch_register_t *reg, const ir_mode *mode)
{
const char *reg_name;
if (mode != NULL) {
int size = get_mode_size_bits(mode);
switch (size) {
......@@ -203,10 +197,8 @@ static void emit_register(const arch_register_t *reg, const ir_mode *mode)
assert(mode_is_float(mode) || size == 32);
}
reg_name = arch_register_get_name(reg);
be_emit_char('%');
be_emit_string(reg_name);
be_emit_string(reg->name);
}
static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
......@@ -511,7 +503,7 @@ end_of_mods:
arch_register_t const * in = x87_attr->x87[1];
if (out == in)
in = x87_attr->x87[0];
be_emit_irprintf("%%%s, %%%s", arch_register_get_name(in), arch_register_get_name(out));
be_emit_irprintf("%%%s, %%%s", in->name, out->name);
break;
}
......
......@@ -755,9 +755,7 @@ static int sim_binop(x87_state *const state, ir_node *const n, ir_op *const op)
int op1_live_after;
int op2_live_after;
DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
arch_register_get_name(out)));
DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, op1_reg->name, op2_reg->name, out->name));
DEBUG_ONLY(vfp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state);)
......@@ -881,13 +879,9 @@ static int sim_binop(x87_state *const state, ir_node *const n, ir_op *const op)
attr->x87[2] = out = get_st_reg(out_idx);
if (reg_index_2 != REG_VFP_VFP_NOREG) {
DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
arch_register_get_name(out)));
DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), op1_reg->name, op2_reg->name, out->name));
} else {
DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
arch_register_get_name(op1_reg),
arch_register_get_name(out)));
DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n), op1_reg->name, out->name));
}
return NO_NODE_ADDED;
......@@ -946,12 +940,12 @@ static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
const arch_register_t *out = x87_irn_get_register(n, res_pos);
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
assert(out == x87_irn_get_register(n, res_pos));
attr = get_ia32_x87_attr(n);
attr->x87[2] = out = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
return NO_NODE_ADDED;
}
......@@ -985,7 +979,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op)
{
ir_node *const val = get_irn_n(n, n_ia32_vfst_val);
arch_register_t const *const op2 = x87_get_irn_register(val);
DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
bool do_pop = false;
int insn = NO_NODE_ADDED;
......@@ -1064,7 +1058,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op)
ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
attr->pop = do_pop;
attr->x87[1] = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(attr->x87[1])));
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), attr->x87[1]->name));
return insn;
}
......@@ -1131,7 +1125,7 @@ static int sim_fisttp(x87_state *state, ir_node *n)
op2_reg_idx = arch_register_get_index(op2);
op2_idx = x87_on_stack(state, op2_reg_idx);
DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
assert(op2_idx >= 0);
/* Note: although the value is still live here, it is destroyed because
......@@ -1147,7 +1141,7 @@ static int sim_fisttp(x87_state *state, ir_node *n)
attr = get_ia32_x87_attr(n);
attr->x87[1] = op2 = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), op2->name));
return NO_NODE_ADDED;
}
......@@ -1170,7 +1164,7 @@ static int sim_FtstFnstsw(x87_state *state, ir_node *n)
int op1_idx = x87_on_stack(state, reg_index_1);
unsigned live = vfp_live_args_after(sim, n, 0);
DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
DB((dbg, LEVEL_1, ">>> %+F %s\n", n, reg1->name));
DEBUG_ONLY(vfp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state);)
......@@ -1221,8 +1215,7 @@ static int sim_Fucom(x87_state *state, ir_node *n)
bool xchg = false;
int pops = 0;
DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
arch_register_get_name(op1), arch_register_get_name(op2)));
DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, op1->name, op2->name));
DEBUG_ONLY(vfp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state);)
......@@ -1425,11 +1418,9 @@ static int sim_Fucom(x87_state *state, ir_node *n)
attr->attr.data.ins_permuted = permuted;
if (op2_idx >= 0) {
DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
arch_register_get_name(op1), arch_register_get_name(op2)));
DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n), op1->name, op2->name));
} else {
DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
arch_register_get_name(op1)));
DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n), op1->name));
}
return NO_NODE_ADDED;
......@@ -1580,8 +1571,7 @@ static int sim_Copy(x87_state *state, ir_node *n)
arch_register_t const *const out = x87_get_irn_register(n);
unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
arch_register_get_name(op1), arch_register_get_name(out)));
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, op1->name, out->name));
DEBUG_ONLY(vfp_dump_live(live);)
if (is_vfp_live(arch_register_get_index(op1), live)) {
......
......@@ -128,14 +128,14 @@ static void sparc_emit_source_register(ir_node const *node, int const pos)
{
const arch_register_t *reg = arch_get_irn_register_in(node, pos);
be_emit_char('%');
be_emit_string(arch_register_get_name(reg));
be_emit_string(reg->name);
}
static void sparc_emit_dest_register(ir_node const *const node, int const pos)
{
const arch_register_t *reg = arch_get_irn_register_out(node, pos);
be_emit_char('%');
be_emit_string(arch_register_get_name(reg));
be_emit_string(reg->name);
}
/**
......@@ -664,7 +664,7 @@ void sparc_emitf(ir_node const *const node, char const *fmt, ...)
case 'R': {
arch_register_t const *const reg = va_arg(ap, const arch_register_t*);
be_emit_char('%');
be_emit_string(arch_register_get_name(reg));
be_emit_string(reg->name);
break;
}
......
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