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Commit 97aa32b4 authored by Matthias Braun's avatar Matthias Braun
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be: merge init_graph() and prepare_graph() callbacks into one

parent 9b260f5d
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ir/be/TEMPLATE/bearch_TEMPLATE.c
View file @ 97aa32b4
......@@ -12,6 +12,7 @@
#include "irgwalk.h"
#include "irprog.h"
#include "ircons.h"
#include "irdump.h"
#include "irgmod.h"
#include "lower_calls.h"
#include "lower_builtins.h"
......@@ -79,7 +80,11 @@ static const arch_irn_ops_t TEMPLATE_irn_ops = {
static void TEMPLATE_prepare_graph(ir_graph *irg)
{
/* transform nodes into assembler instructions */
be_timer_push(T_CODEGEN);
TEMPLATE_transform_graph(irg);
be_timer_pop(T_CODEGEN);
if (be_options.dump_flags & DUMP_BE)
dump_ir_graph(irg, "code-selection");
}
......@@ -101,12 +106,6 @@ static void TEMPLATE_before_ra(ir_graph *irg)
/* Some stuff you need to do after scheduling but before register allocation */
}
static void TEMPLATE_init_graph(ir_graph *irg)
{
(void) irg;
}
extern const arch_isa_if_t TEMPLATE_isa_if;
static TEMPLATE_isa_t TEMPLATE_isa_template = {
......@@ -323,7 +322,6 @@ const arch_isa_if_t TEMPLATE_isa_if = {
TEMPLATE_begin_codegeneration,
TEMPLATE_end_codegeneration,
TEMPLATE_init_graph,
TEMPLATE_get_call_abi,
NULL, /* mark remat */
be_new_spill,
......
ir/be/amd64/bearch_amd64.c
View file @ 97aa32b4
......@@ -98,20 +98,6 @@ static const arch_irn_ops_t amd64_irn_ops = {
NULL, /* perform_memory_operand */
};
/**
* Transforms the standard firm graph into
* a amd64 firm graph
*/
static void amd64_prepare_graph(ir_graph *irg)
{
amd64_transform_graph(irg);
if (be_options.dump_flags & DUMP_BE)
dump_ir_graph(irg, "transformed");
}
static void amd64_before_ra(ir_graph *irg)
{
be_sched_fix_flags(irg, &amd64_reg_classes[CLASS_amd64_flags], NULL, NULL);
......@@ -253,12 +239,22 @@ static void amd64_end_codegeneration(void *self)
free(self);
}
static void amd64_init_graph(ir_graph *irg)
/**
* prepare graph and perform code selection.
*/
static void amd64_prepare_graph(ir_graph *irg)
{
be_abi_introduce(irg);
if (be_options.dump_flags & DUMP_BE) {
dump_ir_graph(irg, "abi");
}
be_timer_push(T_CODEGEN);
amd64_transform_graph(irg);
be_timer_pop(T_CODEGEN);
if (be_options.dump_flags & DUMP_BE)
dump_ir_graph(irg, "code-selection");
}
/**
......@@ -452,7 +448,6 @@ const arch_isa_if_t amd64_isa_if = {
amd64_begin_codegeneration,
amd64_end_codegeneration,
amd64_init_graph,
amd64_get_call_abi,
NULL, /* mark remat */
be_new_spill,
......
ir/be/arm/bearch_arm.c
View file @ 97aa32b4
......@@ -102,13 +102,16 @@ static const arch_irn_ops_t arm_irn_ops = {
};
/**
* Transforms the standard Firm graph into
* a ARM firm graph.
* Transforms the standard Firm graph into an ARM firm graph.
*/
static void arm_prepare_graph(ir_graph *irg)
{
/* transform nodes into assembler instructions */
be_timer_push(T_CODEGEN);
arm_transform_graph(irg);
be_timer_pop(T_CODEGEN);
if (be_options.dump_flags & DUMP_BE)
dump_ir_graph(irg, "code-selection");
/* do local optimizations (mainly CSE) */
local_optimize_graph(irg);
......@@ -462,7 +465,6 @@ const arch_isa_if_t arm_isa_if = {
arm_begin_codegeneration,
arm_end_codegeneration,
NULL,
NULL, /* get call abi */
NULL, /* mark remat */
be_new_spill,
......
ir/be/be_t.h
View file @ 97aa32b4
......@@ -22,7 +22,6 @@
enum {
DUMP_NONE = 0,
DUMP_INITIAL = 1 << 0,
DUMP_ABI = 1 << 1,
DUMP_SCHED = 1 << 2,
DUMP_PREPARED = 1 << 3,
DUMP_RA = 1 << 4,
......
ir/be/bearch.h
View file @ 97aa32b4
......@@ -413,12 +413,6 @@ struct arch_isa_if_t {
*/
void (*end_codegeneration)(void *self);
/**
* Initialize the code generator for a graph
* @param irg A graph
*/
void (*init_graph)(ir_graph *irg);
/**
* Get the ABI restrictions for procedure calls.
* @param call_type The call type of the method (procedure) in question.
......@@ -465,7 +459,8 @@ struct arch_isa_if_t {
void (*handle_intrinsics)(ir_graph *irg);
/**
* Called, when the graph is being normalized.
* Initialize a graph for codegeneration. Code selection is usually
* performed in this step.
*/
void (*prepare_graph)(ir_graph *irg);
......
ir/be/bemain.c
View file @ 97aa32b4
......@@ -79,7 +79,6 @@ static const arch_isa_if_t *isa_if = NULL;
static const lc_opt_enum_mask_items_t dump_items[] = {
{ "none", DUMP_NONE },
{ "initial", DUMP_INITIAL },
{ "abi", DUMP_ABI },
{ "sched", DUMP_SCHED },
{ "prepared", DUMP_PREPARED },
{ "regalloc", DUMP_RA },
......@@ -570,22 +569,9 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
}
be_timer_pop(T_VERIFY);
/* get a code generator for this graph. */
if (arch_env->impl->init_graph)
arch_env->impl->init_graph(irg);
dump(DUMP_PREPARED, irg, "before-code-selection");
/* perform codeselection */
be_timer_push(T_CODEGEN);
/* prepare and perform codeselection */
if (arch_env->impl->prepare_graph != NULL)
arch_env->impl->prepare_graph(irg);
be_timer_pop(T_CODEGEN);
dump(DUMP_PREPARED, irg, "code-selection");
/* disabled for now, fails for EmptyFor.c and XXEndless.c */
/* be_live_chk_compare(irg); */
/* schedule the irg */
be_timer_push(T_SCHED);
......
ir/be/ia32/bearch_ia32.c
View file @ 97aa32b4
......@@ -428,54 +428,6 @@ static const arch_irn_ops_t ia32_irn_ops = {
static int gprof = 0;
/**
* Transforms the standard firm graph into
* an ia32 firm graph
*/
static void ia32_prepare_graph(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
#ifdef FIRM_GRGEN_BE
switch (be_transformer) {
case TRANSFORMER_DEFAULT:
/* transform remaining nodes into assembler instructions */
ia32_transform_graph(irg);
break;
case TRANSFORMER_PBQP:
case TRANSFORMER_RAND:
/* transform nodes into assembler instructions by PBQP magic */
ia32_transform_graph_by_pbqp(irg);
break;
default:
panic("invalid transformer");
}
#else
ia32_transform_graph(irg);
#endif
/* do local optimizations (mainly CSE) */
optimize_graph_df(irg);
/* backend code expects that outedges are always enabled */
assure_edges(irg);
if (irg_data->dump)
dump_ir_graph(irg, "transformed");
/* optimize address mode */
ia32_optimize_graph(irg);
/* do code placement, to optimize the position of constants */
place_code(irg);
/* backend code expects that outedges are always enabled */
assure_edges(irg);
if (irg_data->dump)
dump_ir_graph(irg, "place");
}
ir_node *ia32_turn_back_am(ir_node *node)
{
dbg_info *dbgi = get_irn_dbg_info(node);
......@@ -1115,9 +1067,9 @@ static void ia32_emit(ir_graph *irg)
}
/**
* Initializes a IA32 code generator.
* Prepare a graph and perform code selection.
*/
static void ia32_init_graph(ir_graph *irg)
static void ia32_prepare_graph(ir_graph *irg)
{
struct obstack *obst = be_get_be_obst(irg);
ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
......@@ -1147,6 +1099,51 @@ static void ia32_init_graph(ir_graph *irg)
be_abi_introduce(irg);
if (irg_data->dump)
dump_ir_graph(irg, "abi");
be_timer_push(T_CODEGEN);
#ifdef FIRM_GRGEN_BE
switch (be_transformer) {
case TRANSFORMER_DEFAULT:
/* transform remaining nodes into assembler instructions */
ia32_transform_graph(irg);
break;
case TRANSFORMER_PBQP:
case TRANSFORMER_RAND:
/* transform nodes into assembler instructions by PBQP magic */
ia32_transform_graph_by_pbqp(irg);
break;
default:
panic("invalid transformer");
}
#else
ia32_transform_graph(irg);
#endif
be_timer_pop(T_CODEGEN);
if (irg_data->dump)
dump_ir_graph(irg, "code-selection");
/* do local optimizations (mainly CSE) */
optimize_graph_df(irg);
/* backend code expects that outedges are always enabled */
assure_edges(irg);
/* optimize address mode */
ia32_optimize_graph(irg);
if (irg_data->dump)
dump_ir_graph(irg, "opt");
/* do code placement, to optimize the position of constants */
place_code(irg);
/* backend code expects that outedges are always enabled */
assure_edges(irg);
if (irg_data->dump)
dump_ir_graph(irg, "place");
}
static const tarval_mode_info mo_integer = {
......@@ -1903,7 +1900,6 @@ const arch_isa_if_t ia32_isa_if = {
ia32_begin_codegeneration,
ia32_end_codegeneration,
ia32_init_graph,
ia32_get_call_abi,
ia32_mark_remat,
be_new_spill,
......
ir/be/sparc/bearch_sparc.c
View file @ 97aa32b4
......@@ -181,12 +181,15 @@ const arch_irn_ops_t sparc_irn_ops = {
};
/**
* Transforms the standard firm graph into
* a SPARC firm graph
* Transforms the standard firm graph into a SPARC firm graph
*/
static void sparc_prepare_graph(ir_graph *irg)
{
be_timer_push(T_CODEGEN);
sparc_transform_graph(irg);
be_timer_pop(T_CODEGEN);
if (be_options.dump_flags & DUMP_BE)
dump_ir_graph(irg, "code-selection");
}
static bool sparc_modifies_flags(const ir_node *node)
......@@ -629,7 +632,6 @@ const arch_isa_if_t sparc_isa_if = {
sparc_begin_codegeneration,
sparc_end_codegeneration,
NULL,
NULL, /* get call abi */
NULL, /* mark remat */
sparc_new_spill,
......
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