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Zwinkau
libfirm
Commits
9815fbf8
Commit
9815fbf8
authored
Jul 27, 2010
by
Matthias Braun
Browse files
draft for register width specifications
[r27828]
parent
1725b8d0
Changes
5
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Inline
Side-by-side
ir/be/bearch.c
View file @
9815fbf8
...
...
@@ -361,6 +361,7 @@ static const arch_register_req_t no_requirement = {
NULL
,
NULL
,
0
,
0
,
0
};
const
arch_register_req_t
*
arch_no_register_req
=
&
no_requirement
;
ir/be/bearch.h
View file @
9815fbf8
...
...
@@ -84,12 +84,14 @@ typedef enum arch_register_req_type_t {
arch_register_req_type_should_be_same
=
1U
<<
2
,
/** The register must be unequal from some other at the node. */
arch_register_req_type_must_be_different
=
1U
<<
3
,
/** The registernumber should be aligned (in case of multiregister values)*/
arch_register_req_type_must_be_aligned
=
1U
<<
4
,
/** ignore while allocating registers */
arch_register_req_type_ignore
=
1U
<<
4
,
arch_register_req_type_ignore
=
1U
<<
5
,
/** the output produces a new value for the stack pointer
* (this is not really a constraint but a marker to guide the stackpointer
* rewiring logic) */
arch_register_req_type_produces_sp
=
1U
<<
5
,
arch_register_req_type_produces_sp
=
1U
<<
6
,
}
arch_register_req_type_t
;
extern
const
arch_register_req_t
*
arch_no_register_req
;
...
...
@@ -337,6 +339,8 @@ struct arch_register_req_t {
unsigned
other_different
;
/**< Bitmask of ins which shall use a
different register
(must_be_different) */
unsigned
char
width
;
/**< specifies how many sequential
registers are required */
};
static
inline
int
reg_reqs_equal
(
const
arch_register_req_t
*
req1
,
...
...
ir/be/ia32/ia32_common_transform.c
View file @
9815fbf8
...
...
@@ -48,14 +48,6 @@ ia32_code_gen_t *env_cg = NULL;
heights_t
*
heights
=
NULL
;
static
const
arch_register_req_t
no_register_req
=
{
arch_register_req_type_none
,
NULL
,
/* regclass */
NULL
,
/* limit bitset */
0
,
/* same pos */
0
/* different pos */
};
static
int
check_immediate_constraint
(
long
val
,
char
immediate_constraint_type
)
{
switch
(
immediate_constraint_type
)
{
...
...
@@ -854,7 +846,7 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint,
/* pure memory ops */
if
(
constraint
->
cls
==
NULL
)
{
return
&
no_register_req
;
return
arch_
no_register_req
;
}
if
(
constraint
->
allowed_registers
!=
0
...
...
ir/be/scripts/generate_new_opcodes.pl
View file @
9815fbf8
...
...
@@ -1282,7 +1282,8 @@ sub generate_requirements {
NULL, /* regclass */
NULL, /* limit bitset */
0, /* same pos */
0 /* different pos */
0, /* different pos */
0 /* width */
};
EOF
...
...
@@ -1296,7 +1297,8 @@ EOF
& ${arch}_reg_classes[CLASS_${arch}_${class}],
NULL, /* limit bitset */
0, /* same pos */
0 /* different pos */
0, /* different pos */
1 /* width */
};
EOF
...
...
@@ -1331,7 +1333,8 @@ EOF
& ${arch}_reg_classes[CLASS_${arch}_${class}],
${limit_bitset},
${same_pos}, /* same pos */
${different_pos} /* different pos */
${different_pos}, /* different pos */
1 /* width */
};
EOF
...
...
ir/be/scripts/generate_regalloc_if.pl
View file @
9815fbf8
...
...
@@ -194,7 +194,8 @@ static const arch_register_req_t ${arch}_class_reg_req_${old_classname} = {
&${arch}_reg_classes[CLASS_${arch}_${old_classname}],
NULL,
0,
0
0,
1
};
EOF
...
...
@@ -236,7 +237,8 @@ static const arch_register_req_t ${arch}_single_reg_req_${old_classname}_${name}
${class_ptr},
${arch}_limited_${old_classname}_${name},
0,
0
0,
1
};
EOF
...
...
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