Commit 99f23ed8 authored by Matthias Braun's avatar Matthias Braun
Browse files

cleanup fragile op handling

- The pns of X_regular and X_except are annotated in the opcode now.
- The memory input is annotated in the opcode now
- only nodes with X_regular, X_except are marked fragile
parent 5a2faef9
......@@ -273,16 +273,6 @@ typedef enum ir_builtin_kind {
ir_bk_inner_trampoline, /**< address of a trampoline for GCC inner functions */
} ir_builtin_kind;
/**
* Some projection numbers must be always equal to support automatic phi construction
*/
enum pn_generic {
pn_Generic_M = 0, /**< The memory result. */
pn_Generic_X_regular = 1, /**< Execution result if no exception occurred. */
pn_Generic_X_except = 2, /**< The control flow result branching to the exception handler */
pn_Generic_other = 3 /**< First free projection number */
};
/**
* Possible return values of value_classify().
*/
......
......@@ -478,6 +478,16 @@ FIRM_API void set_binop_left(ir_node *node, ir_node *left);
FIRM_API ir_node *get_binop_right(const ir_node *node);
FIRM_API void set_binop_right(ir_node *node, ir_node *right);
/**
* Test wether a node is the X_except Proj of a fragile operation
*/
FIRM_API int is_x_except_Proj(const ir_node *node);
/**
* Test wether a node is the X_regular Proj of a fragile operation
*/
FIRM_API int is_x_regular_Proj(const ir_node *node);
/** returns the name of an ir_relation */
FIRM_API const char *get_relation_string(ir_relation relation);
......
......@@ -60,8 +60,9 @@ typedef enum {
irop_flag_labeled = 1U << 0, /**< If set, output edge labels on in-edges in vcg graph. */
irop_flag_commutative = 1U << 1, /**< This operation is commutative. */
irop_flag_cfopcode = 1U << 2, /**< This operation is a control flow operation. */
irop_flag_fragile = 1U << 3, /**< Set if the operation can change the control flow because
of an exception. */
irop_flag_fragile = 1U << 3, /**< Set if the operation can change the
control flow because of an exception.
*/
irop_flag_forking = 1U << 4, /**< Forking control flow at this operation. */
irop_flag_highlevel = 1U << 5, /**< This operation is a pure high-level one and can be
skipped in low-level optimizations. */
......@@ -280,6 +281,13 @@ FIRM_API ir_op *new_ir_op(unsigned code, const char *name, op_pin_state p,
unsigned flags, op_arity opar, int op_index,
size_t attr_size, const ir_op_ops *ops);
/**
* Set proj-number for X_regular and X_except projs of fragile nodes.
* Note: should only be used immediately after new_ir_op
*/
FIRM_API void ir_op_set_fragile_indices(ir_op *op, int fragile_mem_index,
int pn_x_regular, int pn_x_except);
/** Returns the ir_op_ops of an ir_op. */
FIRM_API const ir_op_ops *get_op_ops(const ir_op *op);
......
......@@ -343,7 +343,7 @@ static void construct_interval_block(ir_node *blk, ir_loop *l)
cfop = get_Block_cfgpred(blk, i);
if (is_Proj(cfop)) {
ir_node *op = skip_Proj(cfop);
if (is_fragile_op(op) && get_Proj_proj(cfop) == pn_Generic_X_except) {
if (is_x_except_Proj(cfop)) {
/*
* Skip the Proj for the exception flow only, leave the
* not exception flow Proj's intact.
......
......@@ -233,7 +233,7 @@ Jmp => {
# Load / Store
Load => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
irn_flags => [ "rematerializable" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "none" ], out => [ "gp" ] },
......@@ -241,7 +241,7 @@ Load => {
},
Store => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
irn_flags => [ "rematerializable" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ] },
......@@ -301,7 +301,7 @@ fConst => {
# Load / Store
fLoad => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
irn_flags => [ "rematerializable" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "none" ], out => [ "fp" ] },
......@@ -309,7 +309,7 @@ fLoad => {
},
fStore => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
irn_flags => [ "rematerializable" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "fp", "none" ] },
......
......@@ -272,7 +272,7 @@ Jcc => {
mode => "mode_T",
},
Load => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "none" ],
out => [ "gp", "none" ] },
......@@ -292,7 +292,7 @@ FrameAddr => {
mode => $mode_gp,
},
Store => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "ptr", "val", "mem" ],
......
......@@ -351,7 +351,6 @@ EmptyReg => {
},
CopyB => {
op_flags => [ "fragile" ],
state => "pinned",
attr => "unsigned size",
attr_type => "arm_CopyB_attr_t",
......@@ -425,7 +424,7 @@ SwitchJmp => {
},
Ldr => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
ins => [ "ptr", "mem" ],
outs => [ "res", "M" ],
......@@ -436,7 +435,7 @@ Ldr => {
},
Str => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
ins => [ "ptr", "val", "mem" ],
outs => [ "M" ],
......@@ -448,7 +447,7 @@ Str => {
},
StoreStackM4Inc => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
irn_flags => [ "rematerializable" ],
state => "exc_pinned",
reg_req => { in => [ "sp", "gp", "gp", "gp", "gp", "none" ], out => [ "sp:I|S", "none" ] },
......@@ -457,7 +456,7 @@ StoreStackM4Inc => {
},
LoadStackM3Epilogue => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
irn_flags => [ "rematerializable" ],
state => "exc_pinned",
reg_req => { in => [ "sp", "none" ], out => [ "r11:I", "sp:I|S", "pc:I", "none" ] },
......@@ -532,7 +531,7 @@ Cmfe => {
},
Ldf => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
ins => [ "ptr", "mem" ],
outs => [ "res", "M" ],
......@@ -543,7 +542,7 @@ Ldf => {
},
Stf => {
op_flags => [ "labeled", "fragile" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
ins => [ "ptr", "val", "mem" ],
outs => [ "M" ],
......
......@@ -594,9 +594,9 @@ IDiv => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
out => [ "eax", "flags", "none", "edx", "none" ] },
out => [ "eax", "flags", "none", "edx", "none", "none" ] },
ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
outs => [ "div_res", "flags", "M", "mod_res", "X_regular", "X_except" ],
am => "source,unary",
emit => ". idiv%M %unop3",
latency => 25,
......@@ -608,9 +608,9 @@ Div => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
out => [ "eax", "flags", "none", "edx", "none" ] },
out => [ "eax", "flags", "none", "edx", "none", "none" ] },
ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
outs => [ "div_res", "flags", "M", "mod_res", "X_regular", "X_except" ],
am => "source,unary",
emit => ". div%M %unop3",
latency => 25,
......@@ -1152,7 +1152,7 @@ ChangeCW => {
},
FldCW => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "fpcw:I" ] },
ins => [ "base", "index", "mem" ],
......@@ -1164,7 +1164,7 @@ FldCW => {
},
FnstCW => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "pinned",
reg_req => { in => [ "gp", "gp", "none", "fp_cw" ], out => [ "none" ] },
ins => [ "base", "index", "mem", "fpcw" ],
......@@ -1175,7 +1175,7 @@ FnstCW => {
},
FnstCWNOP => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "pinned",
reg_req => { in => [ "fp_cw" ], out => [ "none" ] },
ins => [ "fpcw" ],
......@@ -1203,9 +1203,9 @@ Load => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ],
out => [ "gp", "none", "none", "none" ] },
out => [ "gp", "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem" ],
outs => [ "res", "unused", "M", "X_exc" ],
outs => [ "res", "unused", "M", "X_regular", "X_except" ],
latency => 0,
emit => ". mov%EX%.l %AM, %D0",
units => [ "GP" ],
......@@ -1214,9 +1214,10 @@ Load => {
Store => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none", "none" ] },
reg_req => { in => [ "gp", "gp", "none", "gp" ],
out => [ "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_exc" ],
outs => [ "M", "X_regular", "X_except" ],
emit => '. mov%M %SI3, %AM',
latency => 2,
units => [ "GP" ],
......@@ -1226,9 +1227,10 @@ Store => {
Store8Bit => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none", "none" ] },
reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ],
out => ["none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_exc" ],
outs => [ "M", "X_regular", "X_except" ],
emit => '. mov%M %SB3, %AM',
latency => 2,
units => [ "GP" ],
......@@ -1554,7 +1556,7 @@ Inport => {
# Intel style prefetching
#
Prefetch0 => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "base", "index", "mem" ],
......@@ -1565,7 +1567,7 @@ Prefetch0 => {
},
Prefetch1 => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "base", "index", "mem" ],
......@@ -1576,7 +1578,7 @@ Prefetch1 => {
},
Prefetch2 => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "base", "index", "mem" ],
......@@ -1587,7 +1589,7 @@ Prefetch2 => {
},
PrefetchNTA => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "base", "index", "mem" ],
......@@ -1601,7 +1603,7 @@ PrefetchNTA => {
# 3DNow! prefetch instructions
#
Prefetch => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "base", "index", "mem" ],
......@@ -1612,7 +1614,7 @@ Prefetch => {
},
PrefetchW => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "base", "index", "mem" ],
......@@ -1860,9 +1862,9 @@ xLoad => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ],
out => [ "xmm", "none", "none", "none" ] },
out => [ "xmm", "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem" ],
outs => [ "res", "unused", "M", "X_exc" ],
outs => [ "res", "unused", "M", "X_regular", "X_except" ],
emit => '. mov%XXM %AM, %D0',
attr => "ir_mode *load_mode",
init_attr => "attr->ls_mode = load_mode;",
......@@ -1873,9 +1875,10 @@ xLoad => {
xStore => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none", "none" ] },
reg_req => { in => [ "gp", "gp", "none", "xmm" ],
out => [ "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_exc" ],
outs => [ "M", "X_regular", "X_except" ],
emit => '. mov%XXM %S3, %AM',
latency => 0,
units => [ "SSE" ],
......@@ -1885,9 +1888,10 @@ xStore => {
xStoreSimple => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none" ] },
reg_req => { in => [ "gp", "gp", "none", "xmm" ],
out => [ "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M" ],
outs => [ "M", "X_regular", "X_except" ],
emit => '. mov%XXM %S3, %AM',
latency => 0,
units => [ "SSE" ],
......@@ -1895,7 +1899,7 @@ xStoreSimple => {
},
CvtSI2SS => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
ins => [ "base", "index", "mem", "val" ],
......@@ -1907,7 +1911,7 @@ CvtSI2SS => {
},
CvtSI2SD => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
ins => [ "base", "index", "mem", "val" ],
......@@ -1920,14 +1924,14 @@ CvtSI2SD => {
l_LLtoFloat => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
cmp_attr => "return 1;",
ins => [ "val_high", "val_low" ],
reg_req => { in => [ "none", "none" ], out => [ "none" ] }
},
l_FloattoLL => {
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
cmp_attr => "return 1;",
ins => [ "val" ],
outs => [ "res_high", "res_low" ],
......@@ -1937,12 +1941,14 @@ l_FloattoLL => {
CopyB => {
op_flags => [ "fragile" ],
state => "pinned",
reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
outs => [ "DST", "SRC", "CNT", "M" ],
reg_req => { in => [ "edi", "esi", "ecx", "none" ],
out => [ "edi", "esi", "ecx", "none", "none", "none" ] },
ins => [ "dest", "source", "count", "mem" ],
outs => [ "dest", "source", "count", "M", "X_regular", "X_except" ],
attr_type => "ia32_copyb_attr_t",
attr => "unsigned size",
units => [ "GP" ],
latency => 3,
latency => 3,
# we don't care about this flag, so no need to mark this node
# modified_flags => [ "DF" ]
},
......@@ -1950,12 +1956,14 @@ CopyB => {
CopyB_i => {
op_flags => [ "fragile" ],
state => "pinned",
reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
outs => [ "DST", "SRC", "M" ],
reg_req => { in => [ "edi", "esi", "none" ],
out => [ "edi", "esi", "none", "none", "none" ] },
ins => [ "dest", "source", "mem" ],
outs => [ "dest", "source", "M", "X_regular", "X_except" ],
attr_type => "ia32_copyb_attr_t",
attr => "unsigned size",
units => [ "GP" ],
latency => 3,
latency => 3,
# we don't care about this flag, so no need to mark this node
# modified_flags => [ "DF" ]
},
......@@ -2120,9 +2128,9 @@ vfld => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ],
out => [ "vfp", "none", "none", "none" ] },
out => [ "vfp", "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem" ],
outs => [ "res", "unused", "M", "X_exc" ],
outs => [ "res", "unused", "M", "X_regular", "X_except" ],
attr => "ir_mode *load_mode",
init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
......@@ -2135,9 +2143,9 @@ vfst => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp" ],
out => [ "none", "none" ] },
out => [ "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_exc" ],
outs => [ "M", "X_regular", "X_except" ],
attr => "ir_mode *store_mode",
init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
......@@ -2441,7 +2449,7 @@ fchs => {
fld => {
irn_flags => [ "rematerializable" ],
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
emit => '. fld%XM %AM',
attr_type => "ia32_x87_attr_t",
......@@ -2451,7 +2459,7 @@ fld => {
fst => {
irn_flags => [ "rematerializable" ],
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
emit => '. fst%XM %AM',
mode => "mode_M",
......@@ -2462,7 +2470,7 @@ fst => {
fstp => {
irn_flags => [ "rematerializable" ],
op_flags => [ "fragile", "labeled" ],
op_flags => [ "labeled" ],
state => "exc_pinned",
emit => '. fstp%XM %AM',
mode => "mode_M",
......@@ -2693,9 +2701,11 @@ FtstFnstsw => {
xxLoad => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
reg_req => { in => [ "gp", "gp", "none" ],
out => [ "xmm", "none", "none", "none" ] },
emit => '. movdqu %D0, %AM',
outs => [ "res", "M" ],
ins => [ "base", "index", "mem" ],
outs => [ "res", "M", "X_regular", "X_except" ],
units => [ "SSE" ],
latency => 1,
},
......@@ -2703,11 +2713,13 @@ xxLoad => {
xxStore => {
op_flags => [ "fragile", "labeled" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
reg_req => { in => [ "gp", "gp", "none", "xmm" ],
out => [ "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_regular", "X_except" ],
emit => '. movdqu %binop',
units => [ "SSE" ],
latency => 1,
latency => 1,
mode => "mode_M",
},
......
......@@ -4522,10 +4522,9 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node)
static ir_node *gen_Proj_Load(ir_node *node)
{
ir_node *new_pred;
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
ir_node *pred = get_Proj_pred(node);
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
/* loads might be part of source address mode matches, so we don't
* transform the ProjMs yet (with the exception of loads whose result is
......@@ -4546,18 +4545,18 @@ static ir_node *gen_Proj_Load(ir_node *node)
/* renumber the proj */
new_pred = be_transform_node(pred);
if (is_ia32_Load(new_pred)) {
switch (proj) {
switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
case pn_Load_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc);
default:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except);
case pn_Load_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
case pn_Load_max:
break;
}
} else if (is_ia32_Conv_I2I(new_pred) ||
......@@ -4569,33 +4568,33 @@ static ir_node *gen_Proj_Load(ir_node *node)
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
}
} else if (is_ia32_xLoad(new_pred)) {
switch (proj) {
switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
case pn_Load_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc);
default:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except);
case pn_Load_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
case pn_Load_max:
break;
}
} else if (is_ia32_vfld(new_pred)) {
switch (proj) {
switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
case pn_Load_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc);
default:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except);
case pn_Load_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular);
case pn_Load_max:
break;
}
} else {
......@@ -4619,16 +4618,15 @@ static ir_node *gen_Proj_Load(ir_node *node)
*/
static ir_node *gen_Proj_Div(ir_node *node)
{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);