Commit 9efd8c48 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

be: Add and use 'be_mode_needs_gp_reg()'.

parent a4c2839c
......@@ -33,14 +33,6 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
typedef ir_node* (*new_binop_func)(dbg_info *dbgi, ir_node *block,
ir_node *left, ir_node *right);
/**
* returns true if mode should be stored in a general purpose register
*/
static inline bool mode_needs_gp_reg(ir_mode *mode)
{
return get_mode_arithmetic(mode) == irma_twos_complement;
}
static ir_node *transform_const(ir_node *const node, ir_entity *const entity, ir_tarval *const value)
{
ir_node *const block = be_transform_nodes_block(node);
......@@ -271,7 +263,7 @@ static ir_node *gen_Phi(ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
const arch_register_req_t *req;
if (mode_needs_gp_reg(mode)) {
if (be_mode_needs_gp_reg(mode)) {
req = TEMPLATE_reg_classes[CLASS_TEMPLATE_gp].class_req;
} else {
req = arch_memory_req;
......
......@@ -16,6 +16,7 @@
#include "amd64_transform.h"
#include "be.h"
#include "besched.h"
#include "betranshlp.h"
#include "bitfiddle.h"
#include "gen_amd64_regalloc_if.h"
#include "ident.h"
......@@ -297,7 +298,7 @@ void amd64_lower_va_arg(ir_node *node)
ir_node *max;
ir_entity *offset_entity;
ir_node *stride;
if (mode_is_int(resmode) || mode_is_reference(resmode)) {
if (be_mode_needs_gp_reg(resmode)) {
max = new_r_Const_long(irg, mode_Is, n_gp_args * gp_size);
offset_entity = va_list_members.gp_offset;
stride = new_r_Const_long(irg, mode_Is, gp_size);
......
......@@ -19,6 +19,7 @@
#include "beemithlp.h"
#include "beemitter.h"
#include "bemodule.h"
#include "betranshlp.h"
#include "dbginfo.h"
#include "entity_t.h"
#include "execfreq.h"
......@@ -740,7 +741,7 @@ static void emit_init_expression(ir_node *const init)
return;
case iro_Add:
if (!mode_is_int(mode) && !mode_is_reference(mode))
if (!be_mode_needs_gp_reg(mode))
panic("constant must be int or pointer for '+' to work");
emit_init_expression(get_Add_left(init));
be_emit_cstring(" + ");
......@@ -748,7 +749,7 @@ static void emit_init_expression(ir_node *const init)
return;
case iro_Sub:
if (!mode_is_int(mode) && !mode_is_reference(mode))
if (!be_mode_needs_gp_reg(mode))
panic("constant must be int or pointer for '-' to work");
emit_init_expression(get_Sub_left(init));
be_emit_cstring(" - ");
......
......@@ -821,14 +821,9 @@ uint32_t be_get_tv_bits32(ir_tarval *const tv, unsigned const offset)
return val;
}
static bool mode_needs_gp_reg(ir_mode *const mode)
{
return get_mode_arithmetic(mode) == irma_twos_complement;
}
ir_node *be_skip_downconv(ir_node *node, bool const single_user)
{
assert(mode_needs_gp_reg(get_irn_mode(node)));
assert(be_mode_needs_gp_reg(get_irn_mode(node)));
for (;;) {
if (single_user && get_irn_n_edges(node) > 1) {
/* we only want to skip the conv when we're the only user
......@@ -838,7 +833,7 @@ ir_node *be_skip_downconv(ir_node *node, bool const single_user)
} else if (is_Conv(node)) {
ir_node *const op = get_Conv_op(node);
ir_mode *const src_mode = get_irn_mode(op);
if (!mode_needs_gp_reg(src_mode) || get_mode_size_bits(get_irn_mode(node)) > get_mode_size_bits(src_mode))
if (!be_mode_needs_gp_reg(src_mode) || get_mode_size_bits(get_irn_mode(node)) > get_mode_size_bits(src_mode))
break;
node = op;
} else {
......@@ -850,7 +845,7 @@ ir_node *be_skip_downconv(ir_node *node, bool const single_user)
ir_node *be_skip_sameconv(ir_node *node)
{
assert(mode_needs_gp_reg(get_irn_mode(node)));
assert(be_mode_needs_gp_reg(get_irn_mode(node)));
for (;;) {
if (get_irn_n_edges(node) > 1) {
/* we only want to skip the conv when we're the only user
......@@ -860,7 +855,7 @@ ir_node *be_skip_sameconv(ir_node *node)
} else if (is_Conv(node)) {
ir_node *const op = get_Conv_op(node);
ir_mode *const src_mode = get_irn_mode(op);
if (!mode_needs_gp_reg(src_mode) || get_mode_size_bits(get_irn_mode(node)) != get_mode_size_bits(src_mode))
if (!be_mode_needs_gp_reg(src_mode) || get_mode_size_bits(get_irn_mode(node)) != get_mode_size_bits(src_mode))
break;
node = op;
} else {
......
......@@ -177,4 +177,12 @@ bool be_match_immediate(ir_node const *node, ir_tarval **tarval_out,
ir_node *be_make_Sync(ir_node *block, int arity, ir_node **ins);
/**
* Returns true if mode should be stored in a general purpose register
*/
static inline bool be_mode_needs_gp_reg(ir_mode *const mode)
{
return get_mode_arithmetic(mode) == irma_twos_complement;
}
#endif
......@@ -18,6 +18,7 @@
#include "besched.h"
#include "bespillslots.h"
#include "bestack.h"
#include "betranshlp.h"
#include "beutil.h"
#include "bevarargs.h"
#include "gen_ia32_regalloc_if.h"
......@@ -1226,8 +1227,7 @@ static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
{
(void)sel;
ir_mode *mode = get_irn_mode(mux_true);
if (!mode_is_int(mode) && !mode_is_reference(mode)
&& mode != mode_b)
if (!be_mode_needs_gp_reg(mode) && mode != mode_b)
return false;
/* we can create a set plus up two 3 instructions for any combination
......
......@@ -154,11 +154,6 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, dbg_info *dbgi, ir_node *bloc
static ir_node *nomem;
static ir_node *noreg_GP;
static bool mode_needs_gp_reg(ir_mode *mode)
{
return get_mode_arithmetic(mode) == irma_twos_complement;
}
/** Return non-zero is a node represents the 0 constant. */
static bool is_Const_0(ir_node *node)
{
......@@ -569,7 +564,7 @@ static ir_node *gen_Unknown(ir_node *node)
} else {
res = new_bd_ia32_fldz(dbgi, block);
}
} else if (mode_needs_gp_reg(mode)) {
} else if (be_mode_needs_gp_reg(mode)) {
res = new_bd_ia32_Unknown(dbgi, block);
} else {
panic("unsupported Unknown-Mode");
......@@ -961,7 +956,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block,
use_am = false;
}
if (mode_needs_gp_reg(mode)) {
if (be_mode_needs_gp_reg(mode)) {
if (flags & match_mode_neutral) {
/* we can simply skip downconvs for mode neutral nodes: the upper bits
* can be random for these operations */
......@@ -1240,7 +1235,7 @@ static ir_node *skip_shift_amount_conv(ir_node *n)
while (is_Conv(n) && get_irn_n_edges(n) == 1) {
ir_node *const op = get_Conv_op(n);
ir_mode *const mode = get_irn_mode(op);
if (!mode_needs_gp_reg(mode))
if (!be_mode_needs_gp_reg(mode))
break;
assert(get_mode_size_bits(mode) >= 5);
n = op;
......@@ -2439,7 +2434,7 @@ static ir_node *try_create_dest_am(ir_node *node)
ir_mode *mode = get_irn_mode(val);
/* handle only GP modes for now... */
if (!mode_needs_gp_reg(mode))
if (!be_mode_needs_gp_reg(mode))
return NULL;
/* store must be the only user of the val node */
......@@ -3043,7 +3038,7 @@ static ir_node *gen_Cmp(ir_node *node)
return create_Fucom(node);
}
}
assert(mode_needs_gp_reg(cmp_mode));
assert(be_mode_needs_gp_reg(cmp_mode));
/* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
ia32_address_mode_t am;
......@@ -3121,7 +3116,7 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
ir_node *val_true = get_Mux_true(node);
ir_node *val_false = get_Mux_false(node);
assert(ia32_cg_config.use_cmov);
assert(mode_needs_gp_reg(get_irn_mode(val_true)));
assert(be_mode_needs_gp_reg(get_irn_mode(val_true)));
ia32_address_mode_t am;
ir_node *block = get_nodes_block(node);
......@@ -3434,7 +3429,7 @@ static ir_node *gen_Mux(ir_node *node)
int is_abs = ir_mux_is_abs(sel, mux_false, mux_true);
if (is_abs != 0) {
if (mode_needs_gp_reg(mode)) {
if (be_mode_needs_gp_reg(mode)) {
be_warningf(node, "integer abs not transformed");
} else {
ir_node *op = ir_get_abs_op(sel, mux_false, mux_true);
......@@ -3545,7 +3540,7 @@ static ir_node *gen_Mux(ir_node *node)
panic("cannot transform floating point Mux");
} else {
assert(mode_needs_gp_reg(mode));
assert(be_mode_needs_gp_reg(mode));
if (is_Cmp(sel)) {
ir_node *cmp_left = get_Cmp_left(sel);
......@@ -4229,7 +4224,7 @@ static ir_node *gen_Phi(ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
const arch_register_req_t *req;
if (mode_needs_gp_reg(mode)) {
if (be_mode_needs_gp_reg(mode)) {
/* we shouldn't have any 64bit stuff around anymore */
assert(get_mode_size_bits(mode) <= 32);
/* all integer operations are on 32bit registers now */
......
......@@ -379,7 +379,7 @@ static void mark_non_address_nodes(ir_node *node, void *env)
be_lv_t *lv = (be_lv_t*)env;
ir_mode *mode = get_irn_mode(node);
if (!mode_is_int(mode) && !mode_is_reference(mode) && mode != mode_b)
if (!be_mode_needs_gp_reg(mode) && mode != mode_b)
return;
switch (get_irn_opcode(node)) {
......
......@@ -68,16 +68,6 @@ static const arch_register_t *const omit_fp_callee_saves[] = {
&sparc_registers[REG_I5],
};
static inline bool mode_needs_gp_reg(ir_mode *mode)
{
if (mode_is_int(mode) || mode_is_reference(mode)) {
/* we should only see 32bit code */
assert(get_mode_size_bits(mode) <= 32);
return true;
}
return false;
}
/**
* Create an And that will zero out upper bits.
*
......@@ -1499,7 +1489,7 @@ static ir_node *gen_Unknown(ir_node *node)
if (mode_is_float(mode)) {
ir_node *block = be_transform_nodes_block(node);
return gen_float_const(NULL, block, get_mode_null(mode));
} else if (mode_needs_gp_reg(mode)) {
} else if (be_mode_needs_gp_reg(mode)) {
ir_graph *irg = get_irn_irg(node);
return get_g0(irg);
}
......@@ -1942,7 +1932,7 @@ static ir_node *gen_Phi(ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
const arch_register_req_t *req;
if (mode_needs_gp_reg(mode)) {
if (be_mode_needs_gp_reg(mode)) {
/* we shouldn't have any 64bit stuff around anymore */
assert(get_mode_size_bits(mode) <= 32);
/* all integer operations are on 32bit registers now */
......@@ -1995,10 +1985,8 @@ static ir_node *gen_compare_swap(ir_node *node)
ir_mode *mode = get_irn_mode(old);
assert(get_irn_mode(new) == mode);
if ((!mode_is_int(mode) && !mode_is_reference(mode))
|| get_mode_size_bits(mode) != 32) {
if (be_mode_needs_gp_reg(mode) || get_mode_size_bits(mode) != 32)
panic("compare and swap only allowed for 32bit values");
}
return cas;
}
......
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